Lines Matching +full:0 +full:x444
124 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
199 #define ICE_PTP_CLOCK_INDEX_0 0x00
200 #define ICE_PTP_CLOCK_INDEX_1 0x01
207 #define GLTSYN_CMD_INIT_TIME BIT(0)
209 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
215 #define PHY_CMD_INIT_TIME BIT(0)
217 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
218 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
219 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
221 #define TS_CMD_MASK_E810 0xFF
222 #define TS_CMD_MASK 0xF
223 #define SYNC_EXEC_CMD 0x3
226 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
227 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
228 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
229 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
232 #define Q_0_BASE 0x94000
233 #define Q_1_BASE 0x114000
236 #define Q_REG_TS_CTRL 0x618
237 #define Q_REG_TS_CTRL_S 0
238 #define Q_REG_TS_CTRL_M BIT(0)
241 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
242 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
245 #define Q_REG_FIFO23_STATUS 0xCF8
246 #define Q_REG_FIFO01_STATUS 0xCFC
247 #define Q_REG_FIFO02_S 0
248 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
250 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
253 #define Q_REG_TX_MEM_GBL_CFG 0xC08
254 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
255 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
257 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
259 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
264 #define Q_REG_TX_MEMORY_BANK_START 0xA00
267 #define P_0_BASE 0x80000
268 #define P_4_BASE 0x106000
271 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
272 #define P_REG_RX_TIMER_INC_PRE_U 0x470
273 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
274 #define P_REG_TX_TIMER_INC_PRE_U 0x450
277 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
278 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
279 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
280 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
283 #define P_REG_RX_CAPTURE_L 0x4D8
284 #define P_REG_RX_CAPTURE_U 0x4DC
285 #define P_REG_TX_CAPTURE_L 0x4B4
286 #define P_REG_TX_CAPTURE_U 0x4B8
289 #define P_REG_TIMETUS_L 0x410
290 #define P_REG_TIMETUS_U 0x414
292 #define P_REG_40B_LOW_M 0xFF
296 #define P_REG_WL 0x40C
298 #define PTP_VERNIER_WL 0x111ed
301 #define P_REG_PS 0x408
302 #define P_REG_PS_START_S 0
303 #define P_REG_PS_START_M BIT(0)
314 #define P_REG_TX_OV_STATUS 0x4D4
315 #define P_REG_TX_OV_STATUS_OV_S 0
316 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
317 #define P_REG_RX_OV_STATUS 0x4F8
318 #define P_REG_RX_OV_STATUS_OV_S 0
319 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
322 #define P_REG_TX_OR 0x45C
323 #define P_REG_RX_OR 0x47C
326 #define P_REG_TOTAL_RX_OFFSET_L 0x460
327 #define P_REG_TOTAL_RX_OFFSET_U 0x464
328 #define P_REG_TOTAL_TX_OFFSET_L 0x440
329 #define P_REG_TOTAL_TX_OFFSET_U 0x444
332 #define P_REG_UIX66_10G_40G_L 0x480
333 #define P_REG_UIX66_10G_40G_U 0x484
334 #define P_REG_UIX66_25G_100G_L 0x488
335 #define P_REG_UIX66_25G_100G_U 0x48C
336 #define P_REG_DESK_PAR_RX_TUS_L 0x490
337 #define P_REG_DESK_PAR_RX_TUS_U 0x494
338 #define P_REG_DESK_PAR_TX_TUS_L 0x498
339 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
340 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
341 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
342 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
343 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
344 #define P_REG_PAR_RX_TUS_L 0x420
345 #define P_REG_PAR_RX_TUS_U 0x424
346 #define P_REG_PAR_TX_TUS_L 0x428
347 #define P_REG_PAR_TX_TUS_U 0x42C
348 #define P_REG_PCS_RX_TUS_L 0x430
349 #define P_REG_PCS_RX_TUS_U 0x434
350 #define P_REG_PCS_TX_TUS_L 0x438
351 #define P_REG_PCS_TX_TUS_U 0x43C
352 #define P_REG_PAR_RX_TIME_L 0x4F0
353 #define P_REG_PAR_RX_TIME_U 0x4F4
354 #define P_REG_PAR_TX_TIME_L 0x4CC
355 #define P_REG_PAR_TX_TIME_U 0x4D0
356 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
357 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
358 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
359 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
360 #define P_REG_LINK_SPEED 0x4FC
361 #define P_REG_LINK_SPEED_SERDES_S 0
362 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
364 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
370 #define P_REG_PMD_ALIGNMENT 0x0FC
371 #define P_REG_RX_80_TO_160_CNT 0x6FC
372 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
373 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
374 #define P_REG_RX_40_TO_160_CNT 0x8FC
375 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
376 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
379 #define P_REG_RX_OV_FS 0x4F8
381 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
384 #define P_REG_TX_TMR_CMD 0x448
385 #define P_REG_RX_TMR_CMD 0x468
388 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
391 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
392 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
395 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
396 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
399 #define ETH_GLTSYN_CMD 0x03000344
402 #define INCVAL_HIGH_M 0xFF
405 #define TS_VALID BIT(0)
406 #define TS_LOW_M 0xFFFFFFFF
407 #define TS_HIGH_M 0xFF
410 #define TS_PHY_LOW_M 0xFF
411 #define TS_PHY_HIGH_M 0xFFFFFFFF
429 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
432 #define LOW_TX_MEMORY_BANK_START 0x03090000
433 #define HIGH_TX_MEMORY_BANK_START 0x03090004
455 #define ICE_PCA9575_P0_IN 0x0