Lines Matching +full:0 +full:x3e00
12 #define HINIC_CMDQ_CTRL_PI_SHIFT 0
18 #define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF
19 #define HINIC_CMDQ_CTRL_CMD_MASK 0xFF
20 #define HINIC_CMDQ_CTRL_MOD_MASK 0x1F
21 #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3
22 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1
32 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0
40 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF
41 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1
42 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1
43 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1
44 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3
45 #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3
46 #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1
56 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
61 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
62 #define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F
63 #define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1
64 #define HINIC_SQ_CTRL_LEN_MASK 0x3
75 #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF
76 #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1
77 #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1
78 #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1
79 #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF
80 #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1
81 #define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1
82 #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7
96 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
105 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF
106 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3
107 #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3
108 #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1
109 #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1
111 #define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1
112 #define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF
124 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF
125 #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF
126 #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF
132 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0
139 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF
140 #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF
141 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7
143 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3
154 #define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1
162 #define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1
164 #define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT 0
166 #define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK 0xFFFFU
178 #define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF
184 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
189 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
190 #define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1
191 #define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3
192 #define HINIC_RQ_CTRL_LEN_MASK 0x3
210 #define HINIC_MSS_DEFAULT 0x3E00
211 #define HINIC_MSS_MIN 0x50
214 #define RQ_CQE_STATUS_NUM_LRO_MASK 0xFFU
223 #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT 0
224 #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK 0xFFFU
226 #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK 0x1U
238 #define RQ_CQE_SGE_VLAN_MASK 0xFFFFU
239 #define RQ_CQE_SGE_VLAN_SHIFT 0
259 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
262 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
265 L3TYPE_UNKNOWN = 0,
272 OFFLOAD_DISABLE = 0,
285 HINIC_OUTER_L3TYPE_UNKNOWN = 0,
292 HINIC_L2TYPE_ETH = 0,