25 /* SGMII Control defines */
33 /* SGMII Device Ability for SGMII defines */
43 /* SGMII IF Mode defines */
496 	/* SGMII mode */  in setup_sgmii_internal_phy()
519 	/* Device ability according to SGMII specification */  in setup_sgmii_internal_phy()
523 	/* Adjust link timer for SGMII  -  in setup_sgmii_internal_phy()
524 	 * According to Cisco SGMII specification the timer should be 1.6 ms.  in setup_sgmii_internal_phy()
526 	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so  in setup_sgmii_internal_phy()
529 	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so  in setup_sgmii_internal_phy()
532 	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,  in setup_sgmii_internal_phy()
533 	 * we always set up here a value of 2.5 SGMII.  in setup_sgmii_internal_phy()
555 	/* Adjust link timer for SGMII  -  in setup_sgmii_internal_phy_base_x()
558 	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so  in setup_sgmii_internal_phy_base_x()
561 	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so  in setup_sgmii_internal_phy_base_x()
564 	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,  in setup_sgmii_internal_phy_base_x()
565 	 * we always set up here a value of 2.5 SGMII.  in setup_sgmii_internal_phy_base_x()
1038 		/* Configure internal SGMII PHY */  in memac_init()
1044 		/* Configure 4 internal SGMII PHYs */  in memac_init()