172 	u32 rctrl;		/* 0x050 Receive control register */  member
420 	iowrite32be(tmp, &regs->rctrl);  in init()
732 				iowrite32be(ioread32be(&regs->rctrl) |  in dtsec_isr()
733 					    RCTRL_GRS, &regs->rctrl);  in dtsec_isr()
822 	iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);  in graceful_start()
831 	tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;  in graceful_stop()
832 	iowrite32be(tmp, &regs->rctrl);  in graceful_stop()
983 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_add_hash_mac_address()
1043 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_allmulti()
1049 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_allmulti()
1057 	u32 rctrl, tctrl;  in dtsec_set_tstamp()  local
1062 	rctrl = ioread32be(&regs->rctrl);  in dtsec_set_tstamp()
1066 		rctrl |= RCTRL_RTSE;  in dtsec_set_tstamp()
1069 		rctrl &= ~RCTRL_RTSE;  in dtsec_set_tstamp()
1073 	iowrite32be(rctrl, &regs->rctrl);  in dtsec_set_tstamp()
1095 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_del_hash_mac_address()
1160 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1166 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1169 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1175 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()