Lines Matching +full:eee +full:- +full:broken +full:- +full:100 +full:tx
1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
90 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
174 .name = "imx25-fec",
177 .name = "imx27-fec",
180 .name = "imx28-fec",
183 .name = "imx6q-fec",
186 .name = "mvf600-fec",
189 .name = "imx6sx-fec",
192 .name = "imx6ul-fec",
195 .name = "imx8mq-fec",
198 .name = "imx8qm-fec",
201 .name = "s32v234-fec",
223 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
224 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
225 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
226 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
227 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
228 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
229 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
230 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
231 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
232 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
244 * if this is non-zero then assume it is the address to get MAC from.
266 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
320 #define FEC_MAX_TSO_SEGS 100
324 ((addr >= txq->tso_hdrs_dma) && \
325 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
332 return (bdp >= bd->last) ? bd->base in fec_enet_get_nextdesc()
333 : (struct bufdesc *)(((void *)bdp) + bd->dsize); in fec_enet_get_nextdesc()
339 return (bdp <= bd->base) ? bd->last in fec_enet_get_prevdesc()
340 : (struct bufdesc *)(((void *)bdp) - bd->dsize); in fec_enet_get_prevdesc()
346 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; in fec_enet_get_bd_index()
353 entries = (((const char *)txq->dirty_tx - in fec_enet_get_free_txdesc_num()
354 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; in fec_enet_get_free_txdesc_num()
356 return entries >= 0 ? entries : entries + txq->bd.ring_size; in fec_enet_get_free_txdesc_num()
385 netdev_info(ndev, "TX ring dump\n"); in fec_dump()
388 txq = fep->tx_queue[0]; in fec_dump()
389 bdp = txq->bd.base; in fec_dump()
394 bdp == txq->bd.cur ? 'S' : ' ', in fec_dump()
395 bdp == txq->dirty_tx ? 'H' : ' ', in fec_dump()
396 fec16_to_cpu(bdp->cbd_sc), in fec_dump()
397 fec32_to_cpu(bdp->cbd_bufaddr), in fec_dump()
398 fec16_to_cpu(bdp->cbd_datlen), in fec_dump()
399 txq->tx_skbuff[index]); in fec_dump()
400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_dump()
402 } while (bdp != txq->bd.base); in fec_dump()
407 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; in is_ipv4_pkt()
414 if (skb->ip_summed != CHECKSUM_PARTIAL) in fec_enet_clear_csum()
418 return -1; in fec_enet_clear_csum()
421 ip_hdr(skb)->check = 0; in fec_enet_clear_csum()
422 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; in fec_enet_clear_csum()
435 .nid = dev_to_node(&fep->pdev->dev), in fec_enet_create_page_pool()
436 .dev = &fep->pdev->dev, in fec_enet_create_page_pool()
443 rxq->page_pool = page_pool_create(&pp_params); in fec_enet_create_page_pool()
444 if (IS_ERR(rxq->page_pool)) { in fec_enet_create_page_pool()
445 err = PTR_ERR(rxq->page_pool); in fec_enet_create_page_pool()
446 rxq->page_pool = NULL; in fec_enet_create_page_pool()
450 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); in fec_enet_create_page_pool()
454 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, in fec_enet_create_page_pool()
455 rxq->page_pool); in fec_enet_create_page_pool()
462 xdp_rxq_info_unreg(&rxq->xdp_rxq); in fec_enet_create_page_pool()
464 page_pool_destroy(rxq->page_pool); in fec_enet_create_page_pool()
465 rxq->page_pool = NULL; in fec_enet_create_page_pool()
475 struct bufdesc *bdp = txq->bd.cur; in fec_enet_txq_submit_frag_skb()
477 int nr_frags = skb_shinfo(skb)->nr_frags; in fec_enet_txq_submit_frag_skb()
488 this_frag = &skb_shinfo(skb)->frags[frag]; in fec_enet_txq_submit_frag_skb()
489 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
492 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_submit_frag_skb()
495 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); in fec_enet_txq_submit_frag_skb()
498 if (frag == nr_frags - 1) { in fec_enet_txq_submit_frag_skb()
500 if (fep->bufdesc_ex) { in fec_enet_txq_submit_frag_skb()
502 if (unlikely(skb_shinfo(skb)->tx_flags & in fec_enet_txq_submit_frag_skb()
503 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) in fec_enet_txq_submit_frag_skb()
508 if (fep->bufdesc_ex) { in fec_enet_txq_submit_frag_skb()
509 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_submit_frag_skb()
510 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_submit_frag_skb()
511 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_submit_frag_skb()
514 ebdp->cbd_bdu = 0; in fec_enet_txq_submit_frag_skb()
515 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_submit_frag_skb()
520 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
521 if (((unsigned long) bufaddr) & fep->tx_align || in fec_enet_txq_submit_frag_skb()
522 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_submit_frag_skb()
523 memcpy(txq->tx_bounce[index], bufaddr, frag_len); in fec_enet_txq_submit_frag_skb()
524 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_submit_frag_skb()
526 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_submit_frag_skb()
530 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, in fec_enet_txq_submit_frag_skb()
532 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_submit_frag_skb()
534 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_submit_frag_skb()
538 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_submit_frag_skb()
539 bdp->cbd_datlen = cpu_to_fec16(frag_len); in fec_enet_txq_submit_frag_skb()
544 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_submit_frag_skb()
549 bdp = txq->bd.cur; in fec_enet_txq_submit_frag_skb()
551 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
552 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_txq_submit_frag_skb()
553 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); in fec_enet_txq_submit_frag_skb()
555 return ERR_PTR(-ENOMEM); in fec_enet_txq_submit_frag_skb()
562 int nr_frags = skb_shinfo(skb)->nr_frags; in fec_enet_txq_submit_skb()
580 /* Protocol checksum off-load for TCP and UDP. */ in fec_enet_txq_submit_skb()
586 /* Fill in a Tx ring entry */ in fec_enet_txq_submit_skb()
587 bdp = txq->bd.cur; in fec_enet_txq_submit_skb()
589 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_submit_skb()
593 bufaddr = skb->data; in fec_enet_txq_submit_skb()
596 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_skb()
597 if (((unsigned long) bufaddr) & fep->tx_align || in fec_enet_txq_submit_skb()
598 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_submit_skb()
599 memcpy(txq->tx_bounce[index], skb->data, buflen); in fec_enet_txq_submit_skb()
600 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_submit_skb()
602 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_submit_skb()
607 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); in fec_enet_txq_submit_skb()
608 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_submit_skb()
611 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_submit_skb()
618 dma_unmap_single(&fep->pdev->dev, addr, in fec_enet_txq_submit_skb()
625 if (fep->bufdesc_ex) { in fec_enet_txq_submit_skb()
627 if (unlikely(skb_shinfo(skb)->tx_flags & in fec_enet_txq_submit_skb()
628 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) in fec_enet_txq_submit_skb()
632 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_submit_skb()
633 bdp->cbd_datlen = cpu_to_fec16(buflen); in fec_enet_txq_submit_skb()
635 if (fep->bufdesc_ex) { in fec_enet_txq_submit_skb()
639 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && in fec_enet_txq_submit_skb()
640 fep->hwts_tx_en)) in fec_enet_txq_submit_skb()
641 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in fec_enet_txq_submit_skb()
643 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_submit_skb()
644 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_submit_skb()
646 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_submit_skb()
649 ebdp->cbd_bdu = 0; in fec_enet_txq_submit_skb()
650 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_submit_skb()
653 index = fec_enet_get_bd_index(last_bdp, &txq->bd); in fec_enet_txq_submit_skb()
655 txq->tx_skbuff[index] = skb; in fec_enet_txq_submit_skb()
666 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_submit_skb()
669 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); in fec_enet_txq_submit_skb()
674 * txq->bd.cur. in fec_enet_txq_submit_skb()
677 txq->bd.cur = bdp; in fec_enet_txq_submit_skb()
680 writel(0, txq->bd.reg_desc_active); in fec_enet_txq_submit_skb()
697 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_put_data_tso()
702 if (((unsigned long) data) & fep->tx_align || in fec_enet_txq_put_data_tso()
703 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_put_data_tso()
704 memcpy(txq->tx_bounce[index], data, size); in fec_enet_txq_put_data_tso()
705 data = txq->tx_bounce[index]; in fec_enet_txq_put_data_tso()
707 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_put_data_tso()
711 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); in fec_enet_txq_put_data_tso()
712 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_put_data_tso()
715 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_put_data_tso()
719 bdp->cbd_datlen = cpu_to_fec16(size); in fec_enet_txq_put_data_tso()
720 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_put_data_tso()
722 if (fep->bufdesc_ex) { in fec_enet_txq_put_data_tso()
723 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_put_data_tso()
724 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_put_data_tso()
725 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_put_data_tso()
727 ebdp->cbd_bdu = 0; in fec_enet_txq_put_data_tso()
728 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_put_data_tso()
736 if (fep->bufdesc_ex) in fec_enet_txq_put_data_tso()
737 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); in fec_enet_txq_put_data_tso()
740 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_put_data_tso()
758 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_put_hdr_tso()
762 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; in fec_enet_txq_put_hdr_tso()
763 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; in fec_enet_txq_put_hdr_tso()
764 if (((unsigned long)bufaddr) & fep->tx_align || in fec_enet_txq_put_hdr_tso()
765 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_put_hdr_tso()
766 memcpy(txq->tx_bounce[index], skb->data, hdr_len); in fec_enet_txq_put_hdr_tso()
767 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_put_hdr_tso()
769 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_put_hdr_tso()
772 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, in fec_enet_txq_put_hdr_tso()
774 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { in fec_enet_txq_put_hdr_tso()
777 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_put_hdr_tso()
782 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); in fec_enet_txq_put_hdr_tso()
783 bdp->cbd_datlen = cpu_to_fec16(hdr_len); in fec_enet_txq_put_hdr_tso()
785 if (fep->bufdesc_ex) { in fec_enet_txq_put_hdr_tso()
786 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_put_hdr_tso()
787 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_put_hdr_tso()
788 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_put_hdr_tso()
790 ebdp->cbd_bdu = 0; in fec_enet_txq_put_hdr_tso()
791 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_put_hdr_tso()
794 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_put_hdr_tso()
805 struct bufdesc *bdp = txq->bd.cur; in fec_enet_txq_submit_tso()
817 /* Protocol checksum off-load for TCP and UDP. */ in fec_enet_txq_submit_tso()
826 total_len = skb->len - hdr_len; in fec_enet_txq_submit_tso()
830 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_tso()
831 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); in fec_enet_txq_submit_tso()
832 total_len -= data_left; in fec_enet_txq_submit_tso()
835 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; in fec_enet_txq_submit_tso()
845 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_tso()
846 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_tso()
855 data_left -= size; in fec_enet_txq_submit_tso()
859 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_tso()
863 txq->tx_skbuff[index] = skb; in fec_enet_txq_submit_tso()
866 txq->bd.cur = bdp; in fec_enet_txq_submit_tso()
869 if (!(fep->quirks & FEC_QUIRK_ERR007885) || in fec_enet_txq_submit_tso()
870 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
871 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
872 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
873 !readl(txq->bd.reg_desc_active)) in fec_enet_txq_submit_tso()
874 writel(0, txq->bd.reg_desc_active); in fec_enet_txq_submit_tso()
894 txq = fep->tx_queue[queue]; in fec_enet_start_xmit()
905 if (entries_free <= txq->tx_stop_threshold) in fec_enet_start_xmit()
911 /* Init RX & TX buffer descriptors
922 for (q = 0; q < fep->num_rx_queues; q++) { in fec_enet_bd_init()
924 rxq = fep->rx_queue[q]; in fec_enet_bd_init()
925 bdp = rxq->bd.base; in fec_enet_bd_init()
927 for (i = 0; i < rxq->bd.ring_size; i++) { in fec_enet_bd_init()
930 if (bdp->cbd_bufaddr) in fec_enet_bd_init()
931 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); in fec_enet_bd_init()
933 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_bd_init()
934 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_bd_init()
938 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); in fec_enet_bd_init()
939 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_bd_init()
941 rxq->bd.cur = rxq->bd.base; in fec_enet_bd_init()
944 for (q = 0; q < fep->num_tx_queues; q++) { in fec_enet_bd_init()
946 txq = fep->tx_queue[q]; in fec_enet_bd_init()
947 bdp = txq->bd.base; in fec_enet_bd_init()
948 txq->bd.cur = bdp; in fec_enet_bd_init()
950 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_bd_init()
952 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_bd_init()
953 if (bdp->cbd_bufaddr && in fec_enet_bd_init()
954 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) in fec_enet_bd_init()
955 dma_unmap_single(&fep->pdev->dev, in fec_enet_bd_init()
956 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_bd_init()
957 fec16_to_cpu(bdp->cbd_datlen), in fec_enet_bd_init()
959 if (txq->tx_skbuff[i]) { in fec_enet_bd_init()
960 dev_kfree_skb_any(txq->tx_skbuff[i]); in fec_enet_bd_init()
961 txq->tx_skbuff[i] = NULL; in fec_enet_bd_init()
963 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_bd_init()
964 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_bd_init()
968 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); in fec_enet_bd_init()
969 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_bd_init()
970 txq->dirty_tx = bdp; in fec_enet_bd_init()
979 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_active_rxring()
980 writel(0, fep->rx_queue[i]->bd.reg_desc_active); in fec_enet_active_rxring()
990 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_enable_ring()
991 rxq = fep->rx_queue[i]; in fec_enet_enable_ring()
992 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); in fec_enet_enable_ring()
993 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); in fec_enet_enable_ring()
998 fep->hwp + FEC_RCMR(i)); in fec_enet_enable_ring()
1001 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_enable_ring()
1002 txq = fep->tx_queue[i]; in fec_enet_enable_ring()
1003 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); in fec_enet_enable_ring()
1008 fep->hwp + FEC_DMA_CFG(i)); in fec_enet_enable_ring()
1018 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_reset_skb()
1019 txq = fep->tx_queue[i]; in fec_enet_reset_skb()
1021 for (j = 0; j < txq->bd.ring_size; j++) { in fec_enet_reset_skb()
1022 if (txq->tx_skbuff[j]) { in fec_enet_reset_skb()
1023 dev_kfree_skb_any(txq->tx_skbuff[j]); in fec_enet_reset_skb()
1024 txq->tx_skbuff[j] = NULL; in fec_enet_reset_skb()
1047 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || in fec_restart()
1048 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { in fec_restart()
1049 writel(0, fep->hwp + FEC_ECNTRL); in fec_restart()
1051 writel(1, fep->hwp + FEC_ECNTRL); in fec_restart()
1056 * enet-mac reset will reset mac address registers too, in fec_restart()
1059 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); in fec_restart()
1061 fep->hwp + FEC_ADDR_LOW); in fec_restart()
1063 fep->hwp + FEC_ADDR_HIGH); in fec_restart()
1066 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); in fec_restart()
1072 /* Reset tx SKB buffers. */ in fec_restart()
1076 if (fep->full_duplex == DUPLEX_FULL) { in fec_restart()
1078 writel(0x04, fep->hwp + FEC_X_CNTRL); in fec_restart()
1082 writel(0x0, fep->hwp + FEC_X_CNTRL); in fec_restart()
1086 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_restart()
1089 if (fep->quirks & FEC_QUIRK_HAS_RACC) { in fec_restart()
1090 u32 val = readl(fep->hwp + FEC_RACC); in fec_restart()
1094 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) in fec_restart()
1099 writel(val, fep->hwp + FEC_RACC); in fec_restart()
1100 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); in fec_restart()
1106 * differently on enet-mac. in fec_restart()
1108 if (fep->quirks & FEC_QUIRK_ENET_MAC) { in fec_restart()
1113 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || in fec_restart()
1114 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || in fec_restart()
1115 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || in fec_restart()
1116 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) in fec_restart()
1118 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1123 /* 1G, 100M or 10M */ in fec_restart()
1124 if (ndev->phydev) { in fec_restart()
1125 if (ndev->phydev->speed == SPEED_1000) in fec_restart()
1127 else if (ndev->phydev->speed == SPEED_100) in fec_restart()
1134 if (fep->quirks & FEC_QUIRK_USE_GASKET) { in fec_restart()
1137 writel(0, fep->hwp + FEC_MIIGSK_ENR); in fec_restart()
1138 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) in fec_restart()
1146 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1148 if (ndev->phydev && ndev->phydev->speed == SPEED_10) in fec_restart()
1150 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
1152 /* re-enable the gasket */ in fec_restart()
1153 writel(2, fep->hwp + FEC_MIIGSK_ENR); in fec_restart()
1160 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || in fec_restart()
1161 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && in fec_restart()
1162 ndev->phydev && ndev->phydev->pause)) { in fec_restart()
1166 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); in fec_restart()
1167 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); in fec_restart()
1168 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); in fec_restart()
1169 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); in fec_restart()
1172 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); in fec_restart()
1178 writel(rcntl, fep->hwp + FEC_R_CNTRL); in fec_restart()
1183 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); in fec_restart()
1184 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); in fec_restart()
1187 if (fep->quirks & FEC_QUIRK_ENET_MAC) { in fec_restart()
1191 writel(1 << 8, fep->hwp + FEC_X_WMRK); in fec_restart()
1194 if (fep->bufdesc_ex) in fec_restart()
1197 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && in fec_restart()
1198 fep->rgmii_txc_dly) in fec_restart()
1200 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && in fec_restart()
1201 fep->rgmii_rxc_dly) in fec_restart()
1206 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); in fec_restart()
1210 writel(ecntl, fep->hwp + FEC_ECNTRL); in fec_restart()
1213 if (fep->bufdesc_ex) in fec_restart()
1217 if (fep->link) in fec_restart()
1218 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_restart()
1220 writel(0, fep->hwp + FEC_IMASK); in fec_restart()
1223 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) in fec_restart()
1234 return imx_scu_get_handle(&fep->ipc_handle); in fec_enet_ipc_handle_init()
1239 struct device_node *np = fep->pdev->dev.of_node; in fec_enet_ipg_stop_set()
1243 if (!np || !fep->ipc_handle) in fec_enet_ipg_stop_set()
1252 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); in fec_enet_ipg_stop_set()
1257 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; in fec_enet_stop_mode()
1258 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; in fec_enet_stop_mode()
1260 if (stop_gpr->gpr) { in fec_enet_stop_mode()
1262 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, in fec_enet_stop_mode()
1263 BIT(stop_gpr->bit), in fec_enet_stop_mode()
1264 BIT(stop_gpr->bit)); in fec_enet_stop_mode()
1266 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, in fec_enet_stop_mode()
1267 BIT(stop_gpr->bit), 0); in fec_enet_stop_mode()
1268 } else if (pdata && pdata->sleep_mode_enable) { in fec_enet_stop_mode()
1269 pdata->sleep_mode_enable(enabled); in fec_enet_stop_mode()
1279 writel(0, fep->hwp + FEC_IMASK); in fec_irqs_disable()
1286 writel(0, fep->hwp + FEC_IMASK); in fec_irqs_disable_except_wakeup()
1287 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); in fec_irqs_disable_except_wakeup()
1294 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); in fec_stop()
1298 if (fep->link) { in fec_stop()
1299 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ in fec_stop()
1301 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) in fec_stop()
1309 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { in fec_stop()
1310 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_stop()
1311 writel(0, fep->hwp + FEC_ECNTRL); in fec_stop()
1313 writel(1, fep->hwp + FEC_ECNTRL); in fec_stop()
1317 val = readl(fep->hwp + FEC_ECNTRL); in fec_stop()
1319 writel(val, fep->hwp + FEC_ECNTRL); in fec_stop()
1321 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_stop()
1322 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_stop()
1325 if (fep->quirks & FEC_QUIRK_ENET_MAC && in fec_stop()
1326 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { in fec_stop()
1327 writel(2, fep->hwp + FEC_ECNTRL); in fec_stop()
1328 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); in fec_stop()
1340 ndev->stats.tx_errors++; in fec_timeout()
1342 schedule_work(&fep->tx_timeout_work); in fec_timeout()
1349 struct net_device *ndev = fep->netdev; in fec_enet_timeout_work()
1353 napi_disable(&fep->napi); in fec_enet_timeout_work()
1358 napi_enable(&fep->napi); in fec_enet_timeout_work()
1370 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_enet_hwtstamp()
1371 ns = timecounter_cyc2time(&fep->tc, ts); in fec_enet_hwtstamp()
1372 spin_unlock_irqrestore(&fep->tmreg_lock, flags); in fec_enet_hwtstamp()
1375 hwtstamps->hwtstamp = ns_to_ktime(ns); in fec_enet_hwtstamp()
1392 txq = fep->tx_queue[queue_id]; in fec_enet_tx_queue()
1395 bdp = txq->dirty_tx; in fec_enet_tx_queue()
1398 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_tx_queue()
1400 while (bdp != READ_ONCE(txq->bd.cur)) { in fec_enet_tx_queue()
1403 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); in fec_enet_tx_queue()
1407 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_tx_queue()
1409 skb = txq->tx_skbuff[index]; in fec_enet_tx_queue()
1410 txq->tx_skbuff[index] = NULL; in fec_enet_tx_queue()
1411 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) in fec_enet_tx_queue()
1412 dma_unmap_single(&fep->pdev->dev, in fec_enet_tx_queue()
1413 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_tx_queue()
1414 fec16_to_cpu(bdp->cbd_datlen), in fec_enet_tx_queue()
1416 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_tx_queue()
1424 ndev->stats.tx_errors++; in fec_enet_tx_queue()
1426 ndev->stats.tx_heartbeat_errors++; in fec_enet_tx_queue()
1428 ndev->stats.tx_window_errors++; in fec_enet_tx_queue()
1430 ndev->stats.tx_aborted_errors++; in fec_enet_tx_queue()
1432 ndev->stats.tx_fifo_errors++; in fec_enet_tx_queue()
1434 ndev->stats.tx_carrier_errors++; in fec_enet_tx_queue()
1436 ndev->stats.tx_packets++; in fec_enet_tx_queue()
1437 ndev->stats.tx_bytes += skb->len; in fec_enet_tx_queue()
1444 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && in fec_enet_tx_queue()
1445 fep->hwts_tx_en) && in fec_enet_tx_queue()
1446 fep->bufdesc_ex) { in fec_enet_tx_queue()
1450 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); in fec_enet_tx_queue()
1458 ndev->stats.collisions++; in fec_enet_tx_queue()
1467 txq->dirty_tx = bdp; in fec_enet_tx_queue()
1470 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_tx_queue()
1476 if (entries_free >= txq->tx_wake_threshold) in fec_enet_tx_queue()
1482 if (bdp != txq->bd.cur && in fec_enet_tx_queue()
1483 readl(txq->bd.reg_desc_active) == 0) in fec_enet_tx_queue()
1484 writel(0, txq->bd.reg_desc_active); in fec_enet_tx_queue()
1493 for (i = fep->num_tx_queues - 1; i >= 0; i--) in fec_enet_tx()
1503 off = ((unsigned long)skb->data) & fep->rx_align; in fec_enet_new_rxbdp()
1505 skb_reserve(skb, fep->rx_align + 1 - off); in fec_enet_new_rxbdp()
1507 …bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fe… in fec_enet_new_rxbdp()
1508 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { in fec_enet_new_rxbdp()
1511 return -ENOMEM; in fec_enet_new_rxbdp()
1524 if (length > fep->rx_copybreak) in fec_enet_copybreak()
1531 dma_sync_single_for_cpu(&fep->pdev->dev, in fec_enet_copybreak()
1532 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_copybreak()
1533 FEC_ENET_RX_FRSIZE - fep->rx_align, in fec_enet_copybreak()
1536 memcpy(new_skb->data, (*skb)->data, length); in fec_enet_copybreak()
1538 swap_buffer2(new_skb->data, (*skb)->data, length); in fec_enet_copybreak()
1550 new_page = page_pool_dev_alloc_pages(rxq->page_pool); in fec_enet_update_cbd()
1552 rxq->rx_skb_info[index].page = new_page; in fec_enet_update_cbd()
1554 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; in fec_enet_update_cbd()
1556 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); in fec_enet_update_cbd()
1579 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; in fec_enet_rx_queue()
1585 rxq = fep->rx_queue[queue_id]; in fec_enet_rx_queue()
1590 bdp = rxq->bd.cur; in fec_enet_rx_queue()
1592 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { in fec_enet_rx_queue()
1598 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); in fec_enet_rx_queue()
1605 ndev->stats.rx_errors++; in fec_enet_rx_queue()
1608 ndev->stats.rx_fifo_errors++; in fec_enet_rx_queue()
1614 ndev->stats.rx_length_errors++; in fec_enet_rx_queue()
1619 ndev->stats.rx_crc_errors++; in fec_enet_rx_queue()
1622 ndev->stats.rx_frame_errors++; in fec_enet_rx_queue()
1627 ndev->stats.rx_packets++; in fec_enet_rx_queue()
1628 pkt_len = fec16_to_cpu(bdp->cbd_datlen); in fec_enet_rx_queue()
1629 ndev->stats.rx_bytes += pkt_len; in fec_enet_rx_queue()
1631 index = fec_enet_get_bd_index(bdp, &rxq->bd); in fec_enet_rx_queue()
1632 page = rxq->rx_skb_info[index].page; in fec_enet_rx_queue()
1633 dma_sync_single_for_cpu(&fep->pdev->dev, in fec_enet_rx_queue()
1634 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_rx_queue()
1646 skb_put(skb, pkt_len - 4); in fec_enet_rx_queue()
1648 data = skb->data; in fec_enet_rx_queue()
1654 if (fep->quirks & FEC_QUIRK_HAS_RACC) in fec_enet_rx_queue()
1660 if (fep->bufdesc_ex) in fec_enet_rx_queue()
1665 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && in fec_enet_rx_queue()
1666 fep->bufdesc_ex && in fec_enet_rx_queue()
1667 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { in fec_enet_rx_queue()
1671 vlan_tag = ntohs(vlan_header->h_vlan_TCI); in fec_enet_rx_queue()
1675 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); in fec_enet_rx_queue()
1679 skb->protocol = eth_type_trans(skb, ndev); in fec_enet_rx_queue()
1682 if (fep->hwts_rx_en && fep->bufdesc_ex) in fec_enet_rx_queue()
1683 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), in fec_enet_rx_queue()
1686 if (fep->bufdesc_ex && in fec_enet_rx_queue()
1687 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { in fec_enet_rx_queue()
1688 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { in fec_enet_rx_queue()
1690 skb->ip_summed = CHECKSUM_UNNECESSARY; in fec_enet_rx_queue()
1703 napi_gro_receive(&fep->napi, skb); in fec_enet_rx_queue()
1712 if (fep->bufdesc_ex) { in fec_enet_rx_queue()
1715 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); in fec_enet_rx_queue()
1716 ebdp->cbd_prot = 0; in fec_enet_rx_queue()
1717 ebdp->cbd_bdu = 0; in fec_enet_rx_queue()
1723 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_rx_queue()
1726 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_rx_queue()
1732 writel(0, rxq->bd.reg_desc_active); in fec_enet_rx_queue()
1734 rxq->bd.cur = bdp; in fec_enet_rx_queue()
1744 for (i = fep->num_rx_queues - 1; i >= 0; i--) in fec_enet_rx()
1745 done += fec_enet_rx_queue(ndev, budget - done, i); in fec_enet_rx()
1754 int_events = readl(fep->hwp + FEC_IEVENT); in fec_enet_collect_events()
1759 writel(int_events, fep->hwp + FEC_IEVENT); in fec_enet_collect_events()
1771 if (fec_enet_collect_events(fep) && fep->link) { in fec_enet_interrupt()
1774 if (napi_schedule_prep(&fep->napi)) { in fec_enet_interrupt()
1776 writel(0, fep->hwp + FEC_IMASK); in fec_enet_interrupt()
1777 __napi_schedule(&fep->napi); in fec_enet_interrupt()
1786 struct net_device *ndev = napi->dev; in fec_enet_rx_napi()
1791 done += fec_enet_rx(ndev, budget - done); in fec_enet_rx_napi()
1797 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_enet_rx_napi()
1803 /* ------------------------------------------------------------------------- */
1822 struct device_node *np = fep->pdev->dev.of_node; in fec_get_mac()
1827 else if (ret == -EPROBE_DEFER) in fec_get_mac()
1840 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); in fec_get_mac()
1843 iap = (unsigned char *)&pdata->mac; in fec_get_mac()
1852 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); in fec_get_mac()
1854 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); in fec_get_mac()
1863 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); in fec_get_mac()
1865 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", in fec_get_mac()
1866 ndev->dev_addr); in fec_get_mac()
1871 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); in fec_get_mac()
1876 /* ------------------------------------------------------------------------- */
1884 struct phy_device *phy_dev = ndev->phydev; in fec_enet_adjust_link()
1893 fep->link = 0; in fec_enet_adjust_link()
1894 } else if (phy_dev->link) { in fec_enet_adjust_link()
1895 if (!fep->link) { in fec_enet_adjust_link()
1896 fep->link = phy_dev->link; in fec_enet_adjust_link()
1900 if (fep->full_duplex != phy_dev->duplex) { in fec_enet_adjust_link()
1901 fep->full_duplex = phy_dev->duplex; in fec_enet_adjust_link()
1905 if (phy_dev->speed != fep->speed) { in fec_enet_adjust_link()
1906 fep->speed = phy_dev->speed; in fec_enet_adjust_link()
1912 napi_disable(&fep->napi); in fec_enet_adjust_link()
1917 napi_enable(&fep->napi); in fec_enet_adjust_link()
1920 if (fep->link) { in fec_enet_adjust_link()
1921 napi_disable(&fep->napi); in fec_enet_adjust_link()
1925 napi_enable(&fep->napi); in fec_enet_adjust_link()
1926 fep->link = phy_dev->link; in fec_enet_adjust_link()
1940 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, in fec_enet_mdio_wait()
1944 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); in fec_enet_mdio_wait()
1951 struct fec_enet_private *fep = bus->priv; in fec_enet_mdio_read()
1952 struct device *dev = &fep->pdev->dev; in fec_enet_mdio_read()
1968 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_read()
1973 netdev_err(fep->netdev, "MDIO address write timeout\n"); in fec_enet_mdio_read()
1989 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); in fec_enet_mdio_read()
1994 netdev_err(fep->netdev, "MDIO read timeout\n"); in fec_enet_mdio_read()
1998 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); in fec_enet_mdio_read()
2010 struct fec_enet_private *fep = bus->priv; in fec_enet_mdio_write()
2011 struct device *dev = &fep->pdev->dev; in fec_enet_mdio_write()
2027 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_write()
2032 netdev_err(fep->netdev, "MDIO address write timeout\n"); in fec_enet_mdio_write()
2045 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_write()
2050 netdev_err(fep->netdev, "MDIO write timeout\n"); in fec_enet_mdio_write()
2062 struct phy_device *phy_dev = ndev->phydev; in fec_enet_phy_reset_after_clk_enable()
2066 } else if (fep->phy_node) { in fec_enet_phy_reset_after_clk_enable()
2074 phy_dev = of_phy_find_device(fep->phy_node); in fec_enet_phy_reset_after_clk_enable()
2076 put_device(&phy_dev->mdio.dev); in fec_enet_phy_reset_after_clk_enable()
2086 ret = clk_prepare_enable(fep->clk_enet_out); in fec_enet_clk_enable()
2090 if (fep->clk_ptp) { in fec_enet_clk_enable()
2091 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2092 ret = clk_prepare_enable(fep->clk_ptp); in fec_enet_clk_enable()
2094 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2097 fep->ptp_clk_on = true; in fec_enet_clk_enable()
2099 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2102 ret = clk_prepare_enable(fep->clk_ref); in fec_enet_clk_enable()
2106 ret = clk_prepare_enable(fep->clk_2x_txclk); in fec_enet_clk_enable()
2112 clk_disable_unprepare(fep->clk_enet_out); in fec_enet_clk_enable()
2113 if (fep->clk_ptp) { in fec_enet_clk_enable()
2114 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2115 clk_disable_unprepare(fep->clk_ptp); in fec_enet_clk_enable()
2116 fep->ptp_clk_on = false; in fec_enet_clk_enable()
2117 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2119 clk_disable_unprepare(fep->clk_ref); in fec_enet_clk_enable()
2120 clk_disable_unprepare(fep->clk_2x_txclk); in fec_enet_clk_enable()
2126 if (fep->clk_ref) in fec_enet_clk_enable()
2127 clk_disable_unprepare(fep->clk_ref); in fec_enet_clk_enable()
2129 if (fep->clk_ptp) { in fec_enet_clk_enable()
2130 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2131 clk_disable_unprepare(fep->clk_ptp); in fec_enet_clk_enable()
2132 fep->ptp_clk_on = false; in fec_enet_clk_enable()
2133 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2136 clk_disable_unprepare(fep->clk_enet_out); in fec_enet_clk_enable()
2146 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ in fec_enet_parse_rgmii_delay()
2147 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { in fec_enet_parse_rgmii_delay()
2149 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); in fec_enet_parse_rgmii_delay()
2150 return -EINVAL; in fec_enet_parse_rgmii_delay()
2152 fep->rgmii_txc_dly = true; in fec_enet_parse_rgmii_delay()
2157 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { in fec_enet_parse_rgmii_delay()
2159 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); in fec_enet_parse_rgmii_delay()
2160 return -EINVAL; in fec_enet_parse_rgmii_delay()
2162 fep->rgmii_rxc_dly = true; in fec_enet_parse_rgmii_delay()
2176 int dev_id = fep->dev_id; in fec_enet_mii_probe()
2178 if (fep->phy_node) { in fec_enet_mii_probe()
2179 phy_dev = of_phy_connect(ndev, fep->phy_node, in fec_enet_mii_probe()
2181 fep->phy_interface); in fec_enet_mii_probe()
2184 return -ENODEV; in fec_enet_mii_probe()
2189 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) in fec_enet_mii_probe()
2191 if (dev_id--) in fec_enet_mii_probe()
2193 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); in fec_enet_mii_probe()
2199 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); in fec_enet_mii_probe()
2206 fep->phy_interface); in fec_enet_mii_probe()
2215 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { in fec_enet_mii_probe()
2224 phy_set_max_speed(phy_dev, 100); in fec_enet_mii_probe()
2226 fep->link = 0; in fec_enet_mii_probe()
2227 fep->full_duplex = 0; in fec_enet_mii_probe()
2229 phy_dev->mac_managed_pm = 1; in fec_enet_mii_probe()
2243 int err = -ENXIO; in fec_enet_mii_init()
2251 * - fec0 supports MII & RMII modes while fec1 only supports RMII in fec_enet_mii_init()
2252 * - fec0 acts as the 1588 time master while fec1 is slave in fec_enet_mii_init()
2253 * - external phys can only be configured by fec0 in fec_enet_mii_init()
2263 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { in fec_enet_mii_init()
2266 fep->mii_bus = fec0_mii_bus; in fec_enet_mii_init()
2270 return -ENOENT; in fec_enet_mii_init()
2274 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); in fec_enet_mii_init()
2276 of_property_read_u32(node, "clock-frequency", &bus_freq); in fec_enet_mii_init()
2278 "suppress-preamble"); in fec_enet_mii_init()
2285 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 in fec_enet_mii_init()
2289 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); in fec_enet_mii_init()
2290 if (fep->quirks & FEC_QUIRK_ENET_MAC) in fec_enet_mii_init()
2291 mii_speed--; in fec_enet_mii_init()
2293 dev_err(&pdev->dev, in fec_enet_mii_init()
2295 clk_get_rate(fep->clk_ipg)); in fec_enet_mii_init()
2296 err = -EINVAL; in fec_enet_mii_init()
2312 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; in fec_enet_mii_init()
2314 fep->phy_speed = mii_speed << 1 | holdtime << 8; in fec_enet_mii_init()
2317 fep->phy_speed |= BIT(7); in fec_enet_mii_init()
2319 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { in fec_enet_mii_init()
2322 * - writing MSCR: in fec_enet_mii_init()
2323 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & in fec_enet_mii_init()
2325 * - writing MMFR: in fec_enet_mii_init()
2326 * - mscr[7:0]_not_zero in fec_enet_mii_init()
2328 writel(0, fep->hwp + FEC_MII_DATA); in fec_enet_mii_init()
2331 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_enet_mii_init()
2334 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); in fec_enet_mii_init()
2336 fep->mii_bus = mdiobus_alloc(); in fec_enet_mii_init()
2337 if (fep->mii_bus == NULL) { in fec_enet_mii_init()
2338 err = -ENOMEM; in fec_enet_mii_init()
2342 fep->mii_bus->name = "fec_enet_mii_bus"; in fec_enet_mii_init()
2343 fep->mii_bus->read = fec_enet_mdio_read; in fec_enet_mii_init()
2344 fep->mii_bus->write = fec_enet_mdio_write; in fec_enet_mii_init()
2345 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", in fec_enet_mii_init()
2346 pdev->name, fep->dev_id + 1); in fec_enet_mii_init()
2347 fep->mii_bus->priv = fep; in fec_enet_mii_init()
2348 fep->mii_bus->parent = &pdev->dev; in fec_enet_mii_init()
2350 err = of_mdiobus_register(fep->mii_bus, node); in fec_enet_mii_init()
2358 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) in fec_enet_mii_init()
2359 fec0_mii_bus = fep->mii_bus; in fec_enet_mii_init()
2364 mdiobus_free(fep->mii_bus); in fec_enet_mii_init()
2372 if (--mii_cnt == 0) { in fec_enet_mii_remove()
2373 mdiobus_unregister(fep->mii_bus); in fec_enet_mii_remove()
2374 mdiobus_free(fep->mii_bus); in fec_enet_mii_remove()
2383 strscpy(info->driver, fep->pdev->dev.driver->name, in fec_enet_get_drvinfo()
2384 sizeof(info->driver)); in fec_enet_get_drvinfo()
2385 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); in fec_enet_get_drvinfo()
2394 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); in fec_enet_get_regs_len()
2479 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; in fec_enet_get_regs()
2480 struct device *dev = &fep->pdev->dev; in fec_enet_get_regs()
2506 regs->version = fec_enet_register_version; in fec_enet_get_regs()
2508 memset(buf, 0, regs->len); in fec_enet_get_regs()
2514 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) in fec_enet_get_regs()
2530 if (fep->bufdesc_ex) { in fec_enet_get_ts_info()
2532 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in fec_enet_get_ts_info()
2538 if (fep->ptp_clock) in fec_enet_get_ts_info()
2539 info->phc_index = ptp_clock_index(fep->ptp_clock); in fec_enet_get_ts_info()
2541 info->phc_index = -1; in fec_enet_get_ts_info()
2543 info->tx_types = (1 << HWTSTAMP_TX_OFF) | in fec_enet_get_ts_info()
2546 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in fec_enet_get_ts_info()
2561 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; in fec_enet_get_pauseparam()
2562 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; in fec_enet_get_pauseparam()
2563 pause->rx_pause = pause->tx_pause; in fec_enet_get_pauseparam()
2571 if (!ndev->phydev) in fec_enet_set_pauseparam()
2572 return -ENODEV; in fec_enet_set_pauseparam()
2574 if (pause->tx_pause != pause->rx_pause) { in fec_enet_set_pauseparam()
2576 "hardware only support enable/disable both tx and rx"); in fec_enet_set_pauseparam()
2577 return -EINVAL; in fec_enet_set_pauseparam()
2580 fep->pause_flag = 0; in fec_enet_set_pauseparam()
2582 /* tx pause must be same as rx pause */ in fec_enet_set_pauseparam()
2583 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; in fec_enet_set_pauseparam()
2584 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; in fec_enet_set_pauseparam()
2586 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, in fec_enet_set_pauseparam()
2587 pause->autoneg); in fec_enet_set_pauseparam()
2589 if (pause->autoneg) { in fec_enet_set_pauseparam()
2592 phy_start_aneg(ndev->phydev); in fec_enet_set_pauseparam()
2595 napi_disable(&fep->napi); in fec_enet_set_pauseparam()
2600 napi_enable(&fep->napi); in fec_enet_set_pauseparam()
2610 /* RMON TX */
2630 /* IEEE TX */
2680 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); in fec_enet_update_ethtool_stats()
2691 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); in fec_enet_get_ethtool_stats()
2718 return -EOPNOTSUPP; in fec_enet_get_sset_count()
2728 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); in fec_enet_clear_ethtool_stats()
2731 writel(0, fep->hwp + fec_stats[i].offset); in fec_enet_clear_ethtool_stats()
2734 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); in fec_enet_clear_ethtool_stats()
2756 return us * (fep->itr_clk_rate / 64000) / 1000; in fec_enet_us_to_itr_clock()
2766 if (!fep->rx_time_itr || !fep->rx_pkts_itr || in fec_enet_itr_coal_set()
2767 !fep->tx_time_itr || !fep->tx_pkts_itr) in fec_enet_itr_coal_set()
2777 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); in fec_enet_itr_coal_set()
2778 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); in fec_enet_itr_coal_set()
2779 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); in fec_enet_itr_coal_set()
2780 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); in fec_enet_itr_coal_set()
2785 writel(tx_itr, fep->hwp + FEC_TXIC0); in fec_enet_itr_coal_set()
2786 writel(rx_itr, fep->hwp + FEC_RXIC0); in fec_enet_itr_coal_set()
2787 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_enet_itr_coal_set()
2788 writel(tx_itr, fep->hwp + FEC_TXIC1); in fec_enet_itr_coal_set()
2789 writel(rx_itr, fep->hwp + FEC_RXIC1); in fec_enet_itr_coal_set()
2790 writel(tx_itr, fep->hwp + FEC_TXIC2); in fec_enet_itr_coal_set()
2791 writel(rx_itr, fep->hwp + FEC_RXIC2); in fec_enet_itr_coal_set()
2802 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) in fec_enet_get_coalesce()
2803 return -EOPNOTSUPP; in fec_enet_get_coalesce()
2805 ec->rx_coalesce_usecs = fep->rx_time_itr; in fec_enet_get_coalesce()
2806 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; in fec_enet_get_coalesce()
2808 ec->tx_coalesce_usecs = fep->tx_time_itr; in fec_enet_get_coalesce()
2809 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; in fec_enet_get_coalesce()
2820 struct device *dev = &fep->pdev->dev; in fec_enet_set_coalesce()
2823 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) in fec_enet_set_coalesce()
2824 return -EOPNOTSUPP; in fec_enet_set_coalesce()
2826 if (ec->rx_max_coalesced_frames > 255) { in fec_enet_set_coalesce()
2828 return -EINVAL; in fec_enet_set_coalesce()
2831 if (ec->tx_max_coalesced_frames > 255) { in fec_enet_set_coalesce()
2832 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); in fec_enet_set_coalesce()
2833 return -EINVAL; in fec_enet_set_coalesce()
2836 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); in fec_enet_set_coalesce()
2839 return -EINVAL; in fec_enet_set_coalesce()
2842 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); in fec_enet_set_coalesce()
2844 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); in fec_enet_set_coalesce()
2845 return -EINVAL; in fec_enet_set_coalesce()
2848 fep->rx_time_itr = ec->rx_coalesce_usecs; in fec_enet_set_coalesce()
2849 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; in fec_enet_set_coalesce()
2851 fep->tx_time_itr = ec->tx_coalesce_usecs; in fec_enet_set_coalesce()
2852 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; in fec_enet_set_coalesce()
2866 switch (tuna->id) { in fec_enet_get_tunable()
2868 *(u32 *)data = fep->rx_copybreak; in fec_enet_get_tunable()
2871 ret = -EINVAL; in fec_enet_get_tunable()
2885 switch (tuna->id) { in fec_enet_set_tunable()
2887 fep->rx_copybreak = *(u32 *)data; in fec_enet_set_tunable()
2890 ret = -EINVAL; in fec_enet_set_tunable()
2897 /* LPI Sleep Ts count base on tx clk (clk_ref).
2904 return us * (fep->clk_ref_rate / 1000) / 1000; in fec_enet_us_to_tx_cycle()
2910 struct ethtool_eee *p = &fep->eee; in fec_enet_eee_mode_set()
2915 ret = phy_init_eee(ndev->phydev, false); in fec_enet_eee_mode_set()
2919 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); in fec_enet_eee_mode_set()
2926 p->tx_lpi_enabled = enable; in fec_enet_eee_mode_set()
2927 p->eee_enabled = enable; in fec_enet_eee_mode_set()
2928 p->eee_active = enable; in fec_enet_eee_mode_set()
2930 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); in fec_enet_eee_mode_set()
2931 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); in fec_enet_eee_mode_set()
2940 struct ethtool_eee *p = &fep->eee; in fec_enet_get_eee()
2942 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) in fec_enet_get_eee()
2943 return -EOPNOTSUPP; in fec_enet_get_eee()
2946 return -ENETDOWN; in fec_enet_get_eee()
2948 edata->eee_enabled = p->eee_enabled; in fec_enet_get_eee()
2949 edata->eee_active = p->eee_active; in fec_enet_get_eee()
2950 edata->tx_lpi_timer = p->tx_lpi_timer; in fec_enet_get_eee()
2951 edata->tx_lpi_enabled = p->tx_lpi_enabled; in fec_enet_get_eee()
2953 return phy_ethtool_get_eee(ndev->phydev, edata); in fec_enet_get_eee()
2960 struct ethtool_eee *p = &fep->eee; in fec_enet_set_eee()
2963 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) in fec_enet_set_eee()
2964 return -EOPNOTSUPP; in fec_enet_set_eee()
2967 return -ENETDOWN; in fec_enet_set_eee()
2969 p->tx_lpi_timer = edata->tx_lpi_timer; in fec_enet_set_eee()
2971 if (!edata->eee_enabled || !edata->tx_lpi_enabled || in fec_enet_set_eee()
2972 !edata->tx_lpi_timer) in fec_enet_set_eee()
2980 return phy_ethtool_set_eee(ndev->phydev, edata); in fec_enet_set_eee()
2988 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { in fec_enet_get_wol()
2989 wol->supported = WAKE_MAGIC; in fec_enet_get_wol()
2990 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; in fec_enet_get_wol()
2992 wol->supported = wol->wolopts = 0; in fec_enet_get_wol()
3001 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) in fec_enet_set_wol()
3002 return -EINVAL; in fec_enet_set_wol()
3004 if (wol->wolopts & ~WAKE_MAGIC) in fec_enet_set_wol()
3005 return -EINVAL; in fec_enet_set_wol()
3007 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); in fec_enet_set_wol()
3008 if (device_may_wakeup(&ndev->dev)) in fec_enet_set_wol()
3009 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; in fec_enet_set_wol()
3011 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); in fec_enet_set_wol()
3048 struct phy_device *phydev = ndev->phydev; in fec_enet_ioctl()
3051 return -EINVAL; in fec_enet_ioctl()
3054 return -ENODEV; in fec_enet_ioctl()
3056 if (fep->bufdesc_ex) { in fec_enet_ioctl()
3081 for (q = 0; q < fep->num_rx_queues; q++) { in fec_enet_free_buffers()
3082 rxq = fep->rx_queue[q]; in fec_enet_free_buffers()
3083 for (i = 0; i < rxq->bd.ring_size; i++) in fec_enet_free_buffers()
3084 page_pool_release_page(rxq->page_pool, rxq->rx_skb_info[i].page); in fec_enet_free_buffers()
3086 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) in fec_enet_free_buffers()
3087 xdp_rxq_info_unreg(&rxq->xdp_rxq); in fec_enet_free_buffers()
3088 page_pool_destroy(rxq->page_pool); in fec_enet_free_buffers()
3089 rxq->page_pool = NULL; in fec_enet_free_buffers()
3092 for (q = 0; q < fep->num_tx_queues; q++) { in fec_enet_free_buffers()
3093 txq = fep->tx_queue[q]; in fec_enet_free_buffers()
3094 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_free_buffers()
3095 kfree(txq->tx_bounce[i]); in fec_enet_free_buffers()
3096 txq->tx_bounce[i] = NULL; in fec_enet_free_buffers()
3097 skb = txq->tx_skbuff[i]; in fec_enet_free_buffers()
3098 txq->tx_skbuff[i] = NULL; in fec_enet_free_buffers()
3110 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_free_queue()
3111 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { in fec_enet_free_queue()
3112 txq = fep->tx_queue[i]; in fec_enet_free_queue()
3113 dma_free_coherent(&fep->pdev->dev, in fec_enet_free_queue()
3114 txq->bd.ring_size * TSO_HEADER_SIZE, in fec_enet_free_queue()
3115 txq->tso_hdrs, in fec_enet_free_queue()
3116 txq->tso_hdrs_dma); in fec_enet_free_queue()
3119 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_free_queue()
3120 kfree(fep->rx_queue[i]); in fec_enet_free_queue()
3121 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_free_queue()
3122 kfree(fep->tx_queue[i]); in fec_enet_free_queue()
3132 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_alloc_queue()
3135 ret = -ENOMEM; in fec_enet_alloc_queue()
3139 fep->tx_queue[i] = txq; in fec_enet_alloc_queue()
3140 txq->bd.ring_size = TX_RING_SIZE; in fec_enet_alloc_queue()
3141 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; in fec_enet_alloc_queue()
3143 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; in fec_enet_alloc_queue()
3144 txq->tx_wake_threshold = in fec_enet_alloc_queue()
3145 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; in fec_enet_alloc_queue()
3147 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, in fec_enet_alloc_queue()
3148 txq->bd.ring_size * TSO_HEADER_SIZE, in fec_enet_alloc_queue()
3149 &txq->tso_hdrs_dma, in fec_enet_alloc_queue()
3151 if (!txq->tso_hdrs) { in fec_enet_alloc_queue()
3152 ret = -ENOMEM; in fec_enet_alloc_queue()
3157 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_alloc_queue()
3158 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), in fec_enet_alloc_queue()
3160 if (!fep->rx_queue[i]) { in fec_enet_alloc_queue()
3161 ret = -ENOMEM; in fec_enet_alloc_queue()
3165 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; in fec_enet_alloc_queue()
3166 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; in fec_enet_alloc_queue()
3185 rxq = fep->rx_queue[queue]; in fec_enet_alloc_rxq_buffers()
3186 bdp = rxq->bd.base; in fec_enet_alloc_rxq_buffers()
3188 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); in fec_enet_alloc_rxq_buffers()
3194 for (i = 0; i < rxq->bd.ring_size; i++) { in fec_enet_alloc_rxq_buffers()
3195 page = page_pool_dev_alloc_pages(rxq->page_pool); in fec_enet_alloc_rxq_buffers()
3200 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); in fec_enet_alloc_rxq_buffers()
3202 rxq->rx_skb_info[i].page = page; in fec_enet_alloc_rxq_buffers()
3203 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; in fec_enet_alloc_rxq_buffers()
3204 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); in fec_enet_alloc_rxq_buffers()
3206 if (fep->bufdesc_ex) { in fec_enet_alloc_rxq_buffers()
3208 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); in fec_enet_alloc_rxq_buffers()
3211 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_alloc_rxq_buffers()
3215 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); in fec_enet_alloc_rxq_buffers()
3216 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_alloc_rxq_buffers()
3221 return -ENOMEM; in fec_enet_alloc_rxq_buffers()
3232 txq = fep->tx_queue[queue]; in fec_enet_alloc_txq_buffers()
3233 bdp = txq->bd.base; in fec_enet_alloc_txq_buffers()
3234 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_alloc_txq_buffers()
3235 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); in fec_enet_alloc_txq_buffers()
3236 if (!txq->tx_bounce[i]) in fec_enet_alloc_txq_buffers()
3239 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_alloc_txq_buffers()
3240 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_alloc_txq_buffers()
3242 if (fep->bufdesc_ex) { in fec_enet_alloc_txq_buffers()
3244 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); in fec_enet_alloc_txq_buffers()
3247 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_alloc_txq_buffers()
3251 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); in fec_enet_alloc_txq_buffers()
3252 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_alloc_txq_buffers()
3258 return -ENOMEM; in fec_enet_alloc_txq_buffers()
3266 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_alloc_buffers()
3268 return -ENOMEM; in fec_enet_alloc_buffers()
3270 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_alloc_buffers()
3272 return -ENOMEM; in fec_enet_alloc_buffers()
3283 ret = pm_runtime_resume_and_get(&fep->pdev->dev); in fec_enet_open()
3287 pinctrl_pm_select_default_state(&fep->pdev->dev); in fec_enet_open()
3298 if (ndev->phydev && ndev->phydev->drv) in fec_enet_open()
3325 if (fep->quirks & FEC_QUIRK_ERR006687) in fec_enet_open()
3328 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) in fec_enet_open()
3329 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); in fec_enet_open()
3331 napi_enable(&fep->napi); in fec_enet_open()
3332 phy_start(ndev->phydev); in fec_enet_open()
3335 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & in fec_enet_open()
3345 pm_runtime_mark_last_busy(&fep->pdev->dev); in fec_enet_open()
3346 pm_runtime_put_autosuspend(&fep->pdev->dev); in fec_enet_open()
3347 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_enet_open()
3356 phy_stop(ndev->phydev); in fec_enet_close()
3359 napi_disable(&fep->napi); in fec_enet_close()
3364 phy_disconnect(ndev->phydev); in fec_enet_close()
3366 if (fep->quirks & FEC_QUIRK_ERR006687) in fec_enet_close()
3372 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) in fec_enet_close()
3373 cpu_latency_qos_remove_request(&fep->pm_qos_req); in fec_enet_close()
3375 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_enet_close()
3376 pm_runtime_mark_last_busy(&fep->pdev->dev); in fec_enet_close()
3377 pm_runtime_put_autosuspend(&fep->pdev->dev); in fec_enet_close()
3404 if (ndev->flags & IFF_PROMISC) { in set_multicast_list()
3405 tmp = readl(fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3407 writel(tmp, fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3411 tmp = readl(fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3413 writel(tmp, fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3415 if (ndev->flags & IFF_ALLMULTI) { in set_multicast_list()
3419 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); in set_multicast_list()
3420 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); in set_multicast_list()
3428 crc = ether_crc_le(ndev->addr_len, ha->addr); in set_multicast_list()
3433 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; in set_multicast_list()
3436 hash_high |= 1 << (hash - 32); in set_multicast_list()
3441 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); in set_multicast_list()
3442 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); in set_multicast_list()
3453 if (!is_valid_ether_addr(addr->sa_data)) in fec_set_mac_address()
3454 return -EADDRNOTAVAIL; in fec_set_mac_address()
3455 eth_hw_addr_set(ndev, addr->sa_data); in fec_set_mac_address()
3466 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | in fec_set_mac_address()
3467 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), in fec_set_mac_address()
3468 fep->hwp + FEC_ADDR_LOW); in fec_set_mac_address()
3469 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), in fec_set_mac_address()
3470 fep->hwp + FEC_ADDR_HIGH); in fec_set_mac_address()
3476 * fec_poll_controller - FEC Poll controller function
3488 if (fep->irq[i] > 0) { in fec_poll_controller()
3489 disable_irq(fep->irq[i]); in fec_poll_controller()
3490 fec_enet_interrupt(fep->irq[i], dev); in fec_poll_controller()
3491 enable_irq(fep->irq[i]); in fec_poll_controller()
3501 netdev_features_t changed = features ^ netdev->features; in fec_enet_set_netdev_features()
3503 netdev->features = features; in fec_enet_set_netdev_features()
3508 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; in fec_enet_set_netdev_features()
3510 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; in fec_enet_set_netdev_features()
3518 netdev_features_t changed = features ^ netdev->features; in fec_set_features()
3521 napi_disable(&fep->napi); in fec_set_features()
3528 napi_enable(&fep->napi); in fec_set_features()
3541 if (skb->protocol == htons(ETH_P_ALL)) { in fec_enet_get_raw_vlan_tci()
3542 vhdr = (struct vlan_ethhdr *)(skb->data); in fec_enet_get_raw_vlan_tci()
3543 vlan_TCI = ntohs(vhdr->h_vlan_TCI); in fec_enet_get_raw_vlan_tci()
3555 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) in fec_enet_select_queue()
3600 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : in fec_enet_init()
3607 fep->rx_align = 0xf; in fec_enet_init()
3608 fep->tx_align = 0xf; in fec_enet_init()
3610 fep->rx_align = 0x3; in fec_enet_init()
3611 fep->tx_align = 0x3; in fec_enet_init()
3613 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; in fec_enet_init()
3614 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; in fec_enet_init()
3615 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; in fec_enet_init()
3616 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; in fec_enet_init()
3619 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); in fec_enet_init()
3621 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); in fec_enet_init()
3629 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; in fec_enet_init()
3632 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, in fec_enet_init()
3635 ret = -ENOMEM; in fec_enet_init()
3648 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_init()
3649 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; in fec_enet_init()
3650 unsigned size = dsize * rxq->bd.ring_size; in fec_enet_init()
3652 rxq->bd.qid = i; in fec_enet_init()
3653 rxq->bd.base = cbd_base; in fec_enet_init()
3654 rxq->bd.cur = cbd_base; in fec_enet_init()
3655 rxq->bd.dma = bd_dma; in fec_enet_init()
3656 rxq->bd.dsize = dsize; in fec_enet_init()
3657 rxq->bd.dsize_log2 = dsize_log2; in fec_enet_init()
3658 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; in fec_enet_init()
3661 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); in fec_enet_init()
3664 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_init()
3665 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; in fec_enet_init()
3666 unsigned size = dsize * txq->bd.ring_size; in fec_enet_init()
3668 txq->bd.qid = i; in fec_enet_init()
3669 txq->bd.base = cbd_base; in fec_enet_init()
3670 txq->bd.cur = cbd_base; in fec_enet_init()
3671 txq->bd.dma = bd_dma; in fec_enet_init()
3672 txq->bd.dsize = dsize; in fec_enet_init()
3673 txq->bd.dsize_log2 = dsize_log2; in fec_enet_init()
3674 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; in fec_enet_init()
3677 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); in fec_enet_init()
3682 ndev->watchdog_timeo = TX_TIMEOUT; in fec_enet_init()
3683 ndev->netdev_ops = &fec_netdev_ops; in fec_enet_init()
3684 ndev->ethtool_ops = &fec_enet_ethtool_ops; in fec_enet_init()
3686 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); in fec_enet_init()
3687 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); in fec_enet_init()
3689 if (fep->quirks & FEC_QUIRK_HAS_VLAN) in fec_enet_init()
3691 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; in fec_enet_init()
3693 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { in fec_enet_init()
3697 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM in fec_enet_init()
3699 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; in fec_enet_init()
3702 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_enet_init()
3703 fep->tx_align = 0; in fec_enet_init()
3704 fep->rx_align = 0x3f; in fec_enet_init()
3707 ndev->hw_features = ndev->features; in fec_enet_init()
3711 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) in fec_enet_init()
3729 struct device_node *np = pdev->dev.of_node; in fec_reset_phy()
3734 err = of_property_read_u32(np, "phy-reset-duration", &msec); in fec_reset_phy()
3739 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); in fec_reset_phy()
3740 if (phy_reset == -EPROBE_DEFER) in fec_reset_phy()
3745 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); in fec_reset_phy()
3748 return -EINVAL; in fec_reset_phy()
3750 active_high = of_property_read_bool(np, "phy-reset-active-high"); in fec_reset_phy()
3752 err = devm_gpio_request_one(&pdev->dev, phy_reset, in fec_reset_phy()
3754 "phy-reset"); in fec_reset_phy()
3756 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); in fec_reset_phy()
3792 struct device_node *np = pdev->dev.of_node; in fec_enet_get_queue_num()
3799 /* parse the num of tx and rx queues */ in fec_enet_get_queue_num()
3800 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); in fec_enet_get_queue_num()
3802 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); in fec_enet_get_queue_num()
3805 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", in fec_enet_get_queue_num()
3812 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", in fec_enet_get_queue_num()
3838 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) in fec_enet_get_wakeup_irq()
3839 fep->wake_irq = fep->irq[2]; in fec_enet_get_wakeup_irq()
3841 fep->wake_irq = fep->irq[0]; in fec_enet_get_wakeup_irq()
3851 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); in fec_enet_init_stop_mode()
3855 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, in fec_enet_init_stop_mode()
3858 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); in fec_enet_init_stop_mode()
3862 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); in fec_enet_init_stop_mode()
3863 if (IS_ERR(fep->stop_gpr.gpr)) { in fec_enet_init_stop_mode()
3864 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); in fec_enet_init_stop_mode()
3865 ret = PTR_ERR(fep->stop_gpr.gpr); in fec_enet_init_stop_mode()
3866 fep->stop_gpr.gpr = NULL; in fec_enet_init_stop_mode()
3870 fep->stop_gpr.reg = out_val[1]; in fec_enet_init_stop_mode()
3871 fep->stop_gpr.bit = out_val[2]; in fec_enet_init_stop_mode()
3889 struct device_node *np = pdev->dev.of_node, *phy_node; in fec_probe()
3902 return -ENOMEM; in fec_probe()
3904 SET_NETDEV_DEV(ndev, &pdev->dev); in fec_probe()
3909 of_id = of_match_device(fec_dt_ids, &pdev->dev); in fec_probe()
3911 pdev->id_entry = of_id->data; in fec_probe()
3912 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; in fec_probe()
3914 fep->quirks = dev_info->quirks; in fec_probe()
3916 fep->netdev = ndev; in fec_probe()
3917 fep->num_rx_queues = num_rx_qs; in fec_probe()
3918 fep->num_tx_queues = num_tx_qs; in fec_probe()
3922 if (fep->quirks & FEC_QUIRK_HAS_GBIT) in fec_probe()
3923 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; in fec_probe()
3927 pinctrl_pm_select_default_state(&pdev->dev); in fec_probe()
3929 fep->hwp = devm_platform_ioremap_resource(pdev, 0); in fec_probe()
3930 if (IS_ERR(fep->hwp)) { in fec_probe()
3931 ret = PTR_ERR(fep->hwp); in fec_probe()
3935 fep->pdev = pdev; in fec_probe()
3936 fep->dev_id = dev_id++; in fec_probe()
3942 !of_property_read_bool(np, "fsl,err006687-workaround-present")) in fec_probe()
3943 fep->quirks |= FEC_QUIRK_ERR006687; in fec_probe()
3949 if (of_get_property(np, "fsl,magic-packet", NULL)) in fec_probe()
3950 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; in fec_probe()
3956 phy_node = of_parse_phandle(np, "phy-handle", 0); in fec_probe()
3960 dev_err(&pdev->dev, in fec_probe()
3961 "broken fixed-link specification\n"); in fec_probe()
3966 fep->phy_node = phy_node; in fec_probe()
3968 ret = of_get_phy_mode(pdev->dev.of_node, &interface); in fec_probe()
3970 pdata = dev_get_platdata(&pdev->dev); in fec_probe()
3972 fep->phy_interface = pdata->phy; in fec_probe()
3974 fep->phy_interface = PHY_INTERFACE_MODE_MII; in fec_probe()
3976 fep->phy_interface = interface; in fec_probe()
3983 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fec_probe()
3984 if (IS_ERR(fep->clk_ipg)) { in fec_probe()
3985 ret = PTR_ERR(fep->clk_ipg); in fec_probe()
3989 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in fec_probe()
3990 if (IS_ERR(fep->clk_ahb)) { in fec_probe()
3991 ret = PTR_ERR(fep->clk_ahb); in fec_probe()
3995 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); in fec_probe()
3998 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); in fec_probe()
3999 if (IS_ERR(fep->clk_enet_out)) { in fec_probe()
4000 ret = PTR_ERR(fep->clk_enet_out); in fec_probe()
4004 fep->ptp_clk_on = false; in fec_probe()
4005 mutex_init(&fep->ptp_clk_mutex); in fec_probe()
4008 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); in fec_probe()
4009 if (IS_ERR(fep->clk_ref)) { in fec_probe()
4010 ret = PTR_ERR(fep->clk_ref); in fec_probe()
4013 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); in fec_probe()
4016 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { in fec_probe()
4017 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); in fec_probe()
4018 if (IS_ERR(fep->clk_2x_txclk)) in fec_probe()
4019 fep->clk_2x_txclk = NULL; in fec_probe()
4022 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; in fec_probe()
4023 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); in fec_probe()
4024 if (IS_ERR(fep->clk_ptp)) { in fec_probe()
4025 fep->clk_ptp = NULL; in fec_probe()
4026 fep->bufdesc_ex = false; in fec_probe()
4033 ret = clk_prepare_enable(fep->clk_ipg); in fec_probe()
4036 ret = clk_prepare_enable(fep->clk_ahb); in fec_probe()
4040 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); in fec_probe()
4041 if (!IS_ERR(fep->reg_phy)) { in fec_probe()
4042 ret = regulator_enable(fep->reg_phy); in fec_probe()
4044 dev_err(&pdev->dev, in fec_probe()
4049 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { in fec_probe()
4050 ret = -EPROBE_DEFER; in fec_probe()
4053 fep->reg_phy = NULL; in fec_probe()
4056 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); in fec_probe()
4057 pm_runtime_use_autosuspend(&pdev->dev); in fec_probe()
4058 pm_runtime_get_noresume(&pdev->dev); in fec_probe()
4059 pm_runtime_set_active(&pdev->dev); in fec_probe()
4060 pm_runtime_enable(&pdev->dev); in fec_probe()
4067 if (fep->bufdesc_ex) in fec_probe()
4083 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, in fec_probe()
4084 0, pdev->name, ndev); in fec_probe()
4088 fep->irq[i] = irq; in fec_probe()
4101 pinctrl_pm_select_sleep_state(&pdev->dev); in fec_probe()
4103 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; in fec_probe()
4109 device_init_wakeup(&ndev->dev, fep->wol_flag & in fec_probe()
4112 if (fep->bufdesc_ex && fep->ptp_clock) in fec_probe()
4113 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); in fec_probe()
4115 fep->rx_copybreak = COPYBREAK_DEFAULT; in fec_probe()
4116 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); in fec_probe()
4118 pm_runtime_mark_last_busy(&pdev->dev); in fec_probe()
4119 pm_runtime_put_autosuspend(&pdev->dev); in fec_probe()
4130 pm_runtime_put_noidle(&pdev->dev); in fec_probe()
4131 pm_runtime_disable(&pdev->dev); in fec_probe()
4132 if (fep->reg_phy) in fec_probe()
4133 regulator_disable(fep->reg_phy); in fec_probe()
4135 clk_disable_unprepare(fep->clk_ahb); in fec_probe()
4137 clk_disable_unprepare(fep->clk_ipg); in fec_probe()
4148 dev_id--; in fec_probe()
4160 struct device_node *np = pdev->dev.of_node; in fec_drv_remove()
4163 ret = pm_runtime_resume_and_get(&pdev->dev); in fec_drv_remove()
4167 cancel_work_sync(&fep->tx_timeout_work); in fec_drv_remove()
4171 if (fep->reg_phy) in fec_drv_remove()
4172 regulator_disable(fep->reg_phy); in fec_drv_remove()
4176 of_node_put(fep->phy_node); in fec_drv_remove()
4178 clk_disable_unprepare(fep->clk_ahb); in fec_drv_remove()
4179 clk_disable_unprepare(fep->clk_ipg); in fec_drv_remove()
4180 pm_runtime_put_noidle(&pdev->dev); in fec_drv_remove()
4181 pm_runtime_disable(&pdev->dev); in fec_drv_remove()
4195 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) in fec_suspend()
4196 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; in fec_suspend()
4197 phy_stop(ndev->phydev); in fec_suspend()
4198 napi_disable(&fep->napi); in fec_suspend()
4203 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { in fec_suspend()
4205 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_suspend()
4208 if (fep->wake_irq > 0) { in fec_suspend()
4209 disable_irq(fep->wake_irq); in fec_suspend()
4210 enable_irq_wake(fep->wake_irq); in fec_suspend()
4217 fep->rpm_active = !pm_runtime_status_suspended(dev); in fec_suspend()
4218 if (fep->rpm_active) { in fec_suspend()
4228 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) in fec_suspend()
4229 regulator_disable(fep->reg_phy); in fec_suspend()
4234 if (fep->clk_enet_out || fep->reg_phy) in fec_suspend()
4235 fep->link = 0; in fec_suspend()
4247 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { in fec_resume()
4248 ret = regulator_enable(fep->reg_phy); in fec_resume()
4255 if (fep->rpm_active) in fec_resume()
4263 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { in fec_resume()
4265 if (fep->wake_irq) { in fec_resume()
4266 disable_irq_wake(fep->wake_irq); in fec_resume()
4267 enable_irq(fep->wake_irq); in fec_resume()
4270 val = readl(fep->hwp + FEC_ECNTRL); in fec_resume()
4272 writel(val, fep->hwp + FEC_ECNTRL); in fec_resume()
4273 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; in fec_resume()
4275 pinctrl_pm_select_default_state(&fep->pdev->dev); in fec_resume()
4281 napi_enable(&fep->napi); in fec_resume()
4282 phy_init_hw(ndev->phydev); in fec_resume()
4283 phy_start(ndev->phydev); in fec_resume()
4290 if (fep->reg_phy) in fec_resume()
4291 regulator_disable(fep->reg_phy); in fec_resume()
4300 clk_disable_unprepare(fep->clk_ahb); in fec_runtime_suspend()
4301 clk_disable_unprepare(fep->clk_ipg); in fec_runtime_suspend()
4312 ret = clk_prepare_enable(fep->clk_ahb); in fec_runtime_resume()
4315 ret = clk_prepare_enable(fep->clk_ipg); in fec_runtime_resume()
4322 clk_disable_unprepare(fep->clk_ahb); in fec_runtime_resume()