Lines Matching +full:0 +full:x8014
7 #define ENETC_DEV_ID_PF 0xe100
8 #define ENETC_DEV_ID_VF 0xef00
9 #define ENETC_DEV_ID_PTP 0xee02
12 #define ENETC_BAR_REGS 0
14 /** SI regs, offset: 0h */
15 #define ENETC_SIMR 0
17 #define ENETC_SIMR_RSSE BIT(0)
18 #define ENETC_SICTR0 0x18
19 #define ENETC_SICTR1 0x1c
20 #define ENETC_SIPCAPR0 0x20
24 #define ENETC_SIPCAPR1 0x24
25 #define ENETC_SITGTGR 0x30
26 #define ENETC_SIRBGCR 0x38
28 #define ENETC_SICAR0 0x40
29 #define ENETC_SICAR1 0x44
30 #define ENETC_SICAR2 0x48
35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
36 #define ENETC_SICAR_WR_COHERENT 0x00006727
37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
39 #define ENETC_SIPMAR0 0x80
40 #define ENETC_SIPMAR1 0x84
44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; in enetc_vsi_set_msize()
50 #define ENETC_PSIMSGRR 0x204
53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
56 #define ENETC_VSIMSGSR 0x204 /* RO */
57 #define ENETC_VSIMSGSR_MB BIT(0)
59 #define ENETC_VSIMSGSNDAR0 0x210
60 #define ENETC_VSIMSGSNDAR1 0x214
66 #define ENETC_SIROCT 0x300
67 #define ENETC_SIRFRM 0x308
68 #define ENETC_SIRUCA 0x310
69 #define ENETC_SIRMCA 0x318
70 #define ENETC_SITOCT 0x320
71 #define ENETC_SITFRM 0x328
72 #define ENETC_SITUCA 0x330
73 #define ENETC_SITMCA 0x338
74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
77 #define ENETC_SICBDRMR 0x800
78 #define ENETC_SICBDRSR 0x804 /* RO */
79 #define ENETC_SICBDRBAR0 0x810
80 #define ENETC_SICBDRBAR1 0x814
81 #define ENETC_SICBDRPIR 0x818
82 #define ENETC_SICBDRCIR 0x81c
83 #define ENETC_SICBDRLENR 0x820
85 #define ENETC_SICAPR0 0x900
86 #define ENETC_SICAPR1 0x904
88 #define ENETC_PSIIER 0xa00
90 #define ENETC_PSIIDR 0xa08
91 #define ENETC_SITXIDR 0xa18
92 #define ENETC_SIRXIDR 0xa28
93 #define ENETC_SIMSIVR 0xa30
95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
98 #define ENETC_SIUEFDCR 0xe28
100 #define ENETC_SIRFSCAPR 0x1200
101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
102 #define ENETC_SIRSSCAPR 0x1600
103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
105 /** SI BDR sub-blocks, n = 0..7 */
107 #define ENETC_BDR_OFF(i) ((i) * 0x200)
108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
110 #define ENETC_RBMR 0
115 #define ENETC_RBSR 0x4
116 #define ENETC_RBBSR 0x8
117 #define ENETC_RBCIR 0xc
118 #define ENETC_RBBAR0 0x10
119 #define ENETC_RBBAR1 0x14
120 #define ENETC_RBPIR 0x18
121 #define ENETC_RBLENR 0x20
122 #define ENETC_RBIER 0xa0
123 #define ENETC_RBIER_RXTIE BIT(0)
124 #define ENETC_RBIDR 0xa4
125 #define ENETC_RBICR0 0xa8
127 #define ENETC_RBICR0_ICPT_MASK 0x1ff
129 #define ENETC_RBICR1 0xac
132 #define ENETC_TBMR 0
133 #define ENETC_TBSR_BUSY BIT(0)
135 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
138 #define ENETC_TBSR 0x4
139 #define ENETC_TBBAR0 0x10
140 #define ENETC_TBBAR1 0x14
141 #define ENETC_TBPIR 0x18
142 #define ENETC_TBCIR 0x1c
143 #define ENETC_TBCIR_IDX_MASK 0xffff
144 #define ENETC_TBLENR 0x20
145 #define ENETC_TBIER 0xa0
146 #define ENETC_TBIER_TXTIE BIT(0)
147 #define ENETC_TBIDR 0xa4
148 #define ENETC_TBICR0 0xa8
150 #define ENETC_TBICR0_ICPT_MASK 0xf
152 #define ENETC_TBICR1 0xac
154 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
157 #define ENETC_PORT_BASE 0x10000
158 #define ENETC_PMR 0x0000
161 #define ENETC_PMR_PSPEED_10M 0
165 #define ENETC_PSR 0x0004 /* RO */
166 #define ENETC_PSIPMR 0x0018
169 #define ENETC_PSIPVMR 0x001c
170 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
171 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
172 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
173 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
174 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
175 #define ENETC_PVCLCTR 0x0208
176 #define ENETC_PCVLANR1 0x0210
177 #define ENETC_PCVLANR2 0x0214
178 #define ENETC_VLAN_TYPE_C BIT(0)
180 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
181 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
184 #define ENETC_PPAUONTR 0x0410
185 #define ENETC_PPAUOFFTR 0x0414
186 #define ENETC_PTXMBAR 0x0608
187 #define ENETC_PCAPR0 0x0900
189 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
190 #define ENETC_PCAPR1 0x0904
191 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
192 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
193 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
197 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
199 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
201 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
202 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
204 #define ENETC_PRSSCAPR 0x1404
205 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
206 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
207 #define ENETC_PSIVLANFMR 0x1700
208 #define ENETC_PSIVLANFMR_VS BIT(0)
209 #define ENETC_PRFSMR 0x1800
211 #define ENETC_PRFSCAPR 0x1804
212 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
213 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
214 #define ENETC_PFPMR 0x1900
216 #define ENETC_PFPMR_MWLM BIT(0)
217 #define ENETC_EMDIO_BASE 0x1c00
218 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
219 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
220 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
221 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
222 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
223 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
224 #define ENETC_MMCSR 0x1f00
226 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
228 #define ENETC_PM0_CMD_CFG 0x8008
229 #define ENETC_PM1_CMD_CFG 0x9008
230 #define ENETC_PM0_TX_EN BIT(0)
238 #define ENETC_PM0_MAXFRM 0x8014
240 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
241 #define ENETC_PM0_RX_FIFO 0x801c
244 #define ENETC_PM_IMDIO_BASE 0x8030
246 #define ENETC_PM0_PAUSE_QUANTA 0x8054
247 #define ENETC_PM0_PAUSE_THRESH 0x8064
248 #define ENETC_PM1_PAUSE_QUANTA 0x9054
249 #define ENETC_PM1_PAUSE_THRESH 0x9064
251 #define ENETC_PM0_SINGLE_STEP 0x80c0
252 #define ENETC_PM1_SINGLE_STEP 0x90c0
255 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
257 #define ENETC_PM0_IF_MODE 0x8300
263 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
266 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
267 #define ENETC_PM0_IFM_IFMODE_XGMII 0
269 #define ENETC_PSIDCAPR 0x1b08
270 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
271 #define ENETC_PSFCAPR 0x1b18
272 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
273 #define ENETC_PSGCAPR 0x1b28
275 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
276 #define ENETC_PFMCAPR 0x1b38
277 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
279 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
282 #define ENETC_PM_REOCT(mac) (0x8100 + 0x1000 * (mac))
283 #define ENETC_PM_RALN(mac) (0x8110 + 0x1000 * (mac))
284 #define ENETC_PM_RXPF(mac) (0x8118 + 0x1000 * (mac))
285 #define ENETC_PM_RFRM(mac) (0x8120 + 0x1000 * (mac))
286 #define ENETC_PM_RFCS(mac) (0x8128 + 0x1000 * (mac))
287 #define ENETC_PM_RVLAN(mac) (0x8130 + 0x1000 * (mac))
288 #define ENETC_PM_RERR(mac) (0x8138 + 0x1000 * (mac))
289 #define ENETC_PM_RUCA(mac) (0x8140 + 0x1000 * (mac))
290 #define ENETC_PM_RMCA(mac) (0x8148 + 0x1000 * (mac))
291 #define ENETC_PM_RBCA(mac) (0x8150 + 0x1000 * (mac))
292 #define ENETC_PM_RDRP(mac) (0x8158 + 0x1000 * (mac))
293 #define ENETC_PM_RPKT(mac) (0x8160 + 0x1000 * (mac))
294 #define ENETC_PM_RUND(mac) (0x8168 + 0x1000 * (mac))
295 #define ENETC_PM_R64(mac) (0x8170 + 0x1000 * (mac))
296 #define ENETC_PM_R127(mac) (0x8178 + 0x1000 * (mac))
297 #define ENETC_PM_R255(mac) (0x8180 + 0x1000 * (mac))
298 #define ENETC_PM_R511(mac) (0x8188 + 0x1000 * (mac))
299 #define ENETC_PM_R1023(mac) (0x8190 + 0x1000 * (mac))
300 #define ENETC_PM_R1522(mac) (0x8198 + 0x1000 * (mac))
301 #define ENETC_PM_R1523X(mac) (0x81A0 + 0x1000 * (mac))
302 #define ENETC_PM_ROVR(mac) (0x81A8 + 0x1000 * (mac))
303 #define ENETC_PM_RJBR(mac) (0x81B0 + 0x1000 * (mac))
304 #define ENETC_PM_RFRG(mac) (0x81B8 + 0x1000 * (mac))
305 #define ENETC_PM_RCNP(mac) (0x81C0 + 0x1000 * (mac))
306 #define ENETC_PM_RDRNTP(mac) (0x81C8 + 0x1000 * (mac))
307 #define ENETC_PM_TEOCT(mac) (0x8200 + 0x1000 * (mac))
308 #define ENETC_PM_TOCT(mac) (0x8208 + 0x1000 * (mac))
309 #define ENETC_PM_TCRSE(mac) (0x8210 + 0x1000 * (mac))
310 #define ENETC_PM_TXPF(mac) (0x8218 + 0x1000 * (mac))
311 #define ENETC_PM_TFRM(mac) (0x8220 + 0x1000 * (mac))
312 #define ENETC_PM_TFCS(mac) (0x8228 + 0x1000 * (mac))
313 #define ENETC_PM_TVLAN(mac) (0x8230 + 0x1000 * (mac))
314 #define ENETC_PM_TERR(mac) (0x8238 + 0x1000 * (mac))
315 #define ENETC_PM_TUCA(mac) (0x8240 + 0x1000 * (mac))
316 #define ENETC_PM_TMCA(mac) (0x8248 + 0x1000 * (mac))
317 #define ENETC_PM_TBCA(mac) (0x8250 + 0x1000 * (mac))
318 #define ENETC_PM_TPKT(mac) (0x8260 + 0x1000 * (mac))
319 #define ENETC_PM_TUND(mac) (0x8268 + 0x1000 * (mac))
320 #define ENETC_PM_T64(mac) (0x8270 + 0x1000 * (mac))
321 #define ENETC_PM_T127(mac) (0x8278 + 0x1000 * (mac))
322 #define ENETC_PM_T255(mac) (0x8280 + 0x1000 * (mac))
323 #define ENETC_PM_T511(mac) (0x8288 + 0x1000 * (mac))
324 #define ENETC_PM_T1023(mac) (0x8290 + 0x1000 * (mac))
325 #define ENETC_PM_T1522(mac) (0x8298 + 0x1000 * (mac))
326 #define ENETC_PM_T1523X(mac) (0x82A0 + 0x1000 * (mac))
327 #define ENETC_PM_TCNP(mac) (0x82C0 + 0x1000 * (mac))
328 #define ENETC_PM_TDFR(mac) (0x82D0 + 0x1000 * (mac))
329 #define ENETC_PM_TMCOL(mac) (0x82D8 + 0x1000 * (mac))
330 #define ENETC_PM_TSCOL(mac) (0x82E0 + 0x1000 * (mac))
331 #define ENETC_PM_TLCOL(mac) (0x82E8 + 0x1000 * (mac))
332 #define ENETC_PM_TECOL(mac) (0x82F0 + 0x1000 * (mac))
335 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
336 #define ENETC_PBFDSIR 0x0810
337 #define ENETC_PFDMSAPR 0x0814
338 #define ENETC_UFDMF 0x1680
339 #define ENETC_MFDMF 0x1684
340 #define ENETC_PUFDVFR 0x1780
341 #define ENETC_PMFDVFR 0x1784
342 #define ENETC_PBFDVFR 0x1788
345 #define ENETC_GLOBAL_BASE 0x20000
346 #define ENETC_G_EIPBRR0 0x0bf8
347 #define ENETC_G_EIPBRR1 0x0bfc
348 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
349 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
540 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
549 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
564 memset(txbd, 0, sizeof(*txbd)); in enetc_clear_tx_bd()
568 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
599 #define ENETC_RXBD_ERR_MASK 0xff
603 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
610 #define ENETC_CBD_STATUS_MASK 0xf
651 #define ENETC_SI_INT_IDX 0
689 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); in enetc_bdr_enable_rxvlan()
698 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); in enetc_bdr_enable_txvlan()
713 BDCR_CMD_UNSPEC = 0,
728 /* class 5, command 0 */
755 /* class 7, command 0, Stream Identity Entry Configuration */
765 #define ENETC_CBDR_SID_VID_MASK 0xfff
767 #define ENETC_CBDR_SID_TG_MASK 0xc000
777 #define ENETC_CBDR_SFI_PRI_MASK 0x7
784 /* class 8, command 0, Stream Filter Instance, Short Format */
821 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
831 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
832 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
834 /* class 9, command 0, Stream Gate Instance Table, Short Format
850 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
870 #define ENETC_CBDR_SGL_IOMEN BIT(0)
873 #define ENETC_CBDR_SGL_IPV_MASK 0xe
890 #define ENETC_CBDR_FMI_MR BIT(0)
897 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
899 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
948 #define ENETC_PTGCR 0x11a00
953 #define ENETC_PTGCAPR 0x11a08
954 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
957 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
961 #define ENETC_PPSFPMR 0x11b00
962 #define ENETC_PPSFPMR_PSFPEN BIT(0)