143 #define dw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
608 	dw32(DCR0, DM910X_RESET);	/* RESET MAC */  in dmfe_init_dm910x()
610 	dw32(DCR0, db->cr0_data);  in dmfe_init_dm910x()
621 	dw32(DCR12, 0x180);		/* Let bit 7 output port */  in dmfe_init_dm910x()
623 		dw32(DCR12, 0x80);	/* Issue RESET signal */  in dmfe_init_dm910x()
626 	dw32(DCR12, 0x0);	/* Clear RESET signal */  in dmfe_init_dm910x()
650 	dw32(DCR7, db->cr7_data);  in dmfe_init_dm910x()
653 	dw32(DCR15, db->cr15_data);  in dmfe_init_dm910x()
696 	dw32(DCR7, 0);  in dmfe_start_xmit()
710 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
714 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
723 	dw32(DCR7, db->cr7_data);  in dmfe_start_xmit()
751 	dw32(DCR0, DM910X_RESET);  in dmfe_stop()
792 	dw32(DCR5, db->cr5_data);  in dmfe_interrupt()
799 	dw32(DCR7, 0);  in dmfe_interrupt()
831 	dw32(DCR7, db->cr7_data);  in dmfe_interrupt()
916 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_free_tx_pkt()
1163 		dw32(DCR1, 0x1);   /* Tx polling again */  in dmfe_timer()
1284 	dw32(DCR7, 0);				/* Disable Interrupt */  in dmfe_dynamic_reset()
1285 	dw32(DCR5, dr32(DCR5));  in dmfe_dynamic_reset()
1367 	dw32(DCR4, db->first_tx_desc_dma);     /* TX DESC address */  in dmfe_descriptor_init()
1377 	dw32(DCR3, db->first_rx_desc_dma);		/* RX DESC address */  in dmfe_descriptor_init()
1424 	dw32(DCR6, cr6_tmp);  in update_cr6()
1426 	dw32(DCR6, cr6_data);  in update_cr6()
1525 		dw32(DCR1, 0x1);	/* Issue Tx polling */  in send_filter_frame()
1571 		dw32(DCR9, data | cmd[i]);  in srom_clk_write()
1584 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1586 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1600 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1604 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);  in read_srom_word()
1608 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1612 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1870 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1872 	dw32(DCR9, phy_data | MDCLKH);	/* MII Clock High */  in dmfe_phy_write_1bit()
1874 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1887 	dw32(DCR9, 0x50000);  in dmfe_phy_read_1bit()
1890 	dw32(DCR9, 0x40000);  in dmfe_phy_read_1bit()
2101 	dw32(DCR7, 0);  in dmfe_suspend()
2102 	dw32(DCR5, dr32(DCR5));  in dmfe_suspend()