42 	DBGI_MODE_MBUS = 0,
47 #define IDT_CMD_READ   0
53 #define IDT_LAR_ADR0   	0x180006
54 #define IDT_LAR_MODE144	0xffff0000
57 #define IDT_SCR_ADR0  0x180000
58 #define IDT_SSR0_ADR0 0x180002
59 #define IDT_SSR1_ADR0 0x180004
62 #define IDT_GMR_BASE_ADR0 0x180020
65 #define IDT_DATARY_BASE_ADR0 0
66 #define IDT_MSKARY_BASE_ADR0 0x80000
74 #define IDT4_SCR_ADR0  0x3
77 #define IDT4_GMR_BASE0 0x10
78 #define IDT4_GMR_BASE1 0x20
79 #define IDT4_GMR_BASE2 0x30
82 #define IDT4_DATARY_BASE_ADR0 0x1000000
83 #define IDT4_MSKARY_BASE_ADR0 0x2000000
109  * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
111  * Returns -1 on failure, 0 on success.
116 	if (mc5_cmd_write(adapter, cmd) == 0)  in mc5_write()
117 		return 0;  in mc5_write()
118 	CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n",  in mc5_write()
143 	dbgi_wr_data3(adap, 0, 0, 0);  in init_mask_data_array()
144 	for (i = 0; i < size72; i++)  in init_mask_data_array()
150 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);  in init_mask_data_array()
151 	for (i = 0; i < size72; i++) {  in init_mask_data_array()
155 				     0xfffffff9 : 0xfffffffd);  in init_mask_data_array()
160 	return 0;  in init_mask_data_array()
169 		     V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15));  in init_idt52100()
180 	t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);  in init_idt52100()
185 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);  in init_idt52100()
193 	dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);  in init_idt52100()
198 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);  in init_idt52100()
204 	for (i = 0; i < 32; ++i) {  in init_idt52100()
206 			dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);  in init_idt52100()
208 			dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);  in init_idt52100()
210 			dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);  in init_idt52100()
217 	dbgi_wr_data3(adap, 1, 0, 0);  in init_idt52100()
222 				    IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0);  in init_idt52100()
233 		     adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :  in init_idt43102()
234 		     V_RDLAT(0xd) | V_SRCHLAT(0x12));  in init_idt43102()
243 		     IDT4_CMD_SEARCH144 | 0x3800);  in init_idt43102()
245 	t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);  in init_idt43102()
246 	t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);  in init_idt43102()
247 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);  in init_idt43102()
257 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);  in init_idt43102()
258 	for (i = 0; i < 7; ++i)  in init_idt43102()
262 	for (i = 0; i < 4; ++i)  in init_idt43102()
266 	dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);  in init_idt43102()
272 	dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);  in init_idt43102()
277 	dbgi_wr_data3(adap, 0xf0000000, 0, 0);  in init_idt43102()
316 		return 0;  in t3_mc5_init()
325 	if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {  in t3_mc5_init()
338 	/* All the TCAM addresses we access have only the low 32 bits non 0 */  in t3_mc5_init()
339 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);  in t3_mc5_init()
340 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);  in t3_mc5_init()