Lines Matching +full:com +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
12 * http://www.chelsio.com *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
17 * Maintainers: maintainers@chelsio.com *
19 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
20 * Tina Yang <tainay@chelsio.com> *
21 * Felix Marti <felix@chelsio.com> *
22 * Scott Bardone <sbardone@chelsio.com> *
23 * Kurt Ottaway <kottaway@chelsio.com> *
24 * Frank DiMambro <frank@chelsio.com> *
39 #define OFFSET(REG_ADDR) ((REG_ADDR) << 2) macro
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
115 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
138 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
144 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
147 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
155 /* PM3393 - Enabling HW interrupt blocks. */ in pm3393_interrupt_disable()
174 /* PM3393 - Global interrupt enable */ in pm3393_interrupt_disable()
177 /* ELMER - External chip interrupts. */ in pm3393_interrupt_disable()
178 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); in pm3393_interrupt_disable()
180 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_disable()
182 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_disable()
196 /* PM3393 - Clearing HW interrupt blocks. Note, this assumes in pm3393_interrupt_clear()
197 * bit WCIMODE=0 for a clear-on-read. in pm3393_interrupt_clear()
215 /* PM3393 - Global interrupt status in pm3393_interrupt_clear()
219 /* ELMER - External chip interrupts. in pm3393_interrupt_clear()
221 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer); in pm3393_interrupt_clear()
223 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); in pm3393_interrupt_clear()
225 /* TERMINATOR - PL_INTERUPTS_EXT in pm3393_interrupt_clear()
227 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE); in pm3393_interrupt_clear()
229 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE); in pm3393_interrupt_clear()
242 if (netif_msg_intr(cmac->adapter)) in pm3393_interrupt_handler()
243 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n", in pm3393_interrupt_handler()
261 if (cmac->instance->fc & PAUSE_RX) in pm3393_enable()
263 if (cmac->instance->fc & PAUSE_TX) in pm3393_enable()
268 cmac->instance->enabled |= which; in pm3393_enable()
278 memset(&cmac->stats, 0, sizeof(struct cmac_statistics)); in pm3393_enable_port()
287 t1_link_changed(cmac->adapter, 0); in pm3393_enable_port()
304 cmac->instance->enabled &= ~which; in pm3393_disable()
320 int enabled = cmac->instance->enabled; in pm3393_set_mtu()
338 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX; in pm3393_set_rx_mode()
370 bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f; in pm3393_set_rx_mode()
396 *fc = cmac->instance->fc; in pm3393_get_speed_duplex_fc()
404 return -1; in pm3393_set_speed_duplex_fc()
406 return -1; in pm3393_set_speed_duplex_fc()
408 return -1; in pm3393_set_speed_duplex_fc()
410 if (fc != cmac->instance->fc) { in pm3393_set_speed_duplex_fc()
411 cmac->instance->fc = (u8) fc; in pm3393_set_speed_duplex_fc()
412 if (cmac->instance->enabled & MAC_DIRECTION_TX) in pm3393_set_speed_duplex_fc()
420 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
421 t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
422 t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
423 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
426 ((mac)->stats.stat_name & \
429 (1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \
430 (mac)->stats.stat_name += 1ULL << 40; \
481 return &mac->stats; in pm3393_update_statistics()
486 memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN); in pm3393_macaddress_get()
492 u32 val, lo, mid, hi, enabled = cmac->instance->enabled; in pm3393_macaddress_set()
513 memcpy(cmac->instance->mac_addr, ma, ETH_ALEN); in pm3393_macaddress_set()
586 cmac->ops = &pm3393_ops; in pm3393_mac_create()
587 cmac->instance = (cmac_instance *) (cmac + 1); in pm3393_mac_create()
588 cmac->adapter = adapter; in pm3393_mac_create()
589 cmac->instance->fc = PAUSE_TX | PAUSE_RX; in pm3393_mac_create()
591 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); in pm3393_mac_create()
592 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); in pm3393_mac_create()
593 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); in pm3393_mac_create()
594 t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */ in pm3393_mac_create()
595 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); in pm3393_mac_create()
596 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); in pm3393_mac_create()
597 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800); in pm3393_mac_create()
598 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800); in pm3393_mac_create()
599 t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800); in pm3393_mac_create()
600 t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800); in pm3393_mac_create()
601 t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800); in pm3393_mac_create()
602 t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800); in pm3393_mac_create()
603 t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800); in pm3393_mac_create()
604 t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800); in pm3393_mac_create()
605 t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800); in pm3393_mac_create()
606 t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800); in pm3393_mac_create()
607 t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800); in pm3393_mac_create()
608 t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800); in pm3393_mac_create()
609 t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800); in pm3393_mac_create()
610 t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800); in pm3393_mac_create()
611 t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00); in pm3393_mac_create()
612 t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */ in pm3393_mac_create()
614 t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */ in pm3393_mac_create()
615 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */ in pm3393_mac_create()
616 t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */ in pm3393_mac_create()
617 t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */ in pm3393_mac_create()
618 t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */ in pm3393_mac_create()
619 t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */ in pm3393_mac_create()
620 t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */ in pm3393_mac_create()
621 t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */ in pm3393_mac_create()
622 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */ in pm3393_mac_create()
623 t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
624 t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
625 …t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit… in pm3393_mac_create()
626 t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
628 t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */ in pm3393_mac_create()
629 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */ in pm3393_mac_create()
630 t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */ in pm3393_mac_create()
631 t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */ in pm3393_mac_create()
632 t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */ in pm3393_mac_create()
633 t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */ in pm3393_mac_create()
634 t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */ in pm3393_mac_create()
635 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */ in pm3393_mac_create()
636 t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
637 t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
638 …t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other b… in pm3393_mac_create()
640 t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */ in pm3393_mac_create()
641 t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */ in pm3393_mac_create()
642 t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */ in pm3393_mac_create()
643 t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */ in pm3393_mac_create()
644 t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */ in pm3393_mac_create()
645 t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */ in pm3393_mac_create()
647 t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */ in pm3393_mac_create()
648 t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */ in pm3393_mac_create()
650 …t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machi… in pm3393_mac_create()
651 t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */ in pm3393_mac_create()
653 t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ in pm3393_mac_create()
655 t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); in pm3393_mac_create()
656 t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ in pm3393_mac_create()
657 t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */ in pm3393_mac_create()
658 t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ in pm3393_mac_create()
662 t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */ in pm3393_mac_create()
663 t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */ in pm3393_mac_create()
664 t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */ in pm3393_mac_create()
665 t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */ in pm3393_mac_create()
666 t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */ in pm3393_mac_create()
668 t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */ in pm3393_mac_create()
669 t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */ in pm3393_mac_create()
670 t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */ in pm3393_mac_create()
688 * section 13.1 -- Device Reset. in pm3393_mac_reset()
693 * DRESETB - Digital circuitry in pm3393_mac_reset()
694 * PL4_ARESETB - PL4 analog circuitry in pm3393_mac_reset()
695 * XAUI_ARESETB - XAUI bus analog circuitry in pm3393_mac_reset()
703 * 5. De-assert RSTB ( write 1 ) in pm3393_mac_reset()
705 * - Allows analog clock synthesizer(PL4CSU) to stabilize to in pm3393_mac_reset()
743 t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val); in pm3393_mac_reset()
767 dev_dbg(&adapter->pdev->dev, in pm3393_mac_reset()