Lines Matching refs:tr32
621 #define tr32(reg) tp->read32(tp, reg) macro
667 *val = tr32(TG3PCI_MEM_WIN_DATA); in tg3_read_mem()
1088 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
1143 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1147 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1205 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1208 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1437 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1456 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1469 val = tr32(MAC_EXT_RGMII_MODE); in tg3_mdio_config_5785()
1514 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; in tg3_mdio_init()
1516 is_serdes = tr32(TG3_CPMU_PHY_STRAP) & in tg3_mdio_init()
1617 val = tr32(GRC_RX_CPU_EVENT); in tg3_generate_fw_event()
1647 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1821 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
2373 val = tr32(TG3_CPMU_EEE_MODE); in tg3_eee_pull_config()
2377 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2415 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_adjust()
2435 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_enable()
2633 val = tr32(GRC_MISC_CFG); in tg3_phy_reset()
2659 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_phy_reset()
2678 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_phy_reset()
2792 status = tr32(TG3_CPMU_DRV_STATUS); in tg3_set_function_status()
3063 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_power_down_phy()
3064 u32 serdes_cfg = tr32(MAC_SERDES_CFG); in tg3_power_down_phy()
3076 val = tr32(GRC_MISC_CFG); in tg3_power_down_phy()
3119 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_power_down_phy()
3137 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
3166 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_enable_nvram_access()
3176 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_disable_nvram_access()
3191 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
3202 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
3211 tmp = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
3231 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
3302 *val = tr32(NVRAM_RDDATA); in tg3_nvram_read()
3343 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3355 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3548 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3559 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3588 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3636 u32 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_halt_cpu()
3729 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); in tg3_load_firmware_cpu()
3769 if (tr32(cpu_base + CPU_PC) == pc) in tg3_pause_cpu_and_set_pc()
3812 tr32(RX_CPU_BASE + CPU_PC), in tg3_load_5701_a0_firmware_fix()
3832 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) in tg3_validate_rxcpu_state()
3935 __func__, tr32(cpu_base + CPU_PC), in tg3_load_tso_firmware()
4033 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_power_down_prepare()
4106 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_power_down_prepare()
4247 u32 val = tr32(0x7d00); in tg3_power_down_prepare()
4350 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_autoneg_cfg()
5005 u32 led_ctrl = tr32(MAC_LED_CTRL); in tg3_setup_copper_phy()
5170 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
5171 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
5449 u32 mac_status = tr32(MAC_STATUS); in tg3_init_bcm8002()
5513 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
5518 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
5521 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_setup_fiber_hw_autoneg()
5574 sg_dig_status = tr32(SG_DIG_STATUS); in tg3_setup_fiber_hw_autoneg()
5575 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5619 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5678 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
5684 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_by_hand()
5722 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5750 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5765 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
5771 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5870 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
5939 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
6077 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; in tg3_setup_phy()
6085 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; in tg3_setup_phy()
6094 val |= tr32(MAC_TX_LENGTHS) & in tg3_setup_phy()
6116 val = tr32(PCIE_PWR_MGMT_THRESH); in tg3_setup_phy()
6134 stamp = tr32(TG3_EAV_REF_CLCK_LSB); in tg3_refclk_read()
6136 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32; in tg3_refclk_read()
6144 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write()
6278 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6391 *dst++ = tr32(off + i); in tg3_rd32_loop()
6456 regs[i / sizeof(u32)] = tr32(i); in tg3_dump_state()
6558 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB); in tg3_tx()
6559 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32; in tg3_tx()
6867 tstamp = tr32(TG3_RX_TSTAMP_LSB); in tg3_rx()
6868 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32; in tg3_rx()
7289 val = tr32(HOSTCC_FLOW_ATTN); in tg3_process_error()
7295 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { in tg3_process_error()
7300 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { in tg3_process_error()
7517 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt()
7566 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt_tagged()
7612 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_test_isr()
8836 val = tr32(ofs); in tg3_stop_block()
8850 val = tr32(ofs); in tg3_stop_block()
8907 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
8913 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); in tg3_abort_hw()
8998 val = tr32(MSGINT_MODE); in tg3_restore_pci_state()
9010 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_override_clk()
9031 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_restore_clk()
9038 val = tr32(TG3_CPMU_CLCK_ORIDE); in tg3_restore_clk()
9114 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_chip_reset()
9125 tr32(TG3_PCIE_PHY_TSTCTL) == in tg3_chip_reset()
9136 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
9138 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_chip_reset()
9223 val = tr32(MEMARB_MODE); in tg3_chip_reset()
9248 val = tr32(0xc4); in tg3_chip_reset()
9281 val = tr32(0x7c00); in tg3_chip_reset()
9292 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_chip_reset()
9376 addr0_high = tr32(MAC_ADDR_0_HIGH); in tg3_set_mac_addr()
9377 addr0_low = tr32(MAC_ADDR_0_LOW); in tg3_set_mac_addr()
9378 addr1_high = tr32(MAC_ADDR_1_HIGH); in tg3_set_mac_addr()
9379 addr1_low = tr32(MAC_ADDR_1_LOW); in tg3_set_mac_addr()
9890 val = tr32(TG3_CPMU_CTRL); in tg3_reset_hw()
9894 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9899 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); in tg3_reset_hw()
9904 val = tr32(TG3_CPMU_HST_ACC); in tg3_reset_hw()
9911 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; in tg3_reset_hw()
9916 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; in tg3_reset_hw()
9921 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_reset_hw()
9926 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9932 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw()
9941 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9947 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9959 val = tr32(TG3_CPMU_PADRNG_CTL); in tg3_reset_hw()
9963 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9978 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9997 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10006 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10015 val = tr32(TG3PCI_MSI_DATA); in tg3_reset_hw()
10030 val = tr32(TG3PCI_DMA_RW_CTRL) & in tg3_reset_hw()
10077 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK; in tg3_reset_hw()
10082 val = tr32(GRC_MISC_CFG); in tg3_reset_hw()
10139 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
10149 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10244 val |= tr32(MAC_TX_LENGTHS) & in tg3_reset_hw()
10277 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10306 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; in tg3_reset_hw()
10320 val = tr32(tgtreg); in tg3_reset_hw()
10343 val = tr32(tgtreg); in tg3_reset_hw()
10351 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10356 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10371 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
10447 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10458 val = tr32(MSGINT_MODE); in tg3_reset_hw()
10484 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10522 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10526 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_reset_hw()
10589 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10639 val = tr32(MAC_SERDES_CFG); in tg3_reset_hw()
10667 tmp = tr32(SERDES_RX_CTRL); in tg3_reset_hw()
10874 do { u32 __val = tr32(REG); \
10905 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_periodic_fetch_stats()
10933 u32 val = tr32(HOSTCC_FLOW_ATTN); in tg3_periodic_fetch_stats()
10986 tr32(HOSTCC_MODE); in tg3_timer()
11002 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
11021 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11033 u32 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11060 u32 cpmu = tr32(TG3_CPMU_STATUS); in tg3_timer()
11281 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11300 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_test_interrupt()
11327 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11521 u32 msi_mode = tr32(MSGINT_MODE); in tg3_ints_init()
11620 u32 val = tr32(PCIE_TRANSACTION_CFG); in tg3_start()
12002 cpmu_val = tr32(TG3_CPMU_CTRL); in tg3_get_eeprom()
13221 save_val = tr32(offset); in tg3_test_registers()
13231 val = tr32(offset); in tg3_test_registers()
13243 val = tr32(offset); in tg3_test_registers()
13659 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_test_loopback()
14345 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_nvram_info()
14423 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5752_nvram_info()
14464 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5755_nvram_info()
14520 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5787_nvram_info()
14558 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5761_nvram_info()
14598 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14640 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_57780_nvram_info()
14713 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5717_nvram_info()
14791 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5720_nvram_info()
14811 nv_status = tr32(NVRAM_AUTOSENSE_STATUS); in tg3_get_5720_nvram_info()
14971 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
15121 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
15125 val = tr32(VCPU_CFGSHDW); in tg3_get_eeprom_hw_cfg()
15369 val = tr32(OTP_STATUS); in tg3_issue_otp_command()
15396 thalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
15403 bhalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
16115 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; in tg3_10_100_only_device()
16567 val = tr32(MEMARB_MODE); in tg3_get_invariants()
16584 val = tr32(TG3_CPMU_STATUS); in tg3_get_invariants()
16662 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16754 val = tr32(GRC_MODE); in tg3_get_invariants()
16807 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
16909 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16933 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
16972 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
16973 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
17200 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17202 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17254 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
17489 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
17494 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == in tg3_bus_string()
17778 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { in tg3_init_one()
17840 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
17841 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_init_one()