Lines Matching refs:tg3_writephy
1228 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() function
1237 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1245 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1260 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1264 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1268 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1283 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1294 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1296 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1305 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1319 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1345 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1358 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
2204 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2211 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2213 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2262 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2269 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2271 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2470 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2472 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2475 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2478 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2492 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2511 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2512 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2530 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2532 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2534 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2535 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2563 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2566 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2573 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2594 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2595 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2599 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2606 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2707 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2722 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2723 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2751 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2757 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
3085 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3086 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3089 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3093 tg3_writephy(tp, in tg3_power_down_phy()
3097 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3102 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3125 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
4330 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4341 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4446 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4460 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4483 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4496 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4842 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4843 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4853 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4860 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4863 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
5458 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5461 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5469 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5472 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5474 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5478 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5480 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5482 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5484 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5494 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5894 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5896 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5927 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5928 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5934 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
6019 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6023 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6036 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6046 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6054 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
8218 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8222 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8227 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8237 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8268 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
10688 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
11796 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
12383 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
15575 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()