13054 #define TG3_FL_NOT_5705	0x2  in tg3_test_registers()  macro
13061 		{ MAC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13065 		{ MAC_STATUS, TG3_FL_NOT_5705,  in tg3_test_registers()
13079 		{ MAC_RX_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13093 		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,  in tg3_test_registers()
13095 		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13097 		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,  in tg3_test_registers()
13099 		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,  in tg3_test_registers()
13111 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13115 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13119 		{ HOSTCC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13123 		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13127 		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13131 		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13135 		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13139 		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13141 		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13143 		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13147 		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13151 		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13153 		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13155 		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13177 		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13179 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,  in tg3_test_registers()
13185 		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13203 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))  in tg3_test_registers()