Lines Matching refs:TG3_64BIT_REG_LOW
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { in tg3_write_indirect_mbox()
522 TG3_64BIT_REG_LOW, val); in tg3_write_indirect_mbox()
527 TG3_64BIT_REG_LOW, val); in tg3_write_indirect_mbox()
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && in tg3_write_indirect_mbox()
7534 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt()
7545 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, in tg3_interrupt()
7583 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt_tagged()
9403 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), in tg3_set_bdinfo()
9628 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; in tg3_rings_reset()
9639 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_rings_reset()
9647 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); in tg3_rings_reset()
10172 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10192 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
10385 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, in tg3_reset_hw()
17791 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; in tg3_init_one()
17792 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; in tg3_init_one()
17793 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; in tg3_init_one()