Lines Matching +full:rx +full:- +full:clk +full:- +full:tap +full:- +full:delay
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
33 #include <linux/delay.h>
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
122 * and dev->tx_timeout() should be called to fix the problem
145 /* Do not place this n-ring entries value into the tp struct itself,
149 * replace things like '% foo' with '& (foo - 1)'.
153 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
163 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
189 * the 5701 in the normal rx path. Doing so saves a device structure
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
200 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
206 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
230 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
470 writel(val, tp->regs + off); in tg3_write32()
475 return readl(tp->regs + off); in tg3_read32()
480 writel(val, tp->aperegs + off); in tg3_ape_write32()
485 return readl(tp->aperegs + off); in tg3_ape_read32()
492 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
495 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
500 writel(val, tp->regs + off); in tg3_write_flush_reg32()
501 readl(tp->regs + off); in tg3_write_flush_reg32()
509 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
512 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
531 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
534 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
551 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
554 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
559 * where it is unsafe to read back the register without some delay.
566 /* Non-posted methods */ in _tw32_flush()
567 tp->write32(tp, off, val); in _tw32_flush()
573 tp->read32(tp, off); in _tw32_flush()
584 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
588 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
593 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
604 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
609 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
612 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
614 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
618 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tr32(reg) tp->read32(tp, reg)
631 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
645 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
658 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
672 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
695 if (!tp->pci_fn) in tg3_ape_lock_init()
698 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
721 if (!tp->pci_fn) in tg3_ape_lock()
724 bit = 1 << tp->pci_fn; in tg3_ape_lock()
733 return -EINVAL; in tg3_ape_lock()
753 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
762 ret = -EBUSY; in tg3_ape_lock()
782 if (!tp->pci_fn) in tg3_ape_unlock()
785 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
811 return -EBUSY; in tg3_ape_event_lock()
820 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
823 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
854 return -ENODEV; in tg3_ape_scratchpad_read()
858 return -EAGAIN; in tg3_ape_scratchpad_read()
870 len -= length; in tg3_ape_scratchpad_read()
874 return -EAGAIN; in tg3_ape_scratchpad_read()
895 return -EAGAIN; in tg3_ape_scratchpad_read()
897 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
915 return -EAGAIN; in tg3_ape_send_event()
919 return -EAGAIN; in tg3_ape_send_event()
945 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
962 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
988 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
991 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
992 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1000 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1001 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1002 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1009 tp->irq_sync = 0; in tg3_enable_ints()
1013 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1015 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1016 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1017 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1019 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1023 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1028 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1029 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1031 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1033 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1038 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1039 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1044 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1049 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1052 /* check for RX work to do */ in tg3_has_work()
1053 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1054 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1067 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1069 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1076 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1077 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1094 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1122 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1124 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1128 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1150 loops -= 1; in __tg3_readphy()
1153 ret = -EBUSY; in __tg3_readphy()
1159 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1160 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1164 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1171 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1185 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1187 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1191 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1211 loops -= 1; in __tg3_writephy()
1214 ret = -EBUSY; in __tg3_writephy()
1218 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1219 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1223 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1230 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1360 return -EBUSY; in tg3_bmcr_reset()
1363 while (limit--) { in tg3_bmcr_reset()
1366 return -EBUSY; in tg3_bmcr_reset()
1375 return -EBUSY; in tg3_bmcr_reset()
1382 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1385 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1388 val = -EIO; in tg3_mdio_read()
1390 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1397 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1400 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1403 ret = -EIO; in tg3_mdio_write()
1405 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1415 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1416 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1434 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1493 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1494 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1511 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1519 tp->phy_addr += 7; in tg3_mdio_init()
1523 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1526 tp->phy_addr = addr; in tg3_mdio_init()
1528 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1535 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1536 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1537 return -ENOMEM; in tg3_mdio_init()
1539 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1540 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1541 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1542 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1543 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1544 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1545 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1556 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1558 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1559 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1563 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1565 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1566 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1567 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1568 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1569 return -ENODEV; in tg3_mdio_init()
1572 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1574 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1575 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1579 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1585 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1589 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1590 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1591 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1607 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1608 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1612 /* tp->lock is held. */
1621 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1626 /* tp->lock is held. */
1634 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1635 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1649 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1656 /* tp->lock is held. */
1676 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1691 /* tp->lock is held. */
1713 /* tp->lock is held. */
1717 /* Wait for RX cpu to ACK the previous event. */ in tg3_stop_fw()
1724 /* Wait for RX cpu to ACK this event. */ in tg3_stop_fw()
1729 /* tp->lock is held. */
1758 /* tp->lock is held. */
1779 /* tp->lock is held. */
1823 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1824 return -ENODEV; in tg3_poll_fw()
1828 return -ENODEV; in tg3_poll_fw()
1836 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1839 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1856 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1871 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1872 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1875 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1876 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1878 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1880 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1883 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1884 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1890 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1891 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1896 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1963 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1964 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1967 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1969 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1972 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1977 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1979 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1982 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1984 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1986 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1987 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1990 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1992 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1994 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1995 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2003 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2005 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2007 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2010 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2012 if (phydev->link) { in tg3_adjust_link()
2016 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2018 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2024 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2028 tp->link_config.flowctrl); in tg3_adjust_link()
2030 if (phydev->pause) in tg3_adjust_link()
2032 if (phydev->asym_pause) in tg3_adjust_link()
2040 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2041 tp->mac_mode = mac_mode; in tg3_adjust_link()
2042 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2047 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2055 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2066 if (phydev->link != tp->old_link || in tg3_adjust_link()
2067 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2068 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2069 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2072 tp->old_link = phydev->link; in tg3_adjust_link()
2073 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2074 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2076 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2086 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2092 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2095 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2096 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2098 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2103 switch (phydev->interface) { in tg3_phy_init()
2106 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2117 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2118 return -EINVAL; in tg3_phy_init()
2121 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2132 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2135 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2137 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2138 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2139 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2140 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2141 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2143 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2153 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2156 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2161 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2162 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2163 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2172 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2175 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2176 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2223 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2226 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2253 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2256 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2294 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2307 if (!tp->phy_otp) in tg3_phy_apply_otp()
2310 otp = tp->phy_otp; in tg3_phy_apply_otp()
2343 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2345 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2357 dest->eee_active = 1; in tg3_eee_pull_config()
2359 dest->eee_active = 0; in tg3_eee_pull_config()
2364 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2369 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2370 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2374 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2377 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2384 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2387 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2389 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2391 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2392 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2393 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2396 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2404 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2405 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2408 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2424 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2443 while (limit--) { in tg3_wait_macro_done()
2452 return -EBUSY; in tg3_wait_macro_done()
2481 return -EBUSY; in tg3_phy_write_and_check_testpat()
2489 return -EBUSY; in tg3_phy_write_and_check_testpat()
2495 return -EBUSY; in tg3_phy_write_and_check_testpat()
2505 return -EBUSY; in tg3_phy_write_and_check_testpat()
2515 return -EBUSY; in tg3_phy_write_and_check_testpat()
2537 return -EBUSY; in tg3_phy_reset_chanpat()
2565 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2586 } while (--retries); in tg3_phy_reset_5703_4_5()
2613 netif_carrier_off(tp->dev); in tg3_carrier_off()
2614 tp->link_up = false; in tg3_carrier_off()
2620 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2621 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2625 * link unless the FORCE argument is non-zero.
2640 return -EBUSY; in tg3_phy_reset()
2642 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2643 netif_carrier_off(tp->dev); in tg3_phy_reset()
2688 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2693 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2699 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2706 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2711 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2718 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2721 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2734 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2735 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2738 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2794 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2816 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2820 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2841 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2863 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2870 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2872 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2878 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2896 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2902 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2915 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2921 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2927 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2974 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2977 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3004 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3006 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3022 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3026 if (!tp->pci_fn) in tg3_phy_power_bug()
3031 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3032 !tp->pci_fn) in tg3_phy_power_bug()
3045 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3046 !tp->pci_fn) in tg3_phy_led_bug()
3058 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3061 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3080 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3128 /* tp->lock is held. */
3134 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3143 return -ENODEV; in tg3_nvram_lock()
3146 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3151 /* tp->lock is held. */
3155 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3156 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3157 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3162 /* tp->lock is held. */
3172 /* tp->lock is held. */
3189 return -EINVAL; in tg3_nvram_read_using_eeprom()
3209 return -EBUSY; in tg3_nvram_read_using_eeprom()
3238 return -EBUSY; in tg3_nvram_exec_cmd()
3249 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3251 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3253 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3264 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3267 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3268 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3277 * machine, the 32-bit value will be byteswapped.
3289 return -EINVAL; in tg3_nvram_read()
3362 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3375 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3376 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3382 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3404 len -= size; in tg3_nvram_write_block_unbuffered()
3408 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3450 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3482 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3490 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3493 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3503 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3530 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3579 /* tp->lock is held. */
3590 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3591 return -EBUSY; in tg3_pause_cpu()
3594 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3597 /* tp->lock is held. */
3609 /* tp->lock is held. */
3615 /* tp->lock is held. */
3622 /* tp->lock is held. */
3628 /* tp->lock is held. */
3645 * There is only an Rx CPU for the 5750 derivative in the in tg3_halt_cpu()
3655 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3656 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX"); in tg3_halt_cpu()
3657 return -ENODEV; in tg3_halt_cpu()
3675 * tp->fw->size minus headers. in tg3_fw_data_len()
3685 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3686 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3688 fw_len = tp->fw->size; in tg3_fw_data_len()
3690 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3693 /* tp->lock is held. */
3700 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3703 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3706 return -EINVAL; in tg3_load_firmware_cpu()
3734 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3742 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3746 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3750 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3759 /* tp->lock is held. */
3777 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3780 /* tp->lock is held. */
3786 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3790 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3806 /* Now startup only the RX cpu. */ in tg3_load_5701_a0_firmware_fix()
3808 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3810 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3813 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3814 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3839 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3840 return -EBUSY; in tg3_validate_rxcpu_state()
3845 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3847 return -EEXIST; in tg3_validate_rxcpu_state()
3853 /* tp->lock is held. */
3864 if (!tp->fw) in tg3_load_57766_firmware()
3869 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3881 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3882 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3894 /* tp->lock is held. */
3904 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3908 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3912 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3931 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3933 netdev_err(tp->dev, in tg3_load_tso_firmware()
3936 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3937 return -ENODEV; in tg3_load_tso_firmware()
3944 /* tp->lock is held. */
3958 index -= 4; in __tg3_set_one_mac_addr()
3964 /* tp->lock is held. */
3973 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3979 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3982 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3983 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3984 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3998 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
3999 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4008 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4013 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4030 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4037 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4042 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4043 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4048 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4050 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4052 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4053 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4054 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4056 &tp->link_config.advertising, in tg3_power_down_prepare()
4057 phydev->advertising); in tg3_power_down_prepare()
4081 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4084 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4096 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4097 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4099 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4128 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4130 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4139 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4141 else if (tp->phy_flags & in tg3_power_down_prepare()
4143 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4150 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4164 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4188 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4215 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4218 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4234 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4270 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4271 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4308 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4334 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4357 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4360 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4364 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4366 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4368 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4407 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4408 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4411 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4412 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4418 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4419 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4427 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4428 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4432 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4437 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4438 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4452 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4453 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4464 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4478 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4512 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4513 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4516 err = -EIO; in tg3_phy_pull_config()
4520 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4523 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4526 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4529 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4532 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4533 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4542 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4544 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4546 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4552 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4553 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4556 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4564 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4566 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4568 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4571 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4574 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4586 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4592 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4603 /* Turn off tap power management. */ in tg3_init_5401phy_dsp()
4622 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4627 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4628 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4629 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4630 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4645 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4649 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4650 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4660 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4689 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4702 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4709 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4711 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4713 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4714 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4715 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4752 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4762 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4766 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4784 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4786 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4792 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4798 tp->link_up) { in tg3_setup_copper_phy()
4807 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4828 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4831 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4852 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4854 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4859 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4869 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4870 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4872 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4921 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4922 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4924 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4938 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4945 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4946 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4952 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4955 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4964 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4971 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4979 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4980 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4985 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4989 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4991 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4992 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4993 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4995 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4996 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4997 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4999 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5008 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5010 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5013 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5021 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5022 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5023 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5027 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5028 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5030 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5036 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5038 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5039 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5043 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5058 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5072 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5073 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5074 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5077 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5146 #define ANEG_FAILED -1
5158 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5159 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5160 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5161 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5162 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5163 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5164 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5165 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5166 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5168 ap->cur_time++; in tg3_fiber_aneg_smachine()
5173 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5174 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5175 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5176 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5178 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5179 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5180 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5184 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5186 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5188 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5190 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5191 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5192 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5193 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5194 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5199 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5202 switch (ap->state) { in tg3_fiber_aneg_smachine()
5204 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5205 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5209 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5210 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5211 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5212 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5213 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5214 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5215 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5216 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5217 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5219 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5221 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5226 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5227 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5228 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5230 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5231 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5235 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5239 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5241 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5251 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5252 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5253 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5255 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5257 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5258 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5259 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5260 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5263 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5267 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5268 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5272 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5273 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5274 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5275 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5278 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5282 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5283 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5284 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5285 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5287 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5289 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5290 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5291 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5296 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5300 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5309 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5310 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5311 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5312 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5313 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5314 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5315 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5316 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5317 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5318 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5319 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5320 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5321 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5322 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5324 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5326 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5327 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5328 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5329 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5330 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5331 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5333 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5338 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5339 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5340 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5343 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5345 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5346 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5348 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5349 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5350 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5359 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5360 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5361 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5364 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5369 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5370 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5371 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5374 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5377 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5382 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5412 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5416 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5432 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5433 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5471 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5516 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5517 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5523 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5544 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5547 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5554 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5555 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5559 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5570 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5571 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5591 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5596 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5597 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5599 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5600 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5616 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5624 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5626 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5633 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5634 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5648 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5665 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5695 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5698 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5715 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5716 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5717 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5720 tp->link_up && in tg3_setup_fiber_phy()
5737 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5738 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5739 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5742 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5749 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5757 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5759 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5774 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5775 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5776 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5779 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5784 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5785 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5786 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5790 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5791 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5792 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5798 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5800 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5801 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5825 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5828 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5839 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5848 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5856 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5857 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5865 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5878 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5879 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5881 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5890 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5891 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5899 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5900 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5910 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5920 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5944 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5972 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5986 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5987 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5988 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5990 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5995 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5996 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6004 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6006 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6010 if (!tp->link_up && in tg3_serdes_parallel_detect()
6011 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6037 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6040 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6041 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6042 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6056 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6067 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6069 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6098 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6099 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6107 if (tp->link_up) { in tg3_setup_phy()
6109 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6117 if (!tp->link_up) in tg3_setup_phy()
6119 tp->pwrmgmt_thresh; in tg3_setup_phy()
6128 /* tp->lock must be held */
6141 /* tp->lock must be held */
6158 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6163 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6168 if (tp->ptp_clock) in tg3_get_ts_info()
6169 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6171 info->phc_index = -1; in tg3_get_ts_info()
6173 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6175 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6190 ppb = -ppb; in tg3_ptp_adjfreq()
6194 * accumulator and a programmable correction value. On each clk, the in tg3_ptp_adjfreq()
6223 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6237 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6255 tp->ptp_adjust = 0; in tg3_ptp_settime()
6268 switch (rq->type) { in tg3_ptp_enable()
6271 if (rq->perout.flags) in tg3_ptp_enable()
6272 return -EOPNOTSUPP; in tg3_ptp_enable()
6274 if (rq->perout.index != 0) in tg3_ptp_enable()
6275 return -EINVAL; in tg3_ptp_enable()
6284 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6285 rq->perout.start.nsec; in tg3_ptp_enable()
6287 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6288 netdev_warn(tp->dev, in tg3_ptp_enable()
6289 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6290 rval = -EINVAL; in tg3_ptp_enable()
6295 netdev_warn(tp->dev, in tg3_ptp_enable()
6297 rval = -EINVAL; in tg3_ptp_enable()
6321 return -EOPNOTSUPP; in tg3_ptp_enable()
6344 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6345 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6348 /* tp->lock must be held */
6356 tp->ptp_adjust = 0; in tg3_ptp_init()
6357 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6360 /* tp->lock must be held */
6366 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6367 tp->ptp_adjust = 0; in tg3_ptp_resume()
6372 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6375 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6376 tp->ptp_clock = NULL; in tg3_ptp_fini()
6377 tp->ptp_adjust = 0; in tg3_ptp_fini()
6382 return tp->irq_sync; in tg3_irq_sync()
6465 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6472 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6473 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6476 netdev_err(tp->dev, in tg3_dump_state()
6479 tnapi->hw_status->status, in tg3_dump_state()
6480 tnapi->hw_status->status_tag, in tg3_dump_state()
6481 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6482 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6483 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6484 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6485 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6487 netdev_err(tp->dev, in tg3_dump_state()
6490 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6491 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6492 tnapi->rx_rcb_ptr, in tg3_dump_state()
6493 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6494 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6495 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6496 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6500 /* This is called whenever we suspect that the system chipset is re-
6509 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6511 netdev_warn(tp->dev, in tg3_tx_recover()
6512 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6524 return tnapi->tx_pending - in tg3_tx_avail()
6525 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6534 struct tg3 *tp = tnapi->tp; in tg3_tx()
6535 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6536 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6538 int index = tnapi - tp->napi; in tg3_tx()
6542 index--; in tg3_tx()
6544 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6547 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6548 struct sk_buff *skb = ri->skb; in tg3_tx()
6556 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6566 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6569 ri->skb = NULL; in tg3_tx()
6571 while (ri->fragmented) { in tg3_tx()
6572 ri->fragmented = false; in tg3_tx()
6574 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6579 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6580 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6581 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6584 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6586 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6589 while (ri->fragmented) { in tg3_tx()
6590 ri->fragmented = false; in tg3_tx()
6592 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6599 bytes_compl += skb->len; in tg3_tx()
6611 tnapi->tx_cons = sw_idx; in tg3_tx()
6643 if (!ri->data) in tg3_rx_data_free()
6646 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6648 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6649 ri->data = NULL; in tg3_rx_data_free()
6656 * of the RX descriptor are invariant, see tg3_init_rings.
6659 * posting buffers we only dirty the first cache line of the RX
6660 * descriptor (containing the address). Whereas for the RX status
6661 * buffers the cpu only reads the last cacheline of the RX descriptor
6676 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6677 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6678 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6679 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6683 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6684 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6685 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6690 return -EINVAL; in tg3_alloc_rx_data()
6709 return -ENOMEM; in tg3_alloc_rx_data()
6711 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6713 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6715 return -EIO; in tg3_alloc_rx_data()
6718 map->data = data; in tg3_alloc_rx_data()
6721 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6722 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6728 * members of the RX descriptor are invariant. See notes above
6736 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6739 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6744 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6745 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6746 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6747 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6748 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6752 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6753 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6754 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6755 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6756 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6763 dest_map->data = src_map->data; in tg3_recycle_rx()
6766 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6767 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6774 src_map->data = NULL; in tg3_recycle_rx()
6777 /* The RX ring scheme is composed of multiple rings which post fresh
6783 * RX buffer was obtained from. The chip simply takes the original
6789 * it is first placed into the on-chip ram. When the packet's length
6794 * The "separate ring for rx status" scheme may sound queer, but it makes
6796 * to the buffer post rings, and only the chip writes to the rx status
6797 * rings, then cache lines never move beyond shared-modified state.
6803 struct tg3 *tp = tnapi->tp; in tg3_rx()
6806 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6809 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6811 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6819 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6820 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6823 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6831 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6832 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6834 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6836 data = ri->data; in tg3_rx()
6840 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6842 data = ri->data; in tg3_rx()
6849 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6855 tp->rx_dropped++; in tg3_rx()
6860 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6863 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6865 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6880 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6888 ri->data = NULL; in tg3_rx()
6900 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6906 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6908 memcpy(skb->data, in tg3_rx()
6911 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6920 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6921 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6922 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6924 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6928 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6930 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6931 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6932 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6937 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6938 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6940 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6942 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6945 budget--; in tg3_rx()
6950 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6951 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6952 tp->rx_std_ring_mask; in tg3_rx()
6954 tpr->rx_std_prod_idx); in tg3_rx()
6960 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6964 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6970 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
6971 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
6973 /* Refill RX ring(s). */ in tg3_rx()
6979 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6980 tp->rx_std_ring_mask; in tg3_rx()
6982 tpr->rx_std_prod_idx); in tg3_rx()
6985 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
6986 tp->rx_jmb_ring_mask; in tg3_rx()
6988 tpr->rx_jmb_prod_idx); in tg3_rx()
6996 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
6997 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
6999 if (tnapi != &tp->napi[1]) { in tg3_rx()
7000 tp->rx_refill = true; in tg3_rx()
7001 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7012 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7014 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7015 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7016 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7017 spin_lock(&tp->lock); in tg3_poll_link()
7027 spin_unlock(&tp->lock); in tg3_poll_link()
7040 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7047 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7050 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7051 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7053 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7054 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7057 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7059 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7060 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7063 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7064 cpycnt = i - di; in tg3_rx_prodring_xfer()
7065 err = -ENOSPC; in tg3_rx_prodring_xfer()
7079 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7080 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7085 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7086 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7087 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7088 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7091 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7092 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7093 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7094 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7098 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7105 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7108 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7109 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7111 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7112 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7115 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7117 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7118 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7121 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7122 cpycnt = i - di; in tg3_rx_prodring_xfer()
7123 err = -ENOSPC; in tg3_rx_prodring_xfer()
7137 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7138 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7143 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7144 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7145 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7146 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7149 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7150 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7151 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7152 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7160 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7163 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7169 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7172 /* run RX thread, within the bounds set by NAPI. in tg3_poll_work()
7173 * All RX "locking" is done by ensuring outside in tg3_poll_work()
7174 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7176 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7177 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7179 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7180 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7182 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7183 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7185 tp->rx_refill = false; in tg3_poll_work()
7186 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7188 &tp->napi[i].prodring); in tg3_poll_work()
7192 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7194 dpr->rx_std_prod_idx); in tg3_poll_work()
7196 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7198 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7201 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7209 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7210 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7215 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7216 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7223 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7225 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7236 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7240 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7241 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7244 /* check for RX/TX work to do */ in tg3_poll_msix()
7245 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7246 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7251 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7256 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7261 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7262 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7264 tnapi->coal_now); in tg3_poll_msix()
7291 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7296 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7301 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7317 struct tg3 *tp = tnapi->tp; in tg3_poll()
7319 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7322 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7336 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7340 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7341 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7344 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7367 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7368 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7375 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7376 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7383 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7384 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7385 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7392 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7393 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7398 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7400 netif_carrier_off(tp->dev); in tg3_netif_stop()
7401 netif_tx_disable(tp->dev); in tg3_netif_stop()
7404 /* tp->lock must be held */
7413 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7415 if (tp->link_up) in tg3_netif_start()
7416 netif_carrier_on(tp->dev); in tg3_netif_start()
7419 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7424 __releases(tp->lock) in tg3_irq_quiesce()
7425 __acquires(tp->lock) in tg3_irq_quiesce()
7429 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7431 tp->irq_sync = 1; in tg3_irq_quiesce()
7434 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7436 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7437 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7439 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7443 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7449 spin_lock_bh(&tp->lock); in tg3_full_lock()
7456 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7459 /* One-shot MSI handler - Chip automatically disables interrupt
7465 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7467 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7468 if (tnapi->rx_rcb) in tg3_msi_1shot()
7469 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7472 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7477 /* MSI ISR - No need to check for interrupt sharing and no need to
7484 struct tg3 *tp = tnapi->tp; in tg3_msi()
7486 prefetch(tnapi->hw_status); in tg3_msi()
7487 if (tnapi->rx_rcb) in tg3_msi()
7488 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7490 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7491 * chip-internal interrupt pending events. in tg3_msi()
7492 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7493 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7496 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7498 napi_schedule(&tnapi->napi); in tg3_msi()
7506 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7507 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7515 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7524 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7525 * chip-internal interrupt pending events. in tg3_interrupt()
7526 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7527 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7530 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7537 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7539 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7540 napi_schedule(&tnapi->napi); in tg3_interrupt()
7542 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7555 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7556 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7564 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7573 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7574 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7575 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7576 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7579 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7591 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7596 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7598 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7608 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7609 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7611 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7628 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7629 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7667 /* Test for DMA addresses > 40-bit */
7684 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7685 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7686 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7687 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7694 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7709 if (tp->dma_limit) { in tg3_tx_frag_set()
7712 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7713 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7714 len -= tp->dma_limit; in tg3_tx_frag_set()
7718 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7719 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7722 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7724 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7726 *budget -= 1; in tg3_tx_frag_set()
7735 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7737 *budget -= 1; in tg3_tx_frag_set()
7741 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7745 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7757 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7759 skb = txb->skb; in tg3_tx_skb_unmap()
7760 txb->skb = NULL; in tg3_tx_skb_unmap()
7762 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7765 while (txb->fragmented) { in tg3_tx_skb_unmap()
7766 txb->fragmented = false; in tg3_tx_skb_unmap()
7768 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7772 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7775 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7777 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7781 while (txb->fragmented) { in tg3_tx_skb_unmap()
7782 txb->fragmented = false; in tg3_tx_skb_unmap()
7784 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7789 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7795 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7803 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7811 ret = -1; in tigon3_dma_hwbug_workaround()
7814 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7815 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7817 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7819 ret = -1; in tigon3_dma_hwbug_workaround()
7825 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7826 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7830 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7832 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7834 ret = -1; in tigon3_dma_hwbug_workaround()
7849 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7860 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7879 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7886 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7901 int i = -1, would_hit_hwbug; in tg3_start_xmit()
7912 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7919 * and TX reclaim runs via tp->napi.poll inside of a software in tg3_start_xmit()
7923 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
7934 entry = tnapi->tx_prod; in tg3_start_xmit()
7937 mss = skb_shinfo(skb)->gso_size; in tg3_start_xmit()
7947 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in tg3_start_xmit()
7952 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
7953 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
7966 ip_csum = iph->check; in tg3_start_xmit()
7967 ip_tot_len = iph->tot_len; in tg3_start_xmit()
7968 iph->check = 0; in tg3_start_xmit()
7969 iph->tot_len = htons(mss + hdr_len); in tg3_start_xmit()
7976 tcp_csum = tcph->check; in tg3_start_xmit()
7981 tcph->check = 0; in tg3_start_xmit()
7984 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in tg3_start_xmit()
7997 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8000 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8004 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8007 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8011 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in tg3_start_xmit()
8015 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
8016 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
8025 !mss && skb->len > VLAN_ETH_FRAME_LEN) in tg3_start_xmit()
8033 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in tg3_start_xmit()
8035 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in tg3_start_xmit()
8041 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in tg3_start_xmit()
8043 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8047 tnapi->tx_buffers[entry].skb = skb; in tg3_start_xmit()
8048 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in tg3_start_xmit()
8056 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in tg3_start_xmit()
8059 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
8070 last = skb_shinfo(skb)->nr_frags - 1; in tg3_start_xmit()
8072 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_start_xmit()
8075 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8078 tnapi->tx_buffers[entry].skb = NULL; in tg3_start_xmit()
8079 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in tg3_start_xmit()
8081 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8096 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in tg3_start_xmit()
8103 iph->check = ip_csum; in tg3_start_xmit()
8104 iph->tot_len = ip_tot_len; in tg3_start_xmit()
8106 tcph->check = tcp_csum; in tg3_start_xmit()
8113 entry = tnapi->tx_prod; in tg3_start_xmit()
8121 netdev_tx_sent_queue(txq, skb->len); in tg3_start_xmit()
8126 tnapi->tx_prod = entry; in tg3_start_xmit()
8142 tw32_tx_mbox(tnapi->prodmbox, entry); in tg3_start_xmit()
8148 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in tg3_start_xmit()
8149 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in tg3_start_xmit()
8153 tp->tx_dropped++; in tg3_start_xmit()
8160 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8163 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8166 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8168 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8169 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8171 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8173 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8176 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8178 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8181 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8193 return -EIO; in tg3_phy_lpbk_set()
8204 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8214 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8230 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8235 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8245 /* Reset to prevent losing 1st rx packet intermittently */ in tg3_phy_lpbk_set()
8246 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8250 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8253 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8261 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8283 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8286 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8288 netif_carrier_on(tp->dev); in tg3_set_loopback()
8289 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8292 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8295 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8299 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8309 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8317 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8330 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8331 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8332 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8333 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8334 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8337 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8338 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8339 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8340 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8348 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8349 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8350 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8353 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8354 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8359 /* Initialize rx rings for packet processing.
8363 * end up in the driver. tp->{tx,}lock are held and thus
8371 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8372 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8373 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8374 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8376 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8377 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8379 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8380 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8386 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8390 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8392 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8396 * write into the rx buffer posting rings. in tg3_rx_prodring_alloc()
8398 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8401 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8402 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8403 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8404 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8408 /* Now allocate fresh SKBs for each rx ring. */ in tg3_rx_prodring_alloc()
8409 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8414 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8415 "Using a smaller RX standard ring. Only " in tg3_rx_prodring_alloc()
8417 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8420 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8428 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8433 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8436 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8437 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8438 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8440 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8444 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8449 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8450 "Using a smaller RX jumbo ring. Only %d " in tg3_rx_prodring_alloc()
8452 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8455 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8465 return -ENOMEM; in tg3_rx_prodring_alloc()
8471 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8472 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8473 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8474 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8475 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8476 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8477 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8478 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8480 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8481 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8482 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8483 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8490 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8492 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8493 return -ENOMEM; in tg3_rx_prodring_init()
8495 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8497 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8499 if (!tpr->rx_std) in tg3_rx_prodring_init()
8503 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8505 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8508 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8510 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8512 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8520 return -ENOMEM; in tg3_rx_prodring_init()
8523 /* Free up pending packets in all rx/tx rings.
8527 * end up in the driver. tp->{tx,}lock is not held and we are not
8534 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8535 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8537 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8539 if (!tnapi->tx_buffers) in tg3_free_rings()
8543 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8549 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8553 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8557 /* Initialize tx/rx rings for packet processing.
8561 * end up in the driver. tp->{tx,}lock are held and thus
8571 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8572 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8574 tnapi->last_tag = 0; in tg3_init_rings()
8575 tnapi->last_irq_tag = 0; in tg3_init_rings()
8576 tnapi->hw_status->status = 0; in tg3_init_rings()
8577 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8578 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8580 tnapi->tx_prod = 0; in tg3_init_rings()
8581 tnapi->tx_cons = 0; in tg3_init_rings()
8582 if (tnapi->tx_ring) in tg3_init_rings()
8583 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8585 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8586 if (tnapi->rx_rcb) in tg3_init_rings()
8587 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8589 if (tnapi->prodring.rx_std && in tg3_init_rings()
8590 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8592 return -ENOMEM; in tg3_init_rings()
8603 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8604 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8606 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8607 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8608 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8609 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8612 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8613 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8620 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8628 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8629 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8632 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8635 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8637 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8639 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8647 return -ENOMEM; in tg3_mem_tx_acquire()
8654 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8655 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8657 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8659 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8662 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8664 tnapi->rx_rcb, in tg3_mem_rx_release()
8665 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8666 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8674 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8683 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8685 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8689 * does not handle rx or tx interrupts. in tg3_mem_rx_acquire()
8695 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8697 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8699 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8707 return -ENOMEM; in tg3_mem_rx_acquire()
8718 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8719 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8721 if (tnapi->hw_status) { in tg3_free_consistent()
8722 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8723 tnapi->hw_status, in tg3_free_consistent()
8724 tnapi->status_mapping); in tg3_free_consistent()
8725 tnapi->hw_status = NULL; in tg3_free_consistent()
8732 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8734 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8736 if (tp->hw_stats) { in tg3_free_consistent()
8737 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8738 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8739 tp->hw_stats = NULL; in tg3_free_consistent()
8751 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8753 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8754 if (!tp->hw_stats) in tg3_alloc_consistent()
8757 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8758 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8761 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8763 &tnapi->status_mapping, in tg3_alloc_consistent()
8765 if (!tnapi->hw_status) in tg3_alloc_consistent()
8768 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8777 * other three rx return ring producer indexes. in tg3_alloc_consistent()
8781 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8784 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8787 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8790 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8793 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8795 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8806 return -ENOMEM; in tg3_alloc_consistent()
8812 * clears. tp->lock is held.
8841 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8842 dev_err(&tp->pdev->dev, in tg3_stop_block()
8846 return -ENODEV; in tg3_stop_block()
8856 dev_err(&tp->pdev->dev, in tg3_stop_block()
8859 return -ENODEV; in tg3_stop_block()
8865 /* tp->lock is held. */
8872 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8873 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8874 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8875 err = -ENODEV; in tg3_abort_hw()
8879 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8880 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8898 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8899 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8902 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8903 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8911 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8914 err |= -ENODEV; in tg3_abort_hw()
8928 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8929 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8930 if (tnapi->hw_status) in tg3_abort_hw()
8931 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
8940 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8948 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
8949 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8950 tp->misc_host_ctrl); in tg3_restore_pci_state()
8962 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8964 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8967 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8968 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8969 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8970 tp->pci_lat_timer); in tg3_restore_pci_state()
8973 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
8977 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8980 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8992 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
8993 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
8995 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
8996 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9047 /* tp->lock is held. */
9049 __releases(tp->lock) in tg3_chip_reset()
9050 __acquires(tp->lock) in tg3_chip_reset()
9056 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9057 return -ENODEV; in tg3_chip_reset()
9066 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9084 write_op = tp->write32; in tg3_chip_reset()
9086 tp->write32 = tg3_write32; in tg3_chip_reset()
9095 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9096 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9097 if (tnapi->hw_status) { in tg3_chip_reset()
9098 tnapi->hw_status->status = 0; in tg3_chip_reset()
9099 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9101 tnapi->last_tag = 0; in tg3_chip_reset()
9102 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9108 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9109 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9155 tp->write32 = write_op; in tg3_chip_reset()
9157 /* Unfortunately, we have to delay before the PCI read back. in tg3_chip_reset()
9178 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9182 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9193 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9194 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9206 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9209 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9234 * potentially defective internal ROM, stop the Rx RISC CPU, in tg3_chip_reset()
9245 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9253 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9255 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9257 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9258 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9261 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9262 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9263 val = tp->mac_mode; in tg3_chip_reset()
9264 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9265 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9266 val = tp->mac_mode; in tg3_chip_reset()
9299 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9310 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9316 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9318 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9329 /* tp->lock is held. */
9346 if (tp->hw_stats) { in tg3_halt()
9348 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9349 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9352 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9365 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9366 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9368 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9386 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9389 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9394 /* tp->lock is held. */
9421 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9422 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9423 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9429 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9433 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9435 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9437 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9441 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9451 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9454 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9455 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9456 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9457 limit--; in tg3_coal_rx_init()
9468 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9470 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9472 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9475 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9488 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9490 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9491 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9493 if (!tp->link_up) in __tg3_set_coalesce()
9500 /* tp->lock is held. */
9522 /* tp->lock is held. */
9531 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9532 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9534 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9537 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9543 /* tp->lock is held. */
9566 /* tp->lock is held. */
9575 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9576 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9578 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9581 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9582 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9587 /* tp->lock is held. */
9592 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9599 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9600 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9601 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9602 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9606 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9607 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9608 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9610 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9611 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9612 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9613 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9614 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9615 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9618 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9620 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9621 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9622 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9623 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9626 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9634 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9638 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9640 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9644 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9645 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9651 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9674 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9675 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9688 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9735 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9746 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9749 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9764 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9779 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9785 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9791 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9792 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9803 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9813 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9814 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9820 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9825 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9834 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9838 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9853 /* tp->lock is held. */
9858 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9869 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9870 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9873 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9877 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9991 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
9992 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10038 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10044 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10047 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10051 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10053 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10054 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10056 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10059 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10062 if (tp->rxptpctl) in tg3_reset_hw()
10064 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10069 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10075 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10076 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10101 fw_len = tp->fw_len; in tg3_reset_hw()
10102 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10106 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10109 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10111 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10113 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10115 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10118 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10120 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10122 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10125 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10127 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10144 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10145 return -ENODEV; in tg3_reset_hw()
10154 * RCVDBDI_STD_BD: standard eth size rx ring in tg3_reset_hw()
10155 * RCVDBDI_JUMBO_BD: jumbo frame rx ring in tg3_reset_hw()
10156 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) in tg3_reset_hw()
10160 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | in tg3_reset_hw()
10171 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10173 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10191 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10193 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10219 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10220 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10222 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10223 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10224 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10233 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10287 tp->dma_limit = 0; in tg3_reset_hw()
10288 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10290 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10376 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10384 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10386 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10400 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10407 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10408 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10409 /* reset to prevent losing 1st rx packet intermittently */ in tg3_reset_hw()
10414 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10418 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10420 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10422 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10423 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10426 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10446 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10447 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10451 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10454 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10460 if (tp->irq_cnt > 1) in tg3_reset_hw()
10503 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10512 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10579 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10583 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10588 tp->tx_mode &= ~val; in tg3_reset_hw()
10589 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10592 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10606 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10608 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10611 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10614 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10621 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10624 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10627 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10631 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10634 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10636 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10638 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10658 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10659 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10663 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10669 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10670 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10671 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10675 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10676 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10682 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10683 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10695 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10708 limit -= 4; in tg3_reset_hw()
10768 * packet processing. Invoked with tp->lock held.
10795 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10796 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10809 spin_lock_bh(&tp->lock); in tg3_show_temp()
10810 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10812 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10834 if (tp->hwmon_dev) { in tg3_hwmon_close()
10835 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10836 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10844 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10860 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10862 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10863 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10864 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10875 (PSTAT)->low += __val; \
10876 if ((PSTAT)->low < __val) \
10877 (PSTAT)->high += 1; \
10882 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10884 if (!tp->link_up) in tg3_periodic_fetch_stats()
10887 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10888 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10889 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10890 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10891 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10892 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10893 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10894 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10895 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10896 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10897 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10898 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10899 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10901 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10902 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
10911 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10912 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
10913 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
10914 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
10915 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
10916 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
10917 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
10918 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10919 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10920 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
10921 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
10922 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
10923 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
10924 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
10926 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
10931 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
10937 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
10938 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
10939 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
10941 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
10943 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
10950 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10951 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10954 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
10955 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
10956 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
10957 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
10963 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
10964 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
10965 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
10973 spin_lock(&tp->lock); in tg3_timer()
10975 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10976 spin_unlock(&tp->lock); in tg3_timer()
10990 /* All of this garbage is because when using non-tagged in tg3_timer()
10994 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
10996 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
10998 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11003 spin_unlock(&tp->lock); in tg3_timer()
11010 if (!--tp->timer_counter) { in tg3_timer()
11014 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11024 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11036 if (tp->link_up && in tg3_timer()
11040 if (!tp->link_up && in tg3_timer()
11046 if (!tp->serdes_counter) { in tg3_timer()
11048 (tp->mac_mode & in tg3_timer()
11051 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11056 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11064 if (link_up != tp->link_up) in tg3_timer()
11068 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11076 * that may be filled with rx packets destined for the host. in tg3_timer()
11088 if (!--tp->asf_counter) { in tg3_timer()
11100 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11106 spin_unlock(&tp->lock); in tg3_timer()
11109 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11110 add_timer(&tp->timer); in tg3_timer()
11118 tp->timer_offset = HZ; in tg3_timer_init()
11120 tp->timer_offset = HZ / 10; in tg3_timer_init()
11122 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11124 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11125 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11128 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11133 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11134 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11136 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11137 add_timer(&tp->timer); in tg3_timer_start()
11142 del_timer_sync(&tp->timer); in tg3_timer_stop()
11145 /* Restart hardware after configuration changes, self-test, etc.
11146 * Invoked with tp->lock held.
11149 __releases(tp->lock) in tg3_restart_hw()
11150 __acquires(tp->lock) in tg3_restart_hw()
11156 netdev_err(tp->dev, in tg3_restart_hw()
11157 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11161 tp->irq_sync = 0; in tg3_restart_hw()
11163 dev_close(tp->dev); in tg3_restart_hw()
11177 if (!netif_running(tp->dev)) { in tg3_reset_task()
11193 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11194 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11203 tp->irq_sync = 0; in tg3_reset_task()
11209 dev_close(tp->dev); in tg3_reset_task()
11226 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11228 if (tp->irq_cnt == 1) in tg3_request_irq()
11229 name = tp->dev->name; in tg3_request_irq()
11231 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11232 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11234 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11235 else if (tnapi->tx_buffers) in tg3_request_irq()
11237 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11238 else if (tnapi->rx_rcb) in tg3_request_irq()
11240 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11243 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11244 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11259 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11264 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11265 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11270 return -ENODEV; in tg3_test_interrupt()
11274 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11285 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11286 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11290 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11293 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11294 tnapi->coal_now); in tg3_test_interrupt()
11299 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11309 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11310 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11317 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11333 return -EIO; in tg3_test_interrupt()
11350 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11351 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11356 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11362 if (err != -EIO) in tg3_test_msi()
11366 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11370 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11372 pci_disable_msi(tp->pdev); in tg3_test_msi()
11375 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11392 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11401 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11402 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11403 tp->fw_needed); in tg3_request_firmware()
11404 return -ENOENT; in tg3_request_firmware()
11407 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11414 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11415 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11416 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11417 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11418 release_firmware(tp->fw); in tg3_request_firmware()
11419 tp->fw = NULL; in tg3_request_firmware()
11420 return -EINVAL; in tg3_request_firmware()
11424 tp->fw_needed = NULL; in tg3_request_firmware()
11430 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11433 /* We want as many rx rings enabled as there are cpus. in tg3_irq_count()
11434 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11438 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11449 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11450 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11451 if (!tp->rxq_cnt) in tg3_enable_msix()
11452 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11453 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11454 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11456 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11460 if (!tp->txq_req) in tg3_enable_msix()
11461 tp->txq_cnt = 1; in tg3_enable_msix()
11463 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11465 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11470 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11473 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11474 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11475 tp->irq_cnt, rc); in tg3_enable_msix()
11476 tp->irq_cnt = rc; in tg3_enable_msix()
11477 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11478 if (tp->txq_cnt) in tg3_enable_msix()
11479 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11482 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11483 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11485 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11486 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11490 if (tp->irq_cnt == 1) in tg3_enable_msix()
11495 if (tp->txq_cnt > 1) in tg3_enable_msix()
11498 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11510 netdev_warn(tp->dev, in tg3_ints_init()
11517 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11522 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11530 tp->irq_cnt = 1; in tg3_ints_init()
11531 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11534 if (tp->irq_cnt == 1) { in tg3_ints_init()
11535 tp->txq_cnt = 1; in tg3_ints_init()
11536 tp->rxq_cnt = 1; in tg3_ints_init()
11537 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11538 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11545 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11547 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11557 struct net_device *dev = tp->dev; in tg3_start()
11579 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11582 for (i--; i >= 0; i--) { in tg3_start()
11583 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11585 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11647 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11648 tg3_set_loopback(dev, dev->features); in tg3_start()
11653 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11654 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11655 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11692 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11693 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11694 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11709 if (tp->pcierr_recovery) { in tg3_open()
11712 return -EAGAIN; in tg3_open()
11715 if (tp->fw_needed) { in tg3_open()
11719 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11720 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11721 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11722 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11723 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11729 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11732 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11751 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11755 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11765 if (tp->pcierr_recovery) { in tg3_close()
11768 return -EAGAIN; in tg3_close()
11773 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11783 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11788 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11790 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11802 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11804 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11807 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11811 estats->member = old_estats->member + \
11812 get_stat64(&hw_stats->member)
11816 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11817 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11900 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11901 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11903 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
11904 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
11905 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
11906 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
11908 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
11909 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
11910 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
11911 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
11913 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
11914 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
11915 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
11916 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
11918 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
11919 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
11920 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
11921 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
11922 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
11923 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
11924 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11926 stats->multicast = old_stats->multicast + in tg3_get_nstats()
11927 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
11928 stats->collisions = old_stats->collisions + in tg3_get_nstats()
11929 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
11931 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
11932 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
11933 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
11935 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
11936 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
11937 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
11938 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11939 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
11940 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
11942 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
11945 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
11946 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
11948 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11949 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11962 regs->version = 0; in tg3_get_regs()
11966 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11980 return tp->nvram_size; in tg3_get_eeprom_len()
11992 return -EINVAL; in tg3_get_eeprom()
11994 offset = eeprom->offset; in tg3_get_eeprom()
11995 len = eeprom->len; in tg3_get_eeprom()
11996 eeprom->len = 0; in tg3_get_eeprom()
11998 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12016 b_count = 4 - b_offset; in tg3_get_eeprom()
12021 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12025 len -= b_count; in tg3_get_eeprom()
12027 eeprom->len += b_count; in tg3_get_eeprom()
12031 pd = &data[eeprom->len]; in tg3_get_eeprom()
12032 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12036 i -= 4; in tg3_get_eeprom()
12037 eeprom->len += i; in tg3_get_eeprom()
12043 eeprom->len += i; in tg3_get_eeprom()
12044 ret = -EINTR; in tg3_get_eeprom()
12050 eeprom->len += i; in tg3_get_eeprom()
12054 pd = &data[eeprom->len]; in tg3_get_eeprom()
12056 b_offset = offset + len - b_count; in tg3_get_eeprom()
12061 eeprom->len += b_count; in tg3_get_eeprom()
12083 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12084 return -EINVAL; in tg3_set_eeprom()
12086 offset = eeprom->offset; in tg3_set_eeprom()
12087 len = eeprom->len; in tg3_set_eeprom()
12091 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12105 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12114 return -ENOMEM; in tg3_set_eeprom()
12118 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12119 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12139 return -EAGAIN; in tg3_get_link_ksettings()
12140 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12148 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12152 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12158 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12161 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12163 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12166 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12168 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12169 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12175 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12179 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12182 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12183 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12184 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12186 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12187 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12189 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12190 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12191 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12193 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12196 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12197 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12198 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12200 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12201 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12209 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12214 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12215 return -EAGAIN; in tg3_set_link_ksettings()
12216 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12220 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12221 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12222 return -EINVAL; in tg3_set_link_ksettings()
12224 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12225 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12226 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12227 return -EINVAL; in tg3_set_link_ksettings()
12230 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12232 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12237 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12241 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12251 return -EINVAL; in tg3_set_link_ksettings()
12262 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12264 return -EINVAL; in tg3_set_link_ksettings()
12266 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12267 return -EINVAL; in tg3_set_link_ksettings()
12271 return -EINVAL; in tg3_set_link_ksettings()
12277 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12278 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12279 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12281 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12282 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12284 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12285 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12286 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12289 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12305 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12306 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12307 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12314 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12315 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12317 wol->supported = 0; in tg3_get_wol()
12318 wol->wolopts = 0; in tg3_get_wol()
12319 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12320 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12321 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12327 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12329 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12330 return -EINVAL; in tg3_set_wol()
12331 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12333 return -EINVAL; in tg3_set_wol()
12335 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12348 return tp->msg_enable; in tg3_get_msglevel()
12354 tp->msg_enable = value; in tg3_set_msglevel()
12363 return -EAGAIN; in tg3_nway_reset()
12365 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12366 return -EINVAL; in tg3_nway_reset()
12371 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12372 return -EAGAIN; in tg3_nway_reset()
12373 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12377 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12378 r = -EINVAL; in tg3_nway_reset()
12382 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12387 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12400 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12402 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12404 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12406 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12408 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12410 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12412 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12414 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12426 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12427 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12428 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12429 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12431 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12432 return -EINVAL; in tg3_set_ringparam()
12442 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12445 tp->rx_pending > 63) in tg3_set_ringparam()
12446 tp->rx_pending = 63; in tg3_set_ringparam()
12449 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12451 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12452 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12479 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12481 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12482 epause->rx_pause = 1; in tg3_get_pauseparam()
12484 epause->rx_pause = 0; in tg3_get_pauseparam()
12486 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12487 epause->tx_pause = 1; in tg3_get_pauseparam()
12489 epause->tx_pause = 0; in tg3_get_pauseparam()
12498 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12504 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12507 return -EINVAL; in tg3_set_pauseparam()
12509 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12510 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12511 if (epause->rx_pause) { in tg3_set_pauseparam()
12512 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12514 if (epause->tx_pause) { in tg3_set_pauseparam()
12515 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12517 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12518 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12521 if (epause->autoneg) in tg3_set_pauseparam()
12526 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12527 if (phydev->autoneg) { in tg3_set_pauseparam()
12538 if (!epause->autoneg) in tg3_set_pauseparam()
12551 if (epause->autoneg) in tg3_set_pauseparam()
12555 if (epause->rx_pause) in tg3_set_pauseparam()
12556 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12558 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12559 if (epause->tx_pause) in tg3_set_pauseparam()
12560 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12562 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12580 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12593 return -EOPNOTSUPP; in tg3_get_sset_count()
12603 return -EOPNOTSUPP; in tg3_get_rxnfc()
12605 switch (info->cmd) { in tg3_get_rxnfc()
12607 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12608 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12610 info->data = num_online_cpus(); in tg3_get_rxnfc()
12611 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12612 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12618 return -EOPNOTSUPP; in tg3_get_rxnfc()
12644 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12660 return -EOPNOTSUPP; in tg3_set_rxfh()
12666 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12687 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12688 channel->max_tx = tp->txq_max; in tg3_get_channels()
12691 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12692 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12694 if (tp->rxq_req) in tg3_get_channels()
12695 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12697 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12699 if (tp->txq_req) in tg3_get_channels()
12700 channel->tx_count = tp->txq_req; in tg3_get_channels()
12702 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12712 return -EOPNOTSUPP; in tg3_set_channels()
12714 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12715 channel->tx_count > tp->txq_max) in tg3_set_channels()
12716 return -EINVAL; in tg3_set_channels()
12718 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12719 tp->txq_req = channel->tx_count; in tg3_set_channels()
12773 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12785 if (tp->hw_stats) in tg3_get_ethtool_stats()
12831 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12832 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12840 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12873 return -EIO; in tg3_test_nvram()
12900 return -EIO; in tg3_test_nvram()
12907 return -EIO; in tg3_test_nvram()
12911 return -ENOMEM; in tg3_test_nvram()
12913 err = -EIO; in tg3_test_nvram()
12945 err = -EIO; in tg3_test_nvram()
12979 err = -EIO; in tg3_test_nvram()
12992 err = -EIO; in tg3_test_nvram()
13008 return -ENOMEM; in tg3_test_nvram()
13026 if (!netif_running(tp->dev)) in tg3_test_link()
13027 return -ENODEV; in tg3_test_link()
13029 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13035 if (tp->link_up) in tg3_test_link()
13042 return -EIO; in tg3_test_link()
13223 /* Determine the read-only value. */ in tg3_test_registers()
13226 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13233 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13238 * make sure the read-only bits are not changed and the in tg3_test_registers()
13245 /* Test the read-only bits. */ in tg3_test_registers()
13260 netdev_err(tp->dev, in tg3_test_registers()
13263 return -EIO; in tg3_test_registers()
13279 return -EIO; in tg3_do_mem_test()
13389 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13391 tnapi = &tp->napi[0]; in tg3_run_loopback()
13392 rnapi = &tp->napi[0]; in tg3_run_loopback()
13393 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13395 rnapi = &tp->napi[1]; in tg3_run_loopback()
13397 tnapi = &tp->napi[1]; in tg3_run_loopback()
13399 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13401 err = -EIO; in tg3_run_loopback()
13404 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13406 return -ENOMEM; in tg3_run_loopback()
13409 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13424 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13428 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13439 th->check = 0; in tg3_run_loopback()
13470 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13471 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13473 return -EIO; in tg3_run_loopback()
13476 val = tnapi->tx_prod; in tg3_run_loopback()
13477 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13478 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13480 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13481 rnapi->coal_now); in tg3_run_loopback()
13485 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13490 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13492 return -EIO; in tg3_run_loopback()
13495 tnapi->tx_prod++; in tg3_run_loopback()
13500 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13501 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13507 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13512 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13513 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13514 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13519 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13522 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13530 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13531 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13532 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13534 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13535 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13538 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13539 - ETH_FCS_LEN; in tg3_run_loopback()
13545 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13552 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13553 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13559 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13560 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13563 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13564 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13569 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13596 int err = -EIO; in tg3_test_loopback()
13600 if (tp->dma_limit) in tg3_test_loopback()
13601 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13603 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13604 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13606 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13626 /* Reroute all rx packets to the 1st queue */ in tg3_test_loopback()
13632 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13651 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13695 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13696 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13701 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13704 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13713 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13715 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13717 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13727 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13731 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13734 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13752 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13756 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13761 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13766 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13769 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13774 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13793 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13804 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13806 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13807 return -EFAULT; in tg3_hwtstamp_set()
13811 return -ERANGE; in tg3_hwtstamp_set()
13815 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13818 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13822 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13826 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13830 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13834 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13838 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13842 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13846 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13850 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13854 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13858 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13862 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13866 return -ERANGE; in tg3_hwtstamp_set()
13869 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13871 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13878 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13879 -EFAULT : 0; in tg3_hwtstamp_set()
13888 return -EOPNOTSUPP; in tg3_hwtstamp_get()
13894 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13936 return -ERANGE; in tg3_hwtstamp_get()
13939 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
13940 -EFAULT : 0; in tg3_hwtstamp_get()
13951 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
13952 return -EAGAIN; in tg3_ioctl()
13953 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
13959 data->phy_id = tp->phy_addr; in tg3_ioctl()
13965 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
13969 return -EAGAIN; in tg3_ioctl()
13971 spin_lock_bh(&tp->lock); in tg3_ioctl()
13972 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
13973 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
13974 spin_unlock_bh(&tp->lock); in tg3_ioctl()
13976 data->val_out = mii_regval; in tg3_ioctl()
13982 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
13986 return -EAGAIN; in tg3_ioctl()
13988 spin_lock_bh(&tp->lock); in tg3_ioctl()
13989 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
13990 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
13991 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14005 return -EOPNOTSUPP; in tg3_ioctl()
14015 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14035 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14036 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14037 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14038 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14039 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14040 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14041 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14042 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14043 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14044 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14045 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14046 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14047 return -EINVAL; in tg3_set_coalesce()
14050 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14051 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14052 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14053 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14054 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14055 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14056 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14057 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14058 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14062 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14072 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14073 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14074 return -EOPNOTSUPP; in tg3_set_eee()
14077 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14078 netdev_warn(tp->dev, in tg3_set_eee()
14080 return -EINVAL; in tg3_set_eee()
14083 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14084 netdev_warn(tp->dev, in tg3_set_eee()
14087 return -EINVAL; in tg3_set_eee()
14090 tp->eee = *edata; in tg3_set_eee()
14092 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14095 if (netif_running(tp->dev)) { in tg3_set_eee()
14109 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14110 netdev_warn(tp->dev, in tg3_get_eee()
14112 return -EOPNOTSUPP; in tg3_get_eee()
14115 *edata = tp->eee; in tg3_get_eee()
14166 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14167 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14168 *stats = tp->net_stats_prev; in tg3_get_stats64()
14169 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14174 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14192 dev->mtu = new_mtu; in tg3_set_mtu()
14278 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14295 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14305 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14324 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14328 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14331 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14334 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14338 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14357 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14358 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14362 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14363 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14366 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14367 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14371 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14372 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14376 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14377 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14381 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14382 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14386 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14387 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14396 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14399 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14402 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14405 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14408 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14411 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14414 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14432 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14436 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14443 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14453 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14478 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14481 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14484 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14487 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14490 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14496 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14499 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14501 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14505 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14509 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14527 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14529 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14538 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14541 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14546 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14549 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14576 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14580 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14590 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14593 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14598 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14605 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14611 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14617 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14623 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14631 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14633 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14645 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14647 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14659 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14667 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14671 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14675 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14682 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14688 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14691 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14694 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14704 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14718 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14720 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14732 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14742 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14745 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14759 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14770 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14773 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14783 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14806 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14807 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14812 tp->nvram_size = in tg3_get_5720_nvram_info()
14836 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14842 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14844 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14858 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14866 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14871 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14875 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14879 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14901 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14910 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14916 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14922 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14926 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14936 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14979 netdev_warn(tp->dev, in tg3_nvram_init()
14986 tp->nvram_size = 0; in tg3_nvram_init()
15012 if (tp->nvram_size == 0) in tg3_nvram_init()
15101 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15103 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15113 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15114 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15131 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15144 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15177 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15180 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15182 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15194 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15198 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15202 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15209 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15214 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15217 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15222 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15228 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15232 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15234 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15242 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15243 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15246 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15250 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15252 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15253 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15270 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15277 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15281 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15283 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15286 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15292 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15303 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15305 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15316 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15320 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15323 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15356 return -EBUSY; in tg3_ape_otp_read()
15375 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15379 * configuration is a 32-bit value that straddles the alignment boundary.
15380 * We do two 32-bit reads and then shift and merge the results.
15412 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15413 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15418 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15427 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15428 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15429 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15430 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15431 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15432 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15434 tp->old_link = -1; in tg3_phy_init_link_config()
15445 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15448 switch (tp->pci_fn) { in tg3_phy_probe()
15450 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15453 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15456 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15459 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15465 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15466 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15467 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15482 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15496 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15498 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15500 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15502 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15514 tp->phy_id = p->phy_id; in tg3_phy_probe()
15523 return -ENODEV; in tg3_phy_probe()
15526 if (!tp->phy_id || in tg3_phy_probe()
15527 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15528 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15532 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15541 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15543 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15545 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15547 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15548 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15549 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15554 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15555 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15572 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15573 tp->link_config.flowctrl); in tg3_phy_probe()
15581 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15615 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15616 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15627 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15631 if (tp->board_part_number[0]) in tg3_read_vpd()
15636 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15637 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15638 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15639 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15640 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15644 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15645 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15646 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15647 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15648 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15649 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15650 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15651 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15655 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15656 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15657 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15658 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15659 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15660 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15661 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15662 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15663 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15664 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15665 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15666 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15670 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15671 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15672 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15673 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15674 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15675 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15676 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15677 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15681 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15684 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15724 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15727 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15731 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15737 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15748 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15766 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15773 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15813 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15814 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15818 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15819 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15820 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15844 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15852 offset += val - start; in tg3_read_mgmtfw_ver()
15854 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15856 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15857 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15866 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15867 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15871 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15902 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15907 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15909 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15937 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
15938 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
15947 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
15951 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
15976 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
15999 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16002 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16003 if (peer && peer != tp->pdev) in tg3_find_peer()
16007 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16008 * tp->pdev in that case. in tg3_find_peer()
16011 peer = tp->pdev; in tg3_find_peer()
16026 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16035 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16047 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16049 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16050 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16051 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16052 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16053 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16054 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16055 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16056 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16061 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16068 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16071 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16119 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16122 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16124 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16149 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16151 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16153 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16158 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16160 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16162 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16163 tp->misc_host_ctrl); in tg3_get_invariants()
16173 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16176 * non-zero address during special cycles. However, only in tg3_get_invariants()
16177 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16204 while (pci_id->vendor != 0) { in tg3_get_invariants()
16205 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16211 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16212 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16215 if (bridge->subordinate && in tg3_get_invariants()
16216 (bridge->subordinate->number == in tg3_get_invariants()
16217 tp->pdev->bus->number)) { in tg3_get_invariants()
16237 while (pci_id->vendor != 0) { in tg3_get_invariants()
16238 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16239 pci_id->device, in tg3_get_invariants()
16245 if (bridge->subordinate && in tg3_get_invariants()
16246 (bridge->subordinate->number <= in tg3_get_invariants()
16247 tp->pdev->bus->number) && in tg3_get_invariants()
16248 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16249 tp->pdev->bus->number)) { in tg3_get_invariants()
16258 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16259 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16260 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16265 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16273 if (bridge && bridge->subordinate && in tg3_get_invariants()
16274 (bridge->subordinate->number <= in tg3_get_invariants()
16275 tp->pdev->bus->number) && in tg3_get_invariants()
16276 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16277 tp->pdev->bus->number)) { in tg3_get_invariants()
16287 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16309 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16311 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16327 tp->fw_needed = NULL; in tg3_get_invariants()
16331 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16334 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16336 tp->irq_max = 1; in tg3_get_invariants()
16344 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16354 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16358 tp->txq_max = 1; in tg3_get_invariants()
16359 tp->rxq_max = 1; in tg3_get_invariants()
16360 if (tp->irq_max > 1) { in tg3_get_invariants()
16361 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16366 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16374 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16391 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16394 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16399 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16421 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16422 if (!tp->pcix_cap) { in tg3_get_invariants()
16423 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16424 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16425 return -EIO; in tg3_get_invariants()
16442 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16443 &tp->pci_cacheline_sz); in tg3_get_invariants()
16444 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16445 &tp->pci_lat_timer); in tg3_get_invariants()
16447 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16448 tp->pci_lat_timer = 64; in tg3_get_invariants()
16449 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16450 tp->pci_lat_timer); in tg3_get_invariants()
16453 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16462 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16476 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16477 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16481 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16482 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16486 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16488 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16497 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16501 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16505 tp->read32 = tg3_read32; in tg3_get_invariants()
16506 tp->write32 = tg3_write32; in tg3_get_invariants()
16507 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16508 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16509 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16510 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16514 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16525 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16529 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16531 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16535 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16536 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16537 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16538 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16539 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16540 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16542 iounmap(tp->regs); in tg3_get_invariants()
16543 tp->regs = NULL; in tg3_get_invariants()
16545 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16547 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16550 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16551 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16552 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16553 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16556 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16570 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16574 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16575 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16577 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16587 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16589 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16594 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16595 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16611 tp->fw_needed = NULL; in tg3_get_invariants()
16621 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16625 tp->ape_hb_interval = in tg3_get_invariants()
16629 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16634 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16637 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16640 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16643 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16648 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16650 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16653 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16656 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16661 tp->grc_local_ctrl |= in tg3_get_invariants()
16670 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16684 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16691 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16692 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16693 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16697 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16699 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16702 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16710 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16711 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16712 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16713 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16714 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16716 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16721 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16722 if (tp->phy_otp == 0) in tg3_get_invariants()
16723 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16727 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16729 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16731 tp->coalesce_mode = 0; in tg3_get_invariants()
16734 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16741 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16742 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16765 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16775 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16789 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16805 tp->fw_needed = NULL; in tg3_get_invariants()
16819 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16822 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16823 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16824 tp->misc_host_ctrl); in tg3_get_invariants()
16829 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16831 tp->mac_mode = 0; in tg3_get_invariants()
16834 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16838 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16846 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16847 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16850 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16852 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16868 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16870 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16871 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16876 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16884 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16885 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16888 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16890 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16894 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16895 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16896 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16898 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16900 /* Increment the rx prod index on the rx std ring by at most in tg3_get_invariants()
16906 tp->rx_std_max_post = 8; in tg3_get_invariants()
16909 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16921 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
16925 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
16940 if (tp->pci_fn & 1) in tg3_get_device_address()
16942 if (tp->pci_fn > 1) in tg3_get_device_address()
16985 return -EINVAL; in tg3_get_device_address()
16998 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17031 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17034 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17035 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17165 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17184 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17186 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17188 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17195 ret = -ENODEV; in tg3_do_test_dma()
17227 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17230 ret = -ENOMEM; in tg3_test_dma()
17234 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17237 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17244 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17248 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17250 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17263 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17265 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17270 tp->dma_rwctrl |= in tg3_test_dma()
17276 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17279 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17281 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17285 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17289 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17294 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17304 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17306 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17309 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17319 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17320 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17321 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17332 dev_err(&tp->pdev->dev, in tg3_test_dma()
17341 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17351 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17353 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17354 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17355 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17358 dev_err(&tp->pdev->dev, in tg3_test_dma()
17361 ret = -ENODEV; in tg3_test_dma()
17372 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17379 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17380 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17383 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17386 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17390 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17398 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17400 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17402 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17405 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17407 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17409 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17412 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17414 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17416 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17419 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17421 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17425 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17427 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17429 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17432 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17434 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17436 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17439 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17441 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17443 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17447 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17448 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17453 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17513 strcat(str, ":32-bit"); in tg3_bus_string()
17515 strcat(str, ":64-bit"); in tg3_bus_string()
17521 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17524 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17525 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17526 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17527 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17528 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17529 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17530 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17531 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17532 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17533 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17535 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17537 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17538 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17539 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17540 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17544 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17545 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17546 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17564 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17570 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17578 err = -ENOMEM; in tg3_init_one()
17582 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17585 tp->pdev = pdev; in tg3_init_one()
17586 tp->dev = dev; in tg3_init_one()
17587 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17588 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17589 tp->irq_sync = 1; in tg3_init_one()
17590 tp->pcierr_recovery = false; in tg3_init_one()
17593 tp->msg_enable = tg3_debug; in tg3_init_one()
17595 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17615 tp->misc_host_ctrl = in tg3_init_one()
17621 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17624 * The StrongARM chips on the board (one for tx, one for rx) in tg3_init_one()
17625 * are running in big-endian mode. in tg3_init_one()
17627 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17630 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17632 spin_lock_init(&tp->lock); in tg3_init_one()
17633 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17634 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17636 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17637 if (!tp->regs) { in tg3_init_one()
17638 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17639 err = -ENOMEM; in tg3_init_one()
17643 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17644 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17645 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17646 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17655 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17659 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17660 if (!tp->aperegs) { in tg3_init_one()
17661 dev_err(&pdev->dev, in tg3_init_one()
17663 err = -ENOMEM; in tg3_init_one()
17668 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17669 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17671 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17672 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17673 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17674 dev->irq = pdev->irq; in tg3_init_one()
17678 dev_err(&pdev->dev, in tg3_init_one()
17684 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17685 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17686 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17701 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17704 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17707 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17714 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17716 dev_err(&pdev->dev, in tg3_init_one()
17755 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17757 dev->vlan_features |= features; in tg3_init_one()
17761 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17769 dev->hw_features |= features; in tg3_init_one()
17770 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17772 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17773 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17774 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17780 tp->rx_pending = 63; in tg3_init_one()
17785 dev_err(&pdev->dev, in tg3_init_one()
17794 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17795 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17797 tnapi->tp = tp; in tg3_init_one()
17798 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17800 tnapi->int_mbox = intmbx; in tg3_init_one()
17806 tnapi->consmbox = rcvmbx; in tg3_init_one()
17807 tnapi->prodmbox = sndmbx; in tg3_init_one()
17810 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17812 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17820 * remaining vectors handle rx and tx interrupts. Reuse the in tg3_init_one()
17830 sndmbx -= 0x4; in tg3_init_one()
17850 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17869 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
17875 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17876 &tp->pdev->dev); in tg3_init_one()
17877 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17878 tp->ptp_clock = NULL; in tg3_init_one()
17882 tp->board_part_number, in tg3_init_one()
17885 dev->dev_addr); in tg3_init_one()
17887 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17890 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17891 ethtype = "10/100Base-TX"; in tg3_init_one()
17892 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17893 ethtype = "1000Base-SX"; in tg3_init_one()
17895 ethtype = "10/100/1000Base-T"; in tg3_init_one()
17900 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17901 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17905 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
17907 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17910 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
17911 tp->dma_rwctrl, in tg3_init_one()
17912 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
17913 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
17920 if (tp->aperegs) { in tg3_init_one()
17921 iounmap(tp->aperegs); in tg3_init_one()
17922 tp->aperegs = NULL; in tg3_init_one()
17926 if (tp->regs) { in tg3_init_one()
17927 iounmap(tp->regs); in tg3_init_one()
17928 tp->regs = NULL; in tg3_init_one()
17952 release_firmware(tp->fw); in tg3_remove_one()
17962 if (tp->aperegs) { in tg3_remove_one()
17963 iounmap(tp->aperegs); in tg3_remove_one()
17964 tp->aperegs = NULL; in tg3_remove_one()
17966 if (tp->regs) { in tg3_remove_one()
17967 iounmap(tp->regs); in tg3_remove_one()
17968 tp->regs = NULL; in tg3_remove_one()
18052 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18096 * tg3_io_error_detected - called when PCI error is detected
18115 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18120 tp->pcierr_recovery = true; in tg3_io_error_detected()
18155 * tg3_io_slot_reset - called after the pci bus has been reset.
18158 * Restart the card from scratch, as if from a cold-boot.
18173 dev_err(&pdev->dev, in tg3_io_slot_reset()
18174 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18204 * tg3_io_resume - called when traffic can start flowing again.
18242 tp->pcierr_recovery = false; in tg3_io_resume()