Lines Matching +full:parallel +full:- +full:memories
3 * Copyright (c) 2007-2013 Broadcom Corporation
37 #include <linux/dma-mapping.h>
84 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
85 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
86 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
87 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
88 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
89 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
118 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
125 static int mrrs = -1;
380 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_wr_ind()
381 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); in bnx2x_reg_wr_ind()
382 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_wr_ind()
390 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_rd_ind()
391 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); in bnx2x_reg_rd_ind()
392 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_rd_ind()
407 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; in bnx2x_dp_dmae()
410 switch (dmae->opcode & DMAE_COMMAND_DST) { in bnx2x_dp_dmae()
416 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, in bnx2x_dp_dmae()
417 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, in bnx2x_dp_dmae()
418 dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
419 dmae->comp_val); in bnx2x_dp_dmae()
424 dmae->opcode, dmae->src_addr_lo >> 2, in bnx2x_dp_dmae()
425 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, in bnx2x_dp_dmae()
426 dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
427 dmae->comp_val); in bnx2x_dp_dmae()
434 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, in bnx2x_dp_dmae()
435 dmae->len, dmae->dst_addr_lo >> 2, in bnx2x_dp_dmae()
436 dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
437 dmae->comp_val); in bnx2x_dp_dmae()
442 dmae->opcode, dmae->src_addr_lo >> 2, in bnx2x_dp_dmae()
443 dmae->len, dmae->dst_addr_lo >> 2, in bnx2x_dp_dmae()
444 dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
445 dmae->comp_val); in bnx2x_dp_dmae()
452 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, in bnx2x_dp_dmae()
453 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
454 dmae->comp_val); in bnx2x_dp_dmae()
459 dmae->opcode, dmae->src_addr_lo >> 2, in bnx2x_dp_dmae()
460 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, in bnx2x_dp_dmae()
461 dmae->comp_val); in bnx2x_dp_dmae()
526 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, in bnx2x_prep_dmae_with_comp()
530 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
531 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
532 dmae->comp_val = DMAE_COMP_VAL; in bnx2x_prep_dmae_with_comp()
535 /* issue a dmae command over the init-channel and wait for completion */
544 /* Lock the dmae channel. Disable BHs to prevent a dead-lock in bnx2x_issue_dmae_with_comp()
549 spin_lock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
562 (bp->recovery_state != BNX2X_RECOVERY_DONE && in bnx2x_issue_dmae_with_comp()
563 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_issue_dmae_with_comp()
568 cnt--; in bnx2x_issue_dmae_with_comp()
578 spin_unlock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
589 if (!bp->dmae_ready) { in bnx2x_write_dmae()
624 if (!bp->dmae_ready) { in bnx2x_read_dmae()
668 len -= dmae_wr_max; in bnx2x_write_dmae_phys_len()
702 return -EINVAL; in bnx2x_get_assert_list_entry()
763 bp->fw_major, bp->fw_minor, bp->fw_rev); in bnx2x_mc_assert()
780 BNX2X_ERR("NO MCP - can not dump\n"); in bnx2x_fw_dump_lvl()
783 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", in bnx2x_fw_dump_lvl()
784 (bp->common.bc_ver & 0xff0000) >> 16, in bnx2x_fw_dump_lvl()
785 (bp->common.bc_ver & 0xff00) >> 8, in bnx2x_fw_dump_lvl()
786 (bp->common.bc_ver & 0xff)); in bnx2x_fw_dump_lvl()
788 if (pci_channel_offline(bp->pdev)) { in bnx2x_fw_dump_lvl()
798 trace_shmem_base = bp->common.shmem_base; in bnx2x_fw_dump_lvl()
811 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; in bnx2x_fw_dump_lvl()
823 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; in bnx2x_fw_dump_lvl()
907 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_disable()
926 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_panic_dump()
927 bp->eth_stats.unrecoverable_error++; in bnx2x_panic_dump()
928 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); in bnx2x_panic_dump()
930 BNX2X_ERR("begin crash dump -----------------\n"); in bnx2x_panic_dump()
935 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_panic_dump()
939 bp->def_idx, bp->def_att_idx, bp->attn_state, in bnx2x_panic_dump()
940 bp->spq_prod_idx, bp->stats_counter); in bnx2x_panic_dump()
942 def_sb->atten_status_block.attn_bits, in bnx2x_panic_dump()
943 def_sb->atten_status_block.attn_bits_ack, in bnx2x_panic_dump()
944 def_sb->atten_status_block.status_block_id, in bnx2x_panic_dump()
945 def_sb->atten_status_block.attn_bits_index); in bnx2x_panic_dump()
949 def_sb->sp_sb.index_values[i], in bnx2x_panic_dump()
950 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); in bnx2x_panic_dump()
971 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
987 if (!bp->fp) in bnx2x_panic_dump()
990 if (!fp->rx_cons_sb) in bnx2x_panic_dump()
995 i, fp->rx_bd_prod, fp->rx_bd_cons, in bnx2x_panic_dump()
996 fp->rx_comp_prod, in bnx2x_panic_dump()
997 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); in bnx2x_panic_dump()
999 fp->rx_sge_prod, fp->last_max_sge, in bnx2x_panic_dump()
1000 le16_to_cpu(fp->fp_hc_idx)); in bnx2x_panic_dump()
1005 if (!fp->txdata_ptr[cos]) in bnx2x_panic_dump()
1008 txdata = *fp->txdata_ptr[cos]; in bnx2x_panic_dump()
1031 fp->sb_running_index[j], in bnx2x_panic_dump()
1032 (j == HC_SB_MAX_SM - 1) ? ")" : " "); in bnx2x_panic_dump()
1037 fp->sb_index_values[j], in bnx2x_panic_dump()
1038 (j == loop - 1) ? ")" : " "); in bnx2x_panic_dump()
1055 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + in bnx2x_panic_dump()
1097 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); in bnx2x_panic_dump()
1099 u32 *data = (u32 *)&bp->eq_ring[i].message.data; in bnx2x_panic_dump()
1102 i, bp->eq_ring[i].message.opcode, in bnx2x_panic_dump()
1103 bp->eq_ring[i].message.error); in bnx2x_panic_dump()
1112 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1114 if (!bp->fp) in bnx2x_panic_dump()
1117 if (!fp->rx_cons_sb) in bnx2x_panic_dump()
1120 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); in bnx2x_panic_dump()
1121 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); in bnx2x_panic_dump()
1123 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; in bnx2x_panic_dump()
1124 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; in bnx2x_panic_dump()
1127 i, j, rx_bd[1], rx_bd[0], sw_bd->data); in bnx2x_panic_dump()
1130 start = RX_SGE(fp->rx_sge_prod); in bnx2x_panic_dump()
1131 end = RX_SGE(fp->last_max_sge); in bnx2x_panic_dump()
1133 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; in bnx2x_panic_dump()
1134 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; in bnx2x_panic_dump()
1137 i, j, rx_sge[1], rx_sge[0], sw_page->page); in bnx2x_panic_dump()
1140 start = RCQ_BD(fp->rx_comp_cons - 10); in bnx2x_panic_dump()
1141 end = RCQ_BD(fp->rx_comp_cons + 503); in bnx2x_panic_dump()
1143 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; in bnx2x_panic_dump()
1152 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1154 if (!bp->fp) in bnx2x_panic_dump()
1158 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; in bnx2x_panic_dump()
1160 if (!fp->txdata_ptr[cos]) in bnx2x_panic_dump()
1163 if (!txdata->tx_cons_sb) in bnx2x_panic_dump()
1166 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); in bnx2x_panic_dump()
1167 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); in bnx2x_panic_dump()
1170 &txdata->tx_buf_ring[j]; in bnx2x_panic_dump()
1173 i, cos, j, sw_bd->skb, in bnx2x_panic_dump()
1174 sw_bd->first_bd); in bnx2x_panic_dump()
1177 start = TX_BD(txdata->tx_bd_cons - 10); in bnx2x_panic_dump()
1178 end = TX_BD(txdata->tx_bd_cons + 254); in bnx2x_panic_dump()
1180 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; in bnx2x_panic_dump()
1190 int tmp_msg_en = bp->msg_enable; in bnx2x_panic_dump()
1193 bp->msg_enable |= NETIF_MSG_HW; in bnx2x_panic_dump()
1194 BNX2X_ERR("Idle check (1st round) ----------\n"); in bnx2x_panic_dump()
1196 BNX2X_ERR("Idle check (2nd round) ----------\n"); in bnx2x_panic_dump()
1198 bp->msg_enable = tmp_msg_en; in bnx2x_panic_dump()
1202 BNX2X_ERR("end crash dump -----------------\n"); in bnx2x_panic_dump()
1235 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1236 crd = crd_start = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1237 init_crd = REG_RD(bp, regs->init_crd); in bnx2x_pbf_pN_buf_flushed()
1239 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); in bnx2x_pbf_pN_buf_flushed()
1240 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); in bnx2x_pbf_pN_buf_flushed()
1241 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); in bnx2x_pbf_pN_buf_flushed()
1244 (init_crd - crd_start))) { in bnx2x_pbf_pN_buf_flushed()
1245 if (cur_cnt--) { in bnx2x_pbf_pN_buf_flushed()
1247 crd = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1248 crd_freed = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1251 regs->pN); in bnx2x_pbf_pN_buf_flushed()
1253 regs->pN, crd); in bnx2x_pbf_pN_buf_flushed()
1255 regs->pN, crd_freed); in bnx2x_pbf_pN_buf_flushed()
1260 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); in bnx2x_pbf_pN_buf_flushed()
1270 occup = to_free = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1271 freed = freed_start = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1273 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); in bnx2x_pbf_pN_cmd_flushed()
1274 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); in bnx2x_pbf_pN_cmd_flushed()
1277 if (cur_cnt--) { in bnx2x_pbf_pN_cmd_flushed()
1279 occup = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1280 freed = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1283 regs->pN); in bnx2x_pbf_pN_cmd_flushed()
1285 regs->pN, occup); in bnx2x_pbf_pN_cmd_flushed()
1287 regs->pN, freed); in bnx2x_pbf_pN_cmd_flushed()
1292 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); in bnx2x_pbf_pN_cmd_flushed()
1301 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) in bnx2x_flr_clnup_reg_poll()
1448 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ in bnx2x_poll_hw_usage_counters()
1455 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ in bnx2x_poll_hw_usage_counters()
1462 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ in bnx2x_poll_hw_usage_counters()
1469 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ in bnx2x_poll_hw_usage_counters()
1527 /* Re-enable PF target read access */ in bnx2x_pf_flr_clnup()
1533 return -EBUSY; in bnx2x_pf_flr_clnup()
1539 return -EBUSY; in bnx2x_pf_flr_clnup()
1550 if (bnx2x_is_pcie_pending(bp->pdev)) in bnx2x_pf_flr_clnup()
1557 * Master enable - Due to WB DMAE writes performed before this in bnx2x_pf_flr_clnup()
1558 * register is re-initialized as part of the regular function init in bnx2x_pf_flr_clnup()
1570 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1571 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1572 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_hc_int_enable()
1607 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); in bnx2x_hc_int_enable()
1619 if (bp->port.pmf) in bnx2x_hc_int_enable()
1633 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1634 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1635 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_igu_int_enable()
1659 /* Clean previous status - need to configure igu prior to ack*/ in bnx2x_igu_int_enable()
1668 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); in bnx2x_igu_int_enable()
1673 pci_intx(bp->pdev, true); in bnx2x_igu_int_enable()
1680 if (bp->port.pmf) in bnx2x_igu_int_enable()
1692 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_enable()
1700 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_int_disable_sync()
1709 synchronize_irq(bp->msix_table[0].vector); in bnx2x_int_disable_sync()
1714 synchronize_irq(bp->msix_table[offset++].vector); in bnx2x_int_disable_sync()
1716 synchronize_irq(bp->pdev->irq); in bnx2x_int_disable_sync()
1719 cancel_delayed_work(&bp->sp_task); in bnx2x_int_disable_sync()
1720 cancel_delayed_work(&bp->period_task); in bnx2x_int_disable_sync()
1753 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); in bnx2x_trylock_hw_lock()
1767 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1783 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1799 /* Set the interrupt occurred bit for the sp-task to recognize it in bnx2x_schedule_sp_task()
1803 atomic_set(&bp->interrupt_occurred, 1); in bnx2x_schedule_sp_task()
1812 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); in bnx2x_schedule_sp_task()
1817 struct bnx2x *bp = fp->bp; in bnx2x_sp_event()
1818 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); in bnx2x_sp_event()
1819 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); in bnx2x_sp_event()
1825 fp->index, cid, command, bp->state, in bnx2x_sp_event()
1826 rr_cqe->ramrod_cqe.ramrod_type); in bnx2x_sp_event()
1847 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); in bnx2x_sp_event()
1873 command, fp->index); in bnx2x_sp_event()
1878 q_obj->complete_cmd(bp, q_obj, drv_cmd)) in bnx2x_sp_event()
1879 /* q_obj->complete_cmd() failure means that this was in bnx2x_sp_event()
1882 * In this case we don't want to increase the bp->spq_left in bnx2x_sp_event()
1893 atomic_inc(&bp->cq_spq_left); in bnx2x_sp_event()
1894 /* push the change in bp->spq_left and towards the memory */ in bnx2x_sp_event()
1897 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); in bnx2x_sp_event()
1900 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { in bnx2x_sp_event()
1911 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); in bnx2x_sp_event()
1913 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_sp_event()
1939 if (unlikely(bp->panic)) in bnx2x_interrupt()
1944 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_interrupt()
1946 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); in bnx2x_interrupt()
1950 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); in bnx2x_interrupt()
1951 prefetch(&fp->sb_running_index[SM_RX_ID]); in bnx2x_interrupt()
1952 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); in bnx2x_interrupt()
1963 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_interrupt()
1964 if (c_ops && (bp->cnic_eth_dev.drv_state & in bnx2x_interrupt()
1966 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_interrupt()
2010 return -EINVAL; in bnx2x_acquire_hw_lock()
2017 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); in bnx2x_acquire_hw_lock()
2025 return -EEXIST; in bnx2x_acquire_hw_lock()
2039 return -EAGAIN; in bnx2x_acquire_hw_lock()
2058 return -EINVAL; in bnx2x_release_hw_lock()
2065 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); in bnx2x_release_hw_lock()
2073 return -EFAULT; in bnx2x_release_hw_lock()
2093 return -EINVAL; in bnx2x_get_gpio()
2120 return -EINVAL; in bnx2x_set_gpio()
2130 "Set GPIO %d (shift %d) -> output low\n", in bnx2x_set_gpio()
2139 "Set GPIO %d (shift %d) -> output high\n", in bnx2x_set_gpio()
2148 "Set GPIO %d (shift %d) -> input\n", in bnx2x_set_gpio()
2180 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); in bnx2x_set_mult_gpio()
2186 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); in bnx2x_set_mult_gpio()
2192 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); in bnx2x_set_mult_gpio()
2199 rc = -EINVAL; in bnx2x_set_mult_gpio()
2223 return -EINVAL; in bnx2x_set_gpio_int()
2233 "Clear GPIO INT %d (shift %d) -> output low\n", in bnx2x_set_gpio_int()
2242 "Set GPIO INT %d (shift %d) -> output high\n", in bnx2x_set_gpio_int()
2266 return -EINVAL; in bnx2x_set_spio()
2275 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); in bnx2x_set_spio()
2282 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); in bnx2x_set_spio()
2289 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); in bnx2x_set_spio()
2308 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2310 switch (bp->link_vars.ieee_fc & in bnx2x_calc_fc_adv()
2313 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2318 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; in bnx2x_calc_fc_adv()
2332 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) in bnx2x_set_requested_fc()
2333 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; in bnx2x_set_requested_fc()
2335 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; in bnx2x_set_requested_fc()
2342 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { in bnx2x_init_dropless_fc()
2343 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_init_dropless_fc()
2358 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; in bnx2x_initial_phy_init()
2365 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2366 lp->loopback_mode = LOOPBACK_XGXS; in bnx2x_initial_phy_init()
2368 if (lp->req_line_speed[cfx_idx] < SPEED_20000) { in bnx2x_initial_phy_init()
2369 if (lp->speed_cap_mask[cfx_idx] & in bnx2x_initial_phy_init()
2371 lp->req_line_speed[cfx_idx] = in bnx2x_initial_phy_init()
2373 else if (lp->speed_cap_mask[cfx_idx] & in bnx2x_initial_phy_init()
2375 lp->req_line_speed[cfx_idx] = in bnx2x_initial_phy_init()
2378 lp->req_line_speed[cfx_idx] = in bnx2x_initial_phy_init()
2384 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2385 lp->loopback_mode = LOOPBACK_EXT; in bnx2x_initial_phy_init()
2388 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_initial_phy_init()
2396 if (bp->link_vars.link_up) { in bnx2x_initial_phy_init()
2400 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_initial_phy_init()
2401 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; in bnx2x_initial_phy_init()
2404 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); in bnx2x_initial_phy_init()
2405 return -EINVAL; in bnx2x_initial_phy_init()
2412 bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_link_set()
2419 BNX2X_ERR("Bootcode is missing - can not set link\n"); in bnx2x_link_set()
2426 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); in bnx2x__link_reset()
2429 BNX2X_ERR("Bootcode is missing - can not reset link\n"); in bnx2x__link_reset()
2435 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); in bnx2x_force_link_reset()
2445 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, in bnx2x_link_test()
2449 BNX2X_ERR("Bootcode is missing - can not test link\n"); in bnx2x_link_test()
2459 0 - if all the min_rates are 0.
2470 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_min()
2477 /* If min rate is zero - set it to 1 */ in bnx2x_calc_vn_min()
2483 input->vnic_min_rate[vn] = vn_min_rate; in bnx2x_calc_vn_min()
2486 /* if ETS or all min rates are zeros - disable fairness */ in bnx2x_calc_vn_min()
2488 input->flags.cmng_enables &= in bnx2x_calc_vn_min()
2492 input->flags.cmng_enables &= in bnx2x_calc_vn_min()
2497 input->flags.cmng_enables |= in bnx2x_calc_vn_min()
2505 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_max()
2514 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; in bnx2x_calc_vn_max()
2522 input->vnic_max_rate[vn] = vn_max_rate; in bnx2x_calc_vn_max()
2559 bp->mf_config[vn] = in bnx2x_read_mf_cfg()
2562 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_read_mf_cfg()
2564 bp->flags |= MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2567 bp->flags &= ~MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2576 input.port_rate = bp->link_vars.line_speed; in bnx2x_cmng_fns_init()
2588 /* calculate and set min-max rate for each vn */ in bnx2x_cmng_fns_init()
2589 if (bp->port.pmf) in bnx2x_cmng_fns_init()
2597 bnx2x_init_cmng(&input, &bp->cmng); in bnx2x_cmng_fns_init()
2616 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); in storm_memset_cmng()
2625 (u32 *)&cmng->vnic.vnic_max_rate[vn]); in storm_memset_cmng()
2631 (u32 *)&cmng->vnic.vnic_min_rate[vn]); in storm_memset_cmng()
2642 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_set_local_cmng()
2656 bnx2x_link_update(&bp->link_params, &bp->link_vars); in bnx2x_link_attn()
2660 if (bp->link_vars.link_up) { in bnx2x_link_attn()
2662 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { in bnx2x_link_attn()
2667 memset(&(pstats->mac_stx[0]), 0, in bnx2x_link_attn()
2670 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_link_attn()
2674 if (bp->link_vars.link_up && bp->link_vars.line_speed) in bnx2x_link_attn()
2685 if (bp->state != BNX2X_STATE_OPEN) in bnx2x__link_status_update()
2691 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); in bnx2x__link_status_update()
2692 if (bp->link_vars.link_up) in bnx2x__link_status_update()
2700 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | in bnx2x__link_status_update()
2712 bp->port.advertising[0] = bp->port.supported[0]; in bnx2x__link_status_update()
2714 bp->link_params.bp = bp; in bnx2x__link_status_update()
2715 bp->link_params.port = BP_PORT(bp); in bnx2x__link_status_update()
2716 bp->link_params.req_duplex[0] = DUPLEX_FULL; in bnx2x__link_status_update()
2717 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2718 bp->link_params.req_line_speed[0] = SPEED_10000; in bnx2x__link_status_update()
2719 bp->link_params.speed_cap_mask[0] = 0x7f0000; in bnx2x__link_status_update()
2720 bp->link_params.switch_cfg = SWITCH_CFG_10G; in bnx2x__link_status_update()
2721 bp->link_vars.mac_type = MAC_TYPE_BMAC; in bnx2x__link_status_update()
2722 bp->link_vars.line_speed = SPEED_10000; in bnx2x__link_status_update()
2723 bp->link_vars.link_status = in bnx2x__link_status_update()
2726 bp->link_vars.link_up = 1; in bnx2x__link_status_update()
2727 bp->link_vars.duplex = DUPLEX_FULL; in bnx2x__link_status_update()
2728 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2749 func_params.f_obj = &bp->func_obj; in bnx2x_afex_func_update()
2756 f_update_params->vif_id = vifid; in bnx2x_afex_func_update()
2757 f_update_params->afex_default_vlan = vlan_val; in bnx2x_afex_func_update()
2758 f_update_params->allowed_priorities = allowed_prio; in bnx2x_afex_func_update()
2781 func_params.f_obj = &bp->func_obj; in bnx2x_afex_handle_vif_list_cmd()
2785 update_params->afex_vif_list_command = cmd_type; in bnx2x_afex_handle_vif_list_cmd()
2786 update_params->vif_list_index = vif_index; in bnx2x_afex_handle_vif_list_cmd()
2787 update_params->func_bit_map = in bnx2x_afex_handle_vif_list_cmd()
2789 update_params->func_to_clear = 0; in bnx2x_afex_handle_vif_list_cmd()
2857 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2871 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2911 bp->afex_def_vlan_tag = vlan_val; in bnx2x_handle_afex_cmd()
2912 bp->afex_vlan_mode = vlan_mode; in bnx2x_handle_afex_cmd()
2914 /* notify link down because BP->flags is disabled */ in bnx2x_handle_afex_cmd()
2921 bp->afex_def_vlan_tag = -1; in bnx2x_handle_afex_cmd()
2933 func_params.f_obj = &bp->func_obj; in bnx2x_handle_update_svid_cmd()
2944 /* Re-learn the S-tag from shmem */ in bnx2x_handle_update_svid_cmd()
2948 bp->mf_ov = val; in bnx2x_handle_update_svid_cmd()
2954 /* Configure new S-tag in LLH */ in bnx2x_handle_update_svid_cmd()
2956 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2960 &switch_update_params->changes); in bnx2x_handle_update_svid_cmd()
2961 switch_update_params->vlan = bp->mf_ov; in bnx2x_handle_update_svid_cmd()
2964 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", in bnx2x_handle_update_svid_cmd()
2965 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2968 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", in bnx2x_handle_update_svid_cmd()
2969 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2986 bp->port.pmf = 1; in bnx2x_pmf_update()
2987 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); in bnx2x_pmf_update()
2991 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). in bnx2x_pmf_update()
2996 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_pmf_update()
3002 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_pmf_update()
3030 mutex_lock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3031 seq = ++bp->fw_seq; in bnx2x_fw_command()
3059 mutex_unlock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3081 storm_memset_func_cfg(bp, &tcfg, p->func_id); in bnx2x_func_init()
3085 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); in bnx2x_func_init()
3086 storm_memset_func_en(bp, p->func_id, 1); in bnx2x_func_init()
3089 if (p->spq_active) { in bnx2x_func_init()
3090 storm_memset_spq_addr(bp, p->spq_map, p->func_id); in bnx2x_func_init()
3092 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); in bnx2x_func_init()
3097 * bnx2x_get_common_flags - Return common flags
3103 * Return the flags that are common for the Tx-only and not normal connections.
3123 if (bp->flags & TX_SWITCHING) in bnx2x_get_common_flags()
3148 /* For FCoE - force usage of default priority (for afex) */ in bnx2x_get_q_flags()
3152 if (fp->mode != TPA_MODE_DISABLED) { in bnx2x_get_q_flags()
3155 if (fp->mode == TPA_MODE_GRO) in bnx2x_get_q_flags()
3178 gen_init->stat_id = bnx2x_stats_id(fp); in bnx2x_pf_q_prep_general()
3179 gen_init->spcl_id = fp->cl_id; in bnx2x_pf_q_prep_general()
3181 /* Always use mini-jumbo MTU for FCoE L2 ring */ in bnx2x_pf_q_prep_general()
3183 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; in bnx2x_pf_q_prep_general()
3185 gen_init->mtu = bp->dev->mtu; in bnx2x_pf_q_prep_general()
3187 gen_init->cos = cos; in bnx2x_pf_q_prep_general()
3189 gen_init->fp_hsi = ETH_FP_HSI_VERSION; in bnx2x_pf_q_prep_general()
3200 if (fp->mode != TPA_MODE_DISABLED) { in bnx2x_pf_rx_q_prep()
3201 pause->sge_th_lo = SGE_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3202 pause->sge_th_hi = SGE_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3205 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3206 pause->sge_th_hi + FW_PREFETCH_CNT > in bnx2x_pf_rx_q_prep()
3210 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> in bnx2x_pf_rx_q_prep()
3212 max_sge = ((max_sge + PAGES_PER_SGE - 1) & in bnx2x_pf_rx_q_prep()
3213 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; in bnx2x_pf_rx_q_prep()
3217 /* pause - not for e1 */ in bnx2x_pf_rx_q_prep()
3219 pause->bd_th_lo = BD_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3220 pause->bd_th_hi = BD_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3222 pause->rcq_th_lo = RCQ_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3223 pause->rcq_th_hi = RCQ_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3228 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3229 pause->bd_th_hi + FW_PREFETCH_CNT > in bnx2x_pf_rx_q_prep()
3230 bp->rx_ring_size); in bnx2x_pf_rx_q_prep()
3231 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3232 pause->rcq_th_hi + FW_PREFETCH_CNT > in bnx2x_pf_rx_q_prep()
3235 pause->pri_map = 1; in bnx2x_pf_rx_q_prep()
3239 rxq_init->dscr_map = fp->rx_desc_mapping; in bnx2x_pf_rx_q_prep()
3240 rxq_init->sge_map = fp->rx_sge_mapping; in bnx2x_pf_rx_q_prep()
3241 rxq_init->rcq_map = fp->rx_comp_mapping; in bnx2x_pf_rx_q_prep()
3242 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; in bnx2x_pf_rx_q_prep()
3247 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - in bnx2x_pf_rx_q_prep()
3248 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; in bnx2x_pf_rx_q_prep()
3250 rxq_init->cl_qzone_id = fp->cl_qzone_id; in bnx2x_pf_rx_q_prep()
3251 rxq_init->tpa_agg_sz = tpa_agg_size; in bnx2x_pf_rx_q_prep()
3252 rxq_init->sge_buf_sz = sge_sz; in bnx2x_pf_rx_q_prep()
3253 rxq_init->max_sges_pkt = max_sge; in bnx2x_pf_rx_q_prep()
3254 rxq_init->rss_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3255 rxq_init->mcast_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3262 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); in bnx2x_pf_rx_q_prep()
3264 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; in bnx2x_pf_rx_q_prep()
3265 rxq_init->fw_sb_id = fp->fw_sb_id; in bnx2x_pf_rx_q_prep()
3268 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; in bnx2x_pf_rx_q_prep()
3270 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; in bnx2x_pf_rx_q_prep()
3275 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; in bnx2x_pf_rx_q_prep()
3276 rxq_init->silent_removal_mask = VLAN_VID_MASK; in bnx2x_pf_rx_q_prep()
3284 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; in bnx2x_pf_tx_q_prep()
3285 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; in bnx2x_pf_tx_q_prep()
3286 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; in bnx2x_pf_tx_q_prep()
3287 txq_init->fw_sb_id = fp->fw_sb_id; in bnx2x_pf_tx_q_prep()
3293 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); in bnx2x_pf_tx_q_prep()
3296 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; in bnx2x_pf_tx_q_prep()
3297 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; in bnx2x_pf_tx_q_prep()
3324 func_init.spq_map = bp->spq_mapping; in bnx2x_pf_init()
3325 func_init.spq_prod = bp->spq_prod_idx; in bnx2x_pf_init()
3329 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); in bnx2x_pf_init()
3335 * re-calculated according to the actual link rate. in bnx2x_pf_init()
3337 bp->link_vars.line_speed = SPEED_10000; in bnx2x_pf_init()
3341 if (bp->port.pmf) in bnx2x_pf_init()
3342 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_pf_init()
3344 /* init Event Queue - PCI bus guarantees correct endianity*/ in bnx2x_pf_init()
3345 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); in bnx2x_pf_init()
3346 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); in bnx2x_pf_init()
3347 eq_data.producer = bp->eq_prod; in bnx2x_pf_init()
3369 /* Tx queue should be only re-enabled */ in bnx2x_e1h_enable()
3370 netif_tx_wake_all_queues(bp->dev); in bnx2x_e1h_enable()
3383 &bp->slowpath->drv_info_to_mcp.ether_stat; in bnx2x_drv_info_ether_stat()
3385 &bp->sp_objs->mac_obj; in bnx2x_drv_info_ether_stat()
3388 strscpy(ether_stat->version, DRV_MODULE_VERSION, in bnx2x_drv_info_ether_stat()
3400 memset(ether_stat->mac_local + i, 0, in bnx2x_drv_info_ether_stat()
3401 sizeof(ether_stat->mac_local[0])); in bnx2x_drv_info_ether_stat()
3402 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, in bnx2x_drv_info_ether_stat()
3404 ether_stat->mac_local + MAC_PAD, MAC_PAD, in bnx2x_drv_info_ether_stat()
3406 ether_stat->mtu_size = bp->dev->mtu; in bnx2x_drv_info_ether_stat()
3407 if (bp->dev->features & NETIF_F_RXCSUM) in bnx2x_drv_info_ether_stat()
3408 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; in bnx2x_drv_info_ether_stat()
3409 if (bp->dev->features & NETIF_F_TSO) in bnx2x_drv_info_ether_stat()
3410 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; in bnx2x_drv_info_ether_stat()
3411 ether_stat->feature_flags |= bp->common.boot_mode; in bnx2x_drv_info_ether_stat()
3413 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; in bnx2x_drv_info_ether_stat()
3415 ether_stat->txq_size = bp->tx_ring_size; in bnx2x_drv_info_ether_stat()
3416 ether_stat->rxq_size = bp->rx_ring_size; in bnx2x_drv_info_ether_stat()
3419 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; in bnx2x_drv_info_ether_stat()
3425 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_fcoe_stat()
3427 &bp->slowpath->drv_info_to_mcp.fcoe_stat; in bnx2x_drv_info_fcoe_stat()
3432 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); in bnx2x_drv_info_fcoe_stat()
3434 fcoe_stat->qos_priority = in bnx2x_drv_info_fcoe_stat()
3435 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; in bnx2x_drv_info_fcoe_stat()
3440 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3444 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3448 &bp->fw_stats_data->fcoe; in bnx2x_drv_info_fcoe_stat()
3450 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3451 fcoe_stat->rx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3452 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); in bnx2x_drv_info_fcoe_stat()
3454 ADD_64_LE(fcoe_stat->rx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3455 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, in bnx2x_drv_info_fcoe_stat()
3456 fcoe_stat->rx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3457 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); in bnx2x_drv_info_fcoe_stat()
3459 ADD_64_LE(fcoe_stat->rx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3460 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, in bnx2x_drv_info_fcoe_stat()
3461 fcoe_stat->rx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3462 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); in bnx2x_drv_info_fcoe_stat()
3464 ADD_64_LE(fcoe_stat->rx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3465 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, in bnx2x_drv_info_fcoe_stat()
3466 fcoe_stat->rx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3467 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); in bnx2x_drv_info_fcoe_stat()
3469 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3470 fcoe_stat->rx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3471 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); in bnx2x_drv_info_fcoe_stat()
3473 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3474 fcoe_stat->rx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3475 fcoe_q_tstorm_stats->rcv_ucast_pkts); in bnx2x_drv_info_fcoe_stat()
3477 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3478 fcoe_stat->rx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3479 fcoe_q_tstorm_stats->rcv_bcast_pkts); in bnx2x_drv_info_fcoe_stat()
3481 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3482 fcoe_stat->rx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3483 fcoe_q_tstorm_stats->rcv_mcast_pkts); in bnx2x_drv_info_fcoe_stat()
3485 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3486 fcoe_stat->tx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3487 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); in bnx2x_drv_info_fcoe_stat()
3489 ADD_64_LE(fcoe_stat->tx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3490 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, in bnx2x_drv_info_fcoe_stat()
3491 fcoe_stat->tx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3492 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); in bnx2x_drv_info_fcoe_stat()
3494 ADD_64_LE(fcoe_stat->tx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3495 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, in bnx2x_drv_info_fcoe_stat()
3496 fcoe_stat->tx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3497 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); in bnx2x_drv_info_fcoe_stat()
3499 ADD_64_LE(fcoe_stat->tx_bytes_hi, in bnx2x_drv_info_fcoe_stat()
3500 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, in bnx2x_drv_info_fcoe_stat()
3501 fcoe_stat->tx_bytes_lo, in bnx2x_drv_info_fcoe_stat()
3502 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); in bnx2x_drv_info_fcoe_stat()
3504 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3505 fcoe_stat->tx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3506 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); in bnx2x_drv_info_fcoe_stat()
3508 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3509 fcoe_stat->tx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3510 fcoe_q_xstorm_stats->ucast_pkts_sent); in bnx2x_drv_info_fcoe_stat()
3512 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3513 fcoe_stat->tx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3514 fcoe_q_xstorm_stats->bcast_pkts_sent); in bnx2x_drv_info_fcoe_stat()
3516 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, in bnx2x_drv_info_fcoe_stat()
3517 fcoe_stat->tx_frames_lo, in bnx2x_drv_info_fcoe_stat()
3518 fcoe_q_xstorm_stats->mcast_pkts_sent); in bnx2x_drv_info_fcoe_stat()
3527 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_iscsi_stat()
3529 &bp->slowpath->drv_info_to_mcp.iscsi_stat; in bnx2x_drv_info_iscsi_stat()
3534 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, in bnx2x_drv_info_iscsi_stat()
3537 iscsi_stat->qos_priority = in bnx2x_drv_info_iscsi_stat()
3538 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; in bnx2x_drv_info_iscsi_stat()
3561 if (bp->link_vars.link_up) { in bnx2x_config_mf_bw()
3565 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_config_mf_bw()
3576 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); in bnx2x_handle_eee_event()
3590 /* if drv_info version supported by MFW doesn't match - send NACK */ in bnx2x_handle_drv_info_req()
3600 mutex_lock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3602 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_handle_drv_info_req()
3616 /* if op code isn't supported - send NACK */ in bnx2x_handle_drv_info_req()
3637 } else if (!bp->drv_info_mng_owner) { in bnx2x_handle_drv_info_req()
3656 bp->drv_info_mng_owner = true; in bnx2x_handle_drv_info_req()
3660 mutex_unlock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3672 vals[0] -= '0'; in bnx2x_update_mng_version_utility()
3695 mutex_lock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3697 if (bp->drv_info_mng_owner) in bnx2x_update_mng_version()
3700 if (bp->state != BNX2X_STATE_OPEN) in bnx2x_update_mng_version()
3709 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3712 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; in bnx2x_update_mng_version()
3715 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3718 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; in bnx2x_update_mng_version()
3726 mutex_unlock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3748 /* Check & notify On-Chip dump. */ in bnx2x_update_mfw_dump()
3752 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); in bnx2x_update_mfw_dump()
3755 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); in bnx2x_update_mfw_dump()
3782 * where the bp->flags can change so it is done without any in bnx2x_oem_event()
3785 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_oem_event()
3787 bp->flags |= MF_FUNC_DIS; in bnx2x_oem_event()
3792 bp->flags &= ~MF_FUNC_DIS; in bnx2x_oem_event()
3817 struct eth_spe *next_spe = bp->spq_prod_bd; in bnx2x_sp_get_next()
3819 if (bp->spq_prod_bd == bp->spq_last_bd) { in bnx2x_sp_get_next()
3820 bp->spq_prod_bd = bp->spq; in bnx2x_sp_get_next()
3821 bp->spq_prod_idx = 0; in bnx2x_sp_get_next()
3824 bp->spq_prod_bd++; in bnx2x_sp_get_next()
3825 bp->spq_prod_idx++; in bnx2x_sp_get_next()
3843 bp->spq_prod_idx); in bnx2x_sp_prod_update()
3847 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3867 * bnx2x_sp_post - place a single command on an SP ring
3888 if (unlikely(bp->panic)) { in bnx2x_sp_post()
3890 return -EIO; in bnx2x_sp_post()
3894 spin_lock_bh(&bp->spq_lock); in bnx2x_sp_post()
3897 if (!atomic_read(&bp->eq_spq_left)) { in bnx2x_sp_post()
3899 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3901 return -EBUSY; in bnx2x_sp_post()
3903 } else if (!atomic_read(&bp->cq_spq_left)) { in bnx2x_sp_post()
3905 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3907 return -EBUSY; in bnx2x_sp_post()
3913 spe->hdr.conn_and_cmd_data = in bnx2x_sp_post()
3917 /* In some cases, type may already contain the func-id in bnx2x_sp_post()
3930 spe->hdr.type = cpu_to_le16(type); in bnx2x_sp_post()
3932 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); in bnx2x_sp_post()
3933 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); in bnx2x_sp_post()
3941 atomic_dec(&bp->eq_spq_left); in bnx2x_sp_post()
3943 atomic_dec(&bp->cq_spq_left); in bnx2x_sp_post()
3947 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), in bnx2x_sp_post()
3948 (u32)(U64_LO(bp->spq_mapping) + in bnx2x_sp_post()
3949 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, in bnx2x_sp_post()
3951 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); in bnx2x_sp_post()
3954 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3975 rc = -EBUSY; in bnx2x_acquire_alr()
3992 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_update_dsb_idx()
3996 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { in bnx2x_update_dsb_idx()
3997 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; in bnx2x_update_dsb_idx()
4001 if (bp->def_idx != def_sb->sp_sb.running_index) { in bnx2x_update_dsb_idx()
4002 bp->def_idx = def_sb->sp_sb.running_index; in bnx2x_update_dsb_idx()
4026 if (bp->attn_state & asserted) in bnx2x_attn_int_asserted()
4040 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4041 bp->attn_state |= asserted; in bnx2x_attn_int_asserted()
4042 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4105 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_asserted()
4112 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_asserted()
4118 * NIG mask. This loop should exit after 2-3 iterations max. in bnx2x_attn_int_asserted()
4120 if (bp->common.int_block != INT_BLOCK_HC) { in bnx2x_attn_int_asserted()
4152 …netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card … in bnx2x_fan_failure()
4180 bnx2x_hw_reset_phy(&bp->link_params); in bnx2x_attn_int_deasserted0()
4184 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { in bnx2x_attn_int_deasserted0()
4186 bnx2x_handle_module_detect_int(&bp->link_params); in bnx2x_attn_int_deasserted0()
4248 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); in bnx2x_attn_int_deasserted2()
4255 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); in bnx2x_attn_int_deasserted2()
4288 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, in bnx2x_attn_int_deasserted3()
4309 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bnx2x_attn_int_deasserted3()
4312 if (bp->port.pmf && in bnx2x_attn_int_deasserted3()
4314 bp->dcbx_enabled > 0) in bnx2x_attn_int_deasserted3()
4328 if (bp->link_vars.periodic_flags & in bnx2x_attn_int_deasserted3()
4332 bp->link_vars.periodic_flags &= in bnx2x_attn_int_deasserted3()
4368 BNX2X_ERR("GRC time-out 0x%08x\n", val); in bnx2x_attn_int_deasserted3()
4381 * 0-7 - Engine0 load counter.
4382 * 8-15 - Engine1 load counter.
4383 * 16 - Engine0 RESET_IN_PROGRESS bit.
4384 * 17 - Engine1 RESET_IN_PROGRESS bit.
4385 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4387 * 19 - Engine1 ONE_IS_LOADED.
4388 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4519 val1 |= (1 << bp->pf_num); in bnx2x_set_pf_load()
4532 * bnx2x_clear_pf_load - clear pf load mark
4556 val1 &= ~(1 << bp->pf_num); in bnx2x_clear_pf_load()
4994 netdev_err(bp->dev, in bnx2x_parity_attn()
5019 * bnx2x_chk_parity_attn - checks for parity attentions.
5128 bp->recovery_state = BNX2X_RECOVERY_INIT; in bnx2x_attn_int_deasserted()
5129 schedule_delayed_work(&bp->sp_rtnl_task, 0); in bnx2x_attn_int_deasserted()
5157 group_mask = &bp->attn_group[index]; in bnx2x_attn_int_deasserted()
5161 group_mask->sig[0], group_mask->sig[1], in bnx2x_attn_int_deasserted()
5162 group_mask->sig[2], group_mask->sig[3], in bnx2x_attn_int_deasserted()
5163 group_mask->sig[4]); in bnx2x_attn_int_deasserted()
5166 attn.sig[4] & group_mask->sig[4]); in bnx2x_attn_int_deasserted()
5168 attn.sig[3] & group_mask->sig[3]); in bnx2x_attn_int_deasserted()
5170 attn.sig[1] & group_mask->sig[1]); in bnx2x_attn_int_deasserted()
5172 attn.sig[2] & group_mask->sig[2]); in bnx2x_attn_int_deasserted()
5174 attn.sig[0] & group_mask->sig[0]); in bnx2x_attn_int_deasserted()
5180 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_deasserted()
5188 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_deasserted()
5191 if (~bp->attn_state & deasserted) in bnx2x_attn_int_deasserted()
5208 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5209 bp->attn_state &= ~deasserted; in bnx2x_attn_int_deasserted()
5210 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5216 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5218 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5220 u32 attn_state = bp->attn_state; in bnx2x_attn_int()
5244 u32 igu_addr = bp->igu_base_addr; in bnx2x_igu_ack_sb()
5259 u8 err = elem->message.error; in bnx2x_cnic_handle_cfc_del()
5261 if (!bp->cnic_eth_dev.starting_cid || in bnx2x_cnic_handle_cfc_del()
5262 (cid < bp->cnic_eth_dev.starting_cid && in bnx2x_cnic_handle_cfc_del()
5263 cid != bp->cnic_eth_dev.iscsi_l2_cid)) in bnx2x_cnic_handle_cfc_del()
5285 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_handle_mcast_eqe()
5287 netif_addr_lock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5290 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); in bnx2x_handle_mcast_eqe()
5292 /* If there are pending mcast commands - send them */ in bnx2x_handle_mcast_eqe()
5293 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { in bnx2x_handle_mcast_eqe()
5300 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5308 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); in bnx2x_handle_classification_eqe()
5319 vlan_mac_obj = &bp->iscsi_l2_mac_obj; in bnx2x_handle_classification_eqe()
5321 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; in bnx2x_handle_classification_eqe()
5326 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; in bnx2x_handle_classification_eqe()
5340 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); in bnx2x_handle_classification_eqe()
5352 netif_addr_lock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5354 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_handle_rx_mode_eqe()
5357 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5360 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5363 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5366 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5372 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { in bnx2x_after_afex_vif_lists()
5375 elem->message.data.vif_list_event.func_bit_map); in bnx2x_after_afex_vif_lists()
5377 elem->message.data.vif_list_event.func_bit_map); in bnx2x_after_afex_vif_lists()
5378 } else if (elem->message.data.vif_list_event.echo == in bnx2x_after_afex_vif_lists()
5399 &q_update_params->update_flags); in bnx2x_after_function_update()
5401 &q_update_params->update_flags); in bnx2x_after_function_update()
5405 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { in bnx2x_after_function_update()
5406 q_update_params->silent_removal_value = 0; in bnx2x_after_function_update()
5407 q_update_params->silent_removal_mask = 0; in bnx2x_after_function_update()
5409 q_update_params->silent_removal_value = in bnx2x_after_function_update()
5410 (bp->afex_def_vlan_tag & VLAN_VID_MASK); in bnx2x_after_function_update()
5411 q_update_params->silent_removal_mask = VLAN_VID_MASK; in bnx2x_after_function_update()
5416 fp = &bp->fp[q]; in bnx2x_after_function_update()
5427 fp = &bp->fp[FCOE_IDX(bp)]; in bnx2x_after_function_update()
5435 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_after_function_update()
5444 /* If no FCoE ring - ACK MCP now */ in bnx2x_after_function_update()
5458 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; in bnx2x_cid_to_q_obj()
5470 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; in bnx2x_eq_int()
5471 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; in bnx2x_eq_int()
5473 hw_cons = le16_to_cpu(*bp->eq_cons_sb); in bnx2x_eq_int()
5475 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. in bnx2x_eq_int()
5476 * when we get the next-page we need to adjust so the loop in bnx2x_eq_int()
5483 /* This function may never run in parallel with itself for a in bnx2x_eq_int()
5487 sw_cons = bp->eq_cons; in bnx2x_eq_int()
5488 sw_prod = bp->eq_prod; in bnx2x_eq_int()
5490 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", in bnx2x_eq_int()
5491 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); in bnx2x_eq_int()
5496 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; in bnx2x_eq_int()
5505 opcode = elem->message.opcode; in bnx2x_eq_int()
5511 &elem->message.data.vf_pf_event); in bnx2x_eq_int()
5517 bp->stats_comp++); in bnx2x_eq_int()
5529 cid = SW_CID(elem->message.data.cfc_del_event.cid); in bnx2x_eq_int()
5540 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) in bnx2x_eq_int()
5548 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5556 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5562 echo = elem->message.data.function_update_event.echo; in bnx2x_eq_int()
5566 if (f_obj->complete_cmd( in bnx2x_eq_int()
5575 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5588 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5595 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) in bnx2x_eq_int()
5603 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) in bnx2x_eq_int()
5611 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5617 switch (opcode | bp->state) { in bnx2x_eq_int()
5625 SW_CID(elem->message.data.eth_event.echo)); in bnx2x_eq_int()
5626 rss_raw->clear_pending(rss_raw); in bnx2x_eq_int()
5664 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", in bnx2x_eq_int()
5665 elem->message.opcode, bp->state); in bnx2x_eq_int()
5672 atomic_add(spqe_cnt, &bp->eq_spq_left); in bnx2x_eq_int()
5674 bp->eq_cons = sw_cons; in bnx2x_eq_int()
5675 bp->eq_prod = sw_prod; in bnx2x_eq_int()
5680 bnx2x_update_eq_prod(bp, bp->eq_prod); in bnx2x_eq_int()
5691 if (atomic_read(&bp->interrupt_occurred)) { in bnx2x_sp_task()
5698 atomic_set(&bp->interrupt_occurred, 0); in bnx2x_sp_task()
5712 /* Prevent local bottom-halves from running as in bnx2x_sp_task()
5722 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, in bnx2x_sp_task()
5723 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); in bnx2x_sp_task()
5734 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, in bnx2x_sp_task()
5735 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); in bnx2x_sp_task()
5738 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ in bnx2x_sp_task()
5740 &bp->sp_state)) { in bnx2x_sp_task()
5751 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, in bnx2x_msix_sp_int()
5755 if (unlikely(bp->panic)) in bnx2x_msix_sp_int()
5763 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_msix_sp_int()
5765 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_msix_sp_int()
5782 bp->fw_drv_pulse_wr_seq); in bnx2x_drv_pulse()
5789 if (!netif_running(bp->dev)) in bnx2x_timer()
5798 ++bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5799 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; in bnx2x_timer()
5800 drv_pulse = bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5810 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) in bnx2x_timer()
5815 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_timer()
5822 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2x_timer()
5844 /* helper: writes FP SP data to FW - data_size in dwords */
5925 hc_sm->igu_sb_id = igu_sb_id; in bnx2x_setup_ndsb_state_machine()
5926 hc_sm->igu_seg_id = igu_seg_id; in bnx2x_setup_ndsb_state_machine()
5927 hc_sm->timer_value = 0xFF; in bnx2x_setup_ndsb_state_machine()
5928 hc_sm->time_to_expire = 0xFFFFFFFF; in bnx2x_setup_ndsb_state_machine()
6016 /* write indices to HW - PCI guarantees endianity of regpairs */ in bnx2x_init_sb()
6038 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_init_def_sb()
6039 dma_addr_t mapping = bp->def_status_blk_mapping; in bnx2x_init_def_sb()
6054 igu_sp_sb_index = bp->igu_dsb_id; in bnx2x_init_def_sb()
6061 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; in bnx2x_init_def_sb()
6063 bp->attn_state = 0; in bnx2x_init_def_sb()
6073 bp->attn_group[index].sig[sindex] = in bnx2x_init_def_sb()
6082 bp->attn_group[index].sig[4] = REG_RD(bp, in bnx2x_init_def_sb()
6085 bp->attn_group[index].sig[4] = 0; in bnx2x_init_def_sb()
6088 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_def_sb()
6116 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bnx2x_init_def_sb()
6124 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, in bnx2x_update_coalesce()
6125 bp->tx_ticks, bp->rx_ticks); in bnx2x_update_coalesce()
6130 spin_lock_init(&bp->spq_lock); in bnx2x_init_sp_ring()
6131 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); in bnx2x_init_sp_ring()
6133 bp->spq_prod_idx = 0; in bnx2x_init_sp_ring()
6134 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; in bnx2x_init_sp_ring()
6135 bp->spq_prod_bd = bp->spq; in bnx2x_init_sp_ring()
6136 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; in bnx2x_init_sp_ring()
6144 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; in bnx2x_init_eq_ring()
6146 elem->next_page.addr.hi = in bnx2x_init_eq_ring()
6147 cpu_to_le32(U64_HI(bp->eq_mapping + in bnx2x_init_eq_ring()
6149 elem->next_page.addr.lo = in bnx2x_init_eq_ring()
6150 cpu_to_le32(U64_LO(bp->eq_mapping + in bnx2x_init_eq_ring()
6153 bp->eq_cons = 0; in bnx2x_init_eq_ring()
6154 bp->eq_prod = NUM_EQ_DESC; in bnx2x_init_eq_ring()
6155 bp->eq_cons_sb = BNX2X_EQ_INDEX; in bnx2x_init_eq_ring()
6157 atomic_set(&bp->eq_spq_left, in bnx2x_init_eq_ring()
6158 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); in bnx2x_init_eq_ring()
6176 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; in bnx2x_set_q_rx_mode()
6179 ramrod_param.pstate = &bp->sp_state; in bnx2x_set_q_rx_mode()
6185 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_set_q_rx_mode()
6195 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); in bnx2x_set_q_rx_mode()
6227 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6243 if (bp->accept_any_vlan) { in bnx2x_fill_accept_flags()
6274 return -EINVAL; in bnx2x_fill_accept_flags()
6291 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, in bnx2x_set_storm_rx_mode()
6299 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, in bnx2x_set_storm_rx_mode()
6345 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_igu_sb_id()
6350 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_fw_sb_id()
6355 if (CHIP_IS_E1x(fp->bp)) in bnx2x_fp_cl_id()
6356 return BP_L_ID(fp->bp) + fp->index; in bnx2x_fp_cl_id()
6363 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; in bnx2x_init_eth_fp()
6367 fp->rx_queue = fp_idx; in bnx2x_init_eth_fp()
6368 fp->cid = fp_idx; in bnx2x_init_eth_fp()
6369 fp->cl_id = bnx2x_fp_cl_id(fp); in bnx2x_init_eth_fp()
6370 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); in bnx2x_init_eth_fp()
6371 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); in bnx2x_init_eth_fp()
6373 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); in bnx2x_init_eth_fp()
6376 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); in bnx2x_init_eth_fp()
6379 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; in bnx2x_init_eth_fp()
6385 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); in bnx2x_init_eth_fp()
6389 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], in bnx2x_init_eth_fp()
6390 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), in bnx2x_init_eth_fp()
6393 cids[cos] = fp->txdata_ptr[cos]->cid; in bnx2x_init_eth_fp()
6400 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, in bnx2x_init_eth_fp()
6401 fp->fw_sb_id, fp->igu_sb_id); in bnx2x_init_eth_fp()
6403 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, in bnx2x_init_eth_fp()
6404 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_eth_fp()
6414 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_eth_fp()
6415 fp->igu_sb_id); in bnx2x_init_eth_fp()
6424 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; in bnx2x_init_tx_ring_one()
6426 tx_next_bd->addr_hi = in bnx2x_init_tx_ring_one()
6427 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + in bnx2x_init_tx_ring_one()
6429 tx_next_bd->addr_lo = in bnx2x_init_tx_ring_one()
6430 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + in bnx2x_init_tx_ring_one()
6434 *txdata->tx_cons_sb = cpu_to_le16(0); in bnx2x_init_tx_ring_one()
6436 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); in bnx2x_init_tx_ring_one()
6437 txdata->tx_db.data.zero_fill1 = 0; in bnx2x_init_tx_ring_one()
6438 txdata->tx_db.data.prod = 0; in bnx2x_init_tx_ring_one()
6440 txdata->tx_pkt_prod = 0; in bnx2x_init_tx_ring_one()
6441 txdata->tx_pkt_cons = 0; in bnx2x_init_tx_ring_one()
6442 txdata->tx_bd_prod = 0; in bnx2x_init_tx_ring_one()
6443 txdata->tx_bd_cons = 0; in bnx2x_init_tx_ring_one()
6444 txdata->tx_pkt = 0; in bnx2x_init_tx_ring_one()
6452 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); in bnx2x_init_tx_rings_cnic()
6461 for_each_cos_in_tx_queue(&bp->fp[i], cos) in bnx2x_init_tx_rings()
6462 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); in bnx2x_init_tx_rings()
6475 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; in bnx2x_init_fcoe_fp()
6478 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, in bnx2x_init_fcoe_fp()
6481 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); in bnx2x_init_fcoe_fp()
6493 /* No multi-CoS for FCoE L2 client */ in bnx2x_init_fcoe_fp()
6494 BUG_ON(fp->max_cos != 1); in bnx2x_init_fcoe_fp()
6496 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, in bnx2x_init_fcoe_fp()
6497 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_fcoe_fp()
6502 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_fcoe_fp()
6503 fp->igu_sb_id); in bnx2x_init_fcoe_fp()
6511 bnx2x_init_sb(bp, bp->cnic_sb_mapping, in bnx2x_nic_init_cnic()
6539 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, in bnx2x_pre_irq_nic_init()
6540 bp->common.shmem_base, in bnx2x_pre_irq_nic_init()
6541 bp->common.shmem2_base, BP_PORT(bp)); in bnx2x_pre_irq_nic_init()
6573 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, in bnx2x_gunzip_init()
6574 &bp->gunzip_mapping, GFP_KERNEL); in bnx2x_gunzip_init()
6575 if (bp->gunzip_buf == NULL) in bnx2x_gunzip_init()
6578 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); in bnx2x_gunzip_init()
6579 if (bp->strm == NULL) in bnx2x_gunzip_init()
6582 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); in bnx2x_gunzip_init()
6583 if (bp->strm->workspace == NULL) in bnx2x_gunzip_init()
6589 kfree(bp->strm); in bnx2x_gunzip_init()
6590 bp->strm = NULL; in bnx2x_gunzip_init()
6593 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_init()
6594 bp->gunzip_mapping); in bnx2x_gunzip_init()
6595 bp->gunzip_buf = NULL; in bnx2x_gunzip_init()
6598 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); in bnx2x_gunzip_init()
6599 return -ENOMEM; in bnx2x_gunzip_init()
6604 if (bp->strm) { in bnx2x_gunzip_end()
6605 vfree(bp->strm->workspace); in bnx2x_gunzip_end()
6606 kfree(bp->strm); in bnx2x_gunzip_end()
6607 bp->strm = NULL; in bnx2x_gunzip_end()
6610 if (bp->gunzip_buf) { in bnx2x_gunzip_end()
6611 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_end()
6612 bp->gunzip_mapping); in bnx2x_gunzip_end()
6613 bp->gunzip_buf = NULL; in bnx2x_gunzip_end()
6624 return -EINVAL; in bnx2x_gunzip()
6634 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; in bnx2x_gunzip()
6635 bp->strm->avail_in = len - n; in bnx2x_gunzip()
6636 bp->strm->next_out = bp->gunzip_buf; in bnx2x_gunzip()
6637 bp->strm->avail_out = FW_BUF_SIZE; in bnx2x_gunzip()
6639 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); in bnx2x_gunzip()
6643 rc = zlib_inflate(bp->strm, Z_FINISH); in bnx2x_gunzip()
6645 netdev_err(bp->dev, "Firmware decompression error: %s\n", in bnx2x_gunzip()
6646 bp->strm->msg); in bnx2x_gunzip()
6648 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); in bnx2x_gunzip()
6649 if (bp->gunzip_outlen & 0x3) in bnx2x_gunzip()
6650 netdev_err(bp->dev, in bnx2x_gunzip()
6652 bp->gunzip_outlen); in bnx2x_gunzip()
6653 bp->gunzip_outlen >>= 2; in bnx2x_gunzip()
6655 zlib_inflateEnd(bp->strm); in bnx2x_gunzip()
6680 /* NON-IP protocol */ in bnx2x_lb_pckt()
6687 /* some of the internal memories
6727 count--; in bnx2x_int_mem_test()
6731 return -1; in bnx2x_int_mem_test()
6742 count--; in bnx2x_int_mem_test()
6746 return -2; in bnx2x_int_mem_test()
6783 count--; in bnx2x_int_mem_test()
6787 return -3; in bnx2x_int_mem_test()
6811 return -4; in bnx2x_int_mem_test()
6914 bp->dmae_ready = 0; in bnx2x_setup_dmae()
6915 spin_lock_init(&bp->dmae_lock); in bnx2x_setup_dmae()
6923 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); in bnx2x_init_pxp()
6926 if (bp->mrrs == -1) in bnx2x_init_pxp()
6929 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); in bnx2x_init_pxp()
6930 r_order = bp->mrrs; in bnx2x_init_pxp()
6962 bp->common.shmem_base, in bnx2x_setup_fan_failure_detection()
6963 bp->common.shmem2_base, in bnx2x_setup_fan_failure_detection()
7003 shmem_base[0] = bp->common.shmem_base; in bnx2x__common_init_phy()
7004 shmem2_base[0] = bp->common.shmem2_base; in bnx2x__common_init_phy()
7013 bp->common.chip_id); in bnx2x__common_init_phy()
7049 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7083 * 4-port mode or 2-port mode we need to turn of master-enable in bnx2x_init_hw_common()
7085 * so, we disregard multi-function or not, and always disable in bnx2x_init_hw_common()
7126 return -EBUSY; in bnx2x_init_hw_common()
7131 return -EBUSY; in bnx2x_init_hw_common()
7141 * (i.e. vnic3) to start even if it is marked as "scan-off". in bnx2x_init_hw_common()
7143 * as "scan-off". Real-life scenario for example: if a driver is being in bnx2x_init_hw_common()
7144 * load-unloaded while func6,7 are down. This will cause the timer to access in bnx2x_init_hw_common()
7159 * dmae-operations (writing to pram for example.) in bnx2x_init_hw_common()
7169 * b. Wait 20msec. - note that this timeout is needed to make in bnx2x_init_hw_common()
7200 * PF-s might be dynamic. in bnx2x_init_hw_common()
7209 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; in bnx2x_init_hw_common()
7246 } while (factor-- && (val != 1)); in bnx2x_init_hw_common()
7250 return -EBUSY; in bnx2x_init_hw_common()
7259 bp->dmae_ready = 1; in bnx2x_init_hw_common()
7278 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_common()
7299 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7312 /* Bit-map indicating which L2 hdrs may appear in bnx2x_init_hw_common()
7316 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7326 /* reset VFC memories */ in bnx2x_init_hw_common()
7364 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7388 dev_alert(&bp->pdev->dev, in bnx2x_init_hw_common()
7432 /* in E3 this done in per-port section */ in bnx2x_init_hw_common()
7447 return -EBUSY; in bnx2x_init_hw_common()
7452 return -EBUSY; in bnx2x_init_hw_common()
7457 return -EBUSY; in bnx2x_init_hw_common()
7470 return -EBUSY; in bnx2x_init_hw_common()
7486 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); in bnx2x_init_hw_common()
7495 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7506 /* In E2 2-PORT mode, same ext phy is used for the two paths */ in bnx2x_init_hw_common_chip()
7530 * attempted. Therefore we manually added the enable-master to the in bnx2x_init_hw_port()
7547 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_port()
7562 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); in bnx2x_init_hw_port()
7563 else if (bp->dev->mtu > 4096) { in bnx2x_init_hw_port()
7564 if (bp->flags & ONE_PORT_FLAG) in bnx2x_init_hw_port()
7567 val = bp->dev->mtu; in bnx2x_init_hw_port()
7573 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); in bnx2x_init_hw_port()
7598 /* Ovlan exists only if we are in multi-function + in bnx2x_init_hw_port()
7599 * switch-dependent mode, in switch-independent there in bnx2x_init_hw_port()
7605 (bp->path_has_ovlan ? 7 : 6)); in bnx2x_init_hw_port()
7631 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7655 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use in bnx2x_init_hw_port()
7656 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF in bnx2x_init_hw_port()
7657 * bits 4-7 are used for "per vn group attention" */ in bnx2x_init_hw_port()
7677 /* Bit-map indicating which L2 hdrs may appear after the in bnx2x_init_hw_port()
7705 switch (bp->mf_mode) { in bnx2x_init_hw_port()
7736 bp->flags |= PTP_SUPPORTED; in bnx2x_init_hw_port()
7789 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) in bnx2x_igu_clear_sb_gen()
7814 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); in bnx2x_init_searcher()
7830 func_params.f_obj = &bp->func_obj; in bnx2x_func_switch_update()
7835 &switch_update_params->changes); in bnx2x_func_switch_update()
7838 &switch_update_params->changes); in bnx2x_func_switch_update()
7851 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7852 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_reset_nic_mode()
7881 BNX2X_ERR("Can't suspend tx-switching!\n"); in bnx2x_reset_nic_mode()
7889 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7890 bnx2x_set_rx_filter(&bp->link_params, 1); in bnx2x_reset_nic_mode()
7909 BNX2X_ERR("Can't resume tx-switching!\n"); in bnx2x_reset_nic_mode()
7937 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7939 * the addresses of the transaction, resulting in was-error bit set in the pci
7940 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7964 /* FLR cleanup - hmmm */ in bnx2x_init_hw_func()
7974 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
7985 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; in bnx2x_init_hw_func()
7994 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; in bnx2x_init_hw_func()
7996 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; in bnx2x_init_hw_func()
7997 ilt->lines[cdu_ilt_start + i].page_mapping = in bnx2x_init_hw_func()
7998 bp->context[i].cxt_mapping; in bnx2x_init_hw_func()
7999 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; in bnx2x_init_hw_func()
8020 if (!(bp->flags & USING_MSIX_FLAG)) in bnx2x_init_hw_func()
8030 * Master enable - Due to WB DMAE writes performed before this in bnx2x_init_hw_func()
8031 * register is re-initialized as part of the regular function in bnx2x_init_hw_func()
8039 bp->dmae_ready = 1; in bnx2x_init_hw_func()
8099 bp->mf_ov); in bnx2x_init_hw_func()
8106 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
8131 * E2 mode: address 0-135 match to the mapping memory; in bnx2x_init_hw_func()
8132 * 136 - PF0 default prod; 137 - PF1 default prod; in bnx2x_init_hw_func()
8133 * 138 - PF2 default prod; 139 - PF3 default prod; in bnx2x_init_hw_func()
8134 * 140 - PF0 attn prod; 141 - PF1 attn prod; in bnx2x_init_hw_func()
8135 * 142 - PF2 attn prod; 143 - PF3 attn prod; in bnx2x_init_hw_func()
8136 * 144-147 reserved. in bnx2x_init_hw_func()
8138 * E1.5 mode - In backward compatible mode; in bnx2x_init_hw_func()
8142 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 in bnx2x_init_hw_func()
8145 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; in bnx2x_init_hw_func()
8146 * 132-135 C prods; 136-139 X prods; 140-143 T prods; in bnx2x_init_hw_func()
8147 * 144-147 attn prods; in bnx2x_init_hw_func()
8149 /* non-default-status-blocks */ in bnx2x_init_hw_func()
8152 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { in bnx2x_init_hw_func()
8153 prod_offset = (bp->igu_base_sb + sb_idx) * in bnx2x_init_hw_func()
8162 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, in bnx2x_init_hw_func()
8165 bp->igu_base_sb + sb_idx); in bnx2x_init_hw_func()
8168 /* default-status-blocks */ in bnx2x_init_hw_func()
8182 * igu prods come in chunks of E1HVN_MAX (4) - in bnx2x_init_hw_func()
8193 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8195 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8197 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8199 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8201 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8204 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8206 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8209 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); in bnx2x_init_hw_func()
8212 rf-tool supports split-68 const */ in bnx2x_init_hw_func()
8239 /* Clear "false" parity errors in MSI-X table */ in bnx2x_init_hw_func()
8263 bnx2x_phy_probe(&bp->link_params); in bnx2x_init_hw_func()
8273 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8276 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8279 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem_cnic()
8286 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, in bnx2x_free_mem()
8287 bp->fw_stats_data_sz + bp->fw_stats_req_sz); in bnx2x_free_mem()
8292 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, in bnx2x_free_mem()
8295 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, in bnx2x_free_mem()
8299 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, in bnx2x_free_mem()
8300 bp->context[i].size); in bnx2x_free_mem()
8303 BNX2X_FREE(bp->ilt->lines); in bnx2x_free_mem()
8305 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_free_mem()
8307 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, in bnx2x_free_mem()
8310 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem()
8319 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8321 if (!bp->cnic_sb.e2_sb) in bnx2x_alloc_mem_cnic()
8324 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8326 if (!bp->cnic_sb.e1x_sb) in bnx2x_alloc_mem_cnic()
8330 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem_cnic()
8332 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem_cnic()
8333 if (!bp->t2) in bnx2x_alloc_mem_cnic()
8338 bp->cnic_eth_dev.addr_drv_info_to_mcp = in bnx2x_alloc_mem_cnic()
8339 &bp->slowpath->drv_info_to_mcp; in bnx2x_alloc_mem_cnic()
8349 return -ENOMEM; in bnx2x_alloc_mem_cnic()
8356 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem()
8358 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem()
8359 if (!bp->t2) in bnx2x_alloc_mem()
8363 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, in bnx2x_alloc_mem()
8365 if (!bp->def_status_blk) in bnx2x_alloc_mem()
8368 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, in bnx2x_alloc_mem()
8370 if (!bp->slowpath) in bnx2x_alloc_mem()
8376 * 1. There are multiple entities allocating memory for context - in bnx2x_alloc_mem()
8379 * 2. Since CDU page-size is not a single 4KB page (which is the case in bnx2x_alloc_mem()
8381 * allocation of sub-page-size in the last entry. in bnx2x_alloc_mem()
8389 bp->context[i].size = min(CDU_ILT_PAGE_SZ, in bnx2x_alloc_mem()
8390 (context_size - allocated)); in bnx2x_alloc_mem()
8391 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, in bnx2x_alloc_mem()
8392 bp->context[i].size); in bnx2x_alloc_mem()
8393 if (!bp->context[i].vcxt) in bnx2x_alloc_mem()
8395 allocated += bp->context[i].size; in bnx2x_alloc_mem()
8397 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), in bnx2x_alloc_mem()
8399 if (!bp->ilt->lines) in bnx2x_alloc_mem()
8409 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_alloc_mem()
8410 if (!bp->spq) in bnx2x_alloc_mem()
8414 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, in bnx2x_alloc_mem()
8416 if (!bp->eq_ring) in bnx2x_alloc_mem()
8424 return -ENOMEM; in bnx2x_alloc_mem()
8459 if (rc == -EEXIST) { in bnx2x_set_mac_one()
8495 if (rc == -EEXIST) { in bnx2x_set_vlan_one()
8511 list_for_each_entry(vlan, &bp->vlan_reg, link) in bnx2x_clear_vlan_info()
8512 vlan->hw = false; in bnx2x_clear_vlan_info()
8514 bp->vlan_cnt = 0; in bnx2x_clear_vlan_info()
8519 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; in bnx2x_del_all_vlans()
8525 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); in bnx2x_del_all_vlans()
8548 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); in bnx2x_del_all_macs()
8562 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8563 &bp->sp_objs->mac_obj, set, in bnx2x_set_eth_mac()
8566 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8567 bp->fp->index, set); in bnx2x_set_eth_mac()
8574 return bnx2x_setup_queue(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8576 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8580 * bnx2x_set_int_mode - configure interrupt mode
8584 * In case of MSI-X it will also try to enable MSI-X.
8592 return -EINVAL; in bnx2x_set_int_mode()
8608 /* failed to enable multiple MSI-X */ in bnx2x_set_int_mode()
8609 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", in bnx2x_set_int_mode()
8610 bp->num_queues, in bnx2x_set_int_mode()
8611 1 + bp->num_cnic_queues); in bnx2x_set_int_mode()
8619 bp->num_ethernet_queues = 1; in bnx2x_set_int_mode()
8620 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; in bnx2x_set_int_mode()
8625 return -EINVAL; in bnx2x_set_int_mode()
8644 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); in bnx2x_ilt_set_info()
8645 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); in bnx2x_ilt_set_info()
8648 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; in bnx2x_ilt_set_info()
8649 ilt_client->client_num = ILT_CLIENT_CDU; in bnx2x_ilt_set_info()
8650 ilt_client->page_size = CDU_ILT_PAGE_SZ; in bnx2x_ilt_set_info()
8651 ilt_client->flags = ILT_CLIENT_SKIP_MEM; in bnx2x_ilt_set_info()
8652 ilt_client->start = line; in bnx2x_ilt_set_info()
8657 ilt_client->end = line - 1; in bnx2x_ilt_set_info()
8660 ilt_client->start, in bnx2x_ilt_set_info()
8661 ilt_client->end, in bnx2x_ilt_set_info()
8662 ilt_client->page_size, in bnx2x_ilt_set_info()
8663 ilt_client->flags, in bnx2x_ilt_set_info()
8664 ilog2(ilt_client->page_size >> 12)); in bnx2x_ilt_set_info()
8667 if (QM_INIT(bp->qm_cid_count)) { in bnx2x_ilt_set_info()
8668 ilt_client = &ilt->clients[ILT_CLIENT_QM]; in bnx2x_ilt_set_info()
8669 ilt_client->client_num = ILT_CLIENT_QM; in bnx2x_ilt_set_info()
8670 ilt_client->page_size = QM_ILT_PAGE_SZ; in bnx2x_ilt_set_info()
8671 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8672 ilt_client->start = line; in bnx2x_ilt_set_info()
8675 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, in bnx2x_ilt_set_info()
8678 ilt_client->end = line - 1; in bnx2x_ilt_set_info()
8682 ilt_client->start, in bnx2x_ilt_set_info()
8683 ilt_client->end, in bnx2x_ilt_set_info()
8684 ilt_client->page_size, in bnx2x_ilt_set_info()
8685 ilt_client->flags, in bnx2x_ilt_set_info()
8686 ilog2(ilt_client->page_size >> 12)); in bnx2x_ilt_set_info()
8691 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; in bnx2x_ilt_set_info()
8692 ilt_client->client_num = ILT_CLIENT_SRC; in bnx2x_ilt_set_info()
8693 ilt_client->page_size = SRC_ILT_PAGE_SZ; in bnx2x_ilt_set_info()
8694 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8695 ilt_client->start = line; in bnx2x_ilt_set_info()
8697 ilt_client->end = line - 1; in bnx2x_ilt_set_info()
8701 ilt_client->start, in bnx2x_ilt_set_info()
8702 ilt_client->end, in bnx2x_ilt_set_info()
8703 ilt_client->page_size, in bnx2x_ilt_set_info()
8704 ilt_client->flags, in bnx2x_ilt_set_info()
8705 ilog2(ilt_client->page_size >> 12)); in bnx2x_ilt_set_info()
8708 ilt_client = &ilt->clients[ILT_CLIENT_TM]; in bnx2x_ilt_set_info()
8709 ilt_client->client_num = ILT_CLIENT_TM; in bnx2x_ilt_set_info()
8710 ilt_client->page_size = TM_ILT_PAGE_SZ; in bnx2x_ilt_set_info()
8711 ilt_client->flags = 0; in bnx2x_ilt_set_info()
8712 ilt_client->start = line; in bnx2x_ilt_set_info()
8714 ilt_client->end = line - 1; in bnx2x_ilt_set_info()
8718 ilt_client->start, in bnx2x_ilt_set_info()
8719 ilt_client->end, in bnx2x_ilt_set_info()
8720 ilt_client->page_size, in bnx2x_ilt_set_info()
8721 ilt_client->flags, in bnx2x_ilt_set_info()
8722 ilog2(ilt_client->page_size >> 12)); in bnx2x_ilt_set_info()
8729 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8736 * - HC configuration
8737 * - Queue's CDU context
8747 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); in bnx2x_pf_q_prep_init()
8748 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); in bnx2x_pf_q_prep_init()
8753 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); in bnx2x_pf_q_prep_init()
8754 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); in bnx2x_pf_q_prep_init()
8757 init_params->rx.hc_rate = bp->rx_ticks ? in bnx2x_pf_q_prep_init()
8758 (1000000 / bp->rx_ticks) : 0; in bnx2x_pf_q_prep_init()
8759 init_params->tx.hc_rate = bp->tx_ticks ? in bnx2x_pf_q_prep_init()
8760 (1000000 / bp->tx_ticks) : 0; in bnx2x_pf_q_prep_init()
8763 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = in bnx2x_pf_q_prep_init()
8764 fp->fw_sb_id; in bnx2x_pf_q_prep_init()
8770 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; in bnx2x_pf_q_prep_init()
8771 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; in bnx2x_pf_q_prep_init()
8775 init_params->max_cos = fp->max_cos; in bnx2x_pf_q_prep_init()
8778 fp->index, init_params->max_cos); in bnx2x_pf_q_prep_init()
8781 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { in bnx2x_pf_q_prep_init()
8782 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; in bnx2x_pf_q_prep_init()
8783 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * in bnx2x_pf_q_prep_init()
8785 init_params->cxts[cos] = in bnx2x_pf_q_prep_init()
8786 &bp->context[cxt_index].vcxt[cxt_offset].eth; in bnx2x_pf_q_prep_init()
8798 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; in bnx2x_setup_tx_only()
8800 /* Set tx-only QUEUE flags: don't zero statistics */ in bnx2x_setup_tx_only()
8801 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); in bnx2x_setup_tx_only()
8804 tx_only_params->cid_index = tx_index; in bnx2x_setup_tx_only()
8807 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); in bnx2x_setup_tx_only()
8810 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); in bnx2x_setup_tx_only()
8813 …"preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp… in bnx2x_setup_tx_only()
8814 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], in bnx2x_setup_tx_only()
8815 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, in bnx2x_setup_tx_only()
8816 tx_only_params->gen_params.spcl_id, tx_only_params->flags); in bnx2x_setup_tx_only()
8823 * bnx2x_setup_queue - setup queue
8830 * actually: 1) RESET->INIT 2) INIT->SETUP
8844 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); in bnx2x_setup_queue()
8848 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, in bnx2x_setup_queue()
8864 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); in bnx2x_setup_queue()
8874 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); in bnx2x_setup_queue()
8877 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, in bnx2x_setup_queue()
8880 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, in bnx2x_setup_queue()
8881 &setup_params->rxq_params); in bnx2x_setup_queue()
8883 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, in bnx2x_setup_queue()
8890 bp->fcoe_init = true; in bnx2x_setup_queue()
8895 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); in bnx2x_setup_queue()
8899 /* loop through the relevant tx-only indices */ in bnx2x_setup_queue()
8901 tx_index < fp->max_cos; in bnx2x_setup_queue()
8904 /* prepare and send tx-only ramrod*/ in bnx2x_setup_queue()
8909 fp->index, tx_index); in bnx2x_setup_queue()
8919 struct bnx2x_fastpath *fp = &bp->fp[index]; in bnx2x_stop_queue()
8924 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); in bnx2x_stop_queue()
8930 /* close tx-only connections */ in bnx2x_stop_queue()
8932 tx_index < fp->max_cos; in bnx2x_stop_queue()
8936 txdata = fp->txdata_ptr[tx_index]; in bnx2x_stop_queue()
8938 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", in bnx2x_stop_queue()
8939 txdata->txq_index); in bnx2x_stop_queue()
8941 /* send halt terminate on tx-only connection */ in bnx2x_stop_queue()
8951 /* send halt terminate on tx-only connection */ in bnx2x_stop_queue()
8997 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_reset_func()
8999 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), in bnx2x_reset_func()
9019 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_reset_func()
9043 /* Timers workaround bug for E2: if this is vnic-3, in bnx2x_reset_func()
9051 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; in bnx2x_reset_func()
9061 bp->dmae_ready = 0; in bnx2x_reset_func()
9100 func_params.f_obj = &bp->func_obj; in bnx2x_reset_hw()
9115 func_params.f_obj = &bp->func_obj; in bnx2x_func_stop()
9139 * bnx2x_send_unload_req - request unload mode from the MCP.
9155 else if (bp->flags & NO_WOL_FLAG) in bnx2x_send_unload_req()
9158 else if (bp->wol) { in bnx2x_send_unload_req()
9160 const u8 *mac_addr = bp->dev->dev_addr; in bnx2x_send_unload_req()
9161 struct pci_dev *pdev = bp->pdev; in bnx2x_send_unload_req()
9165 /* The mac address is written to entries 1-4 to in bnx2x_send_unload_req()
9178 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); in bnx2x_send_unload_req()
9180 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); in bnx2x_send_unload_req()
9193 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", in bnx2x_send_unload_req()
9196 bnx2x_load_count[path][0]--; in bnx2x_send_unload_req()
9197 bnx2x_load_count[path][1 + port]--; in bnx2x_send_unload_req()
9198 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", in bnx2x_send_unload_req()
9213 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9230 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_func_wait_started()
9232 if (!bp->port.pmf) in bnx2x_func_wait_started()
9239 * 2. Sync SP queue - this guarantees us that attention handling started in bnx2x_func_wait_started()
9243 * pending bit of transaction from STARTED-->TX_STOPPED, if we already in bnx2x_func_wait_started()
9245 * State will return to STARTED after completion of TX_STOPPED-->STARTED in bnx2x_func_wait_started()
9251 synchronize_irq(bp->msix_table[0].vector); in bnx2x_func_wait_started()
9253 synchronize_irq(bp->pdev->irq); in bnx2x_func_wait_started()
9258 while (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9259 BNX2X_F_STATE_STARTED && tout--) in bnx2x_func_wait_started()
9262 if (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9266 return -EBUSY; in bnx2x_func_wait_started()
9275 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); in bnx2x_func_wait_started()
9277 func_params.f_obj = &bp->func_obj; in bnx2x_func_wait_started()
9281 /* STARTED-->TX_ST0PPED */ in bnx2x_func_wait_started()
9285 /* TX_ST0PPED-->STARTED */ in bnx2x_func_wait_started()
9317 /* Called during unload, to stop PTP-related stuff */
9323 cancel_work_sync(&bp->ptp_task); in bnx2x_stop_ptp()
9325 if (bp->ptp_tx_skb) { in bnx2x_stop_ptp()
9326 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_stop_ptp()
9327 bp->ptp_tx_skb = NULL; in bnx2x_stop_ptp()
9346 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_chip_cleanup()
9349 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); in bnx2x_chip_cleanup()
9360 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, in bnx2x_chip_cleanup()
9366 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, in bnx2x_chip_cleanup()
9391 netif_addr_lock_bh(bp->dev); in bnx2x_chip_cleanup()
9393 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_chip_cleanup()
9394 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_chip_cleanup()
9395 else if (bp->slowpath) in bnx2x_chip_cleanup()
9399 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_chip_cleanup()
9404 netif_addr_unlock_bh(bp->dev); in bnx2x_chip_cleanup()
9448 /* If SP settings didn't get completed so far - something in bnx2x_chip_cleanup()
9470 if (bp->flags & PTP_SUPPORTED) { in bnx2x_chip_cleanup()
9472 if (bp->ptp_clock) { in bnx2x_chip_cleanup()
9473 ptp_clock_unregister(bp->ptp_clock); in bnx2x_chip_cleanup()
9474 bp->ptp_clock = NULL; in bnx2x_chip_cleanup()
9493 if (!pci_channel_offline(bp->pdev)) { in bnx2x_chip_cleanup()
9575 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9589 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9621 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9636 * initializes bp->common.shmem_base and waits for validity signature to appear
9644 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_init_shmem()
9649 if (bp->common.shmem_base == 0xFFFFFFFF) { in bnx2x_init_shmem()
9650 bp->flags |= NO_MCP_FLAG; in bnx2x_init_shmem()
9651 return -ENODEV; in bnx2x_init_shmem()
9654 if (bp->common.shmem_base) { in bnx2x_init_shmem()
9666 return -ENODEV; in bnx2x_init_shmem()
9690 * - PCIE core
9691 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9693 * - IGU
9694 * - MISC (including AEU)
9695 * - GRC
9696 * - RBCN, RBCP
9741 * - all xxMACs are handled by the bnx2x_link code. in bnx2x_process_kill_chip_reset()
9794 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9814 } while (cnt-- > 0); in bnx2x_er_poll_igu_vq()
9819 return -EBUSY; in bnx2x_er_poll_igu_vq()
9849 } while (cnt-- > 0); in bnx2x_process_kill()
9856 return -EAGAIN; in bnx2x_process_kill()
9866 return -EAGAIN; in bnx2x_process_kill()
9874 /* Wait for 1ms to empty GLUE and PCI-E core queues, in bnx2x_process_kill()
9899 return -EAGAIN; in bnx2x_process_kill()
9907 * reset state, re-enable attentions. */ in bnx2x_process_kill()
9918 /* if not going to reset MCP - load "fake" driver to reset HW while in bnx2x_leader_reset()
9926 rc = -EAGAIN; in bnx2x_leader_reset()
9932 rc = -EAGAIN; in bnx2x_leader_reset()
9938 rc = -EAGAIN; in bnx2x_leader_reset()
9947 rc = -EAGAIN; in bnx2x_leader_reset()
9966 bp->is_leader = 0; in bnx2x_leader_reset()
9974 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); in bnx2x_recovery_failed()
9977 netif_device_detach(bp->dev); in bnx2x_recovery_failed()
9988 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_recovery_failed()
9996 * will never be called when netif_running(bp->dev) is false.
10005 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { in bnx2x_parity_recover()
10009 vf->state = VF_LOST; in bnx2x_parity_recover()
10014 switch (bp->recovery_state) { in bnx2x_parity_recover()
10032 bp->is_leader = 1; in bnx2x_parity_recover()
10036 /* If interface has been removed - break */ in bnx2x_parity_recover()
10040 bp->recovery_state = BNX2X_RECOVERY_WAIT; in bnx2x_parity_recover()
10051 if (bp->is_leader) { in bnx2x_parity_recover()
10072 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
10076 /* If all other functions got down - in bnx2x_parity_recover()
10089 * to continue as a none-leader. in bnx2x_parity_recover()
10093 } else { /* non-leader */ in bnx2x_parity_recover()
10105 bp->is_leader = 1; in bnx2x_parity_recover()
10109 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
10120 &bp->sp_rtnl_task, in bnx2x_parity_recover()
10126 bp->eth_stats.recoverable_error; in bnx2x_parity_recover()
10128 bp->eth_stats.unrecoverable_error; in bnx2x_parity_recover()
10129 bp->recovery_state = in bnx2x_parity_recover()
10133 netdev_err(bp->dev, in bnx2x_parity_recover()
10136 netif_device_detach(bp->dev); in bnx2x_parity_recover()
10142 bp->recovery_state = in bnx2x_parity_recover()
10147 bp->eth_stats.recoverable_error = in bnx2x_parity_recover()
10149 bp->eth_stats.unrecoverable_error = in bnx2x_parity_recover()
10174 func_params.f_obj = &bp->func_obj; in bnx2x_udp_port_update()
10179 &switch_update_params->changes); in bnx2x_udp_port_update()
10181 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { in bnx2x_udp_port_update()
10182 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; in bnx2x_udp_port_update()
10183 switch_update_params->geneve_dst_port = geneve_port; in bnx2x_udp_port_update()
10186 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { in bnx2x_udp_port_update()
10187 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; in bnx2x_udp_port_update()
10188 switch_update_params->vxlan_dst_port = vxlan_port; in bnx2x_udp_port_update()
10191 /* Re-enable inner-rss for the offloaded UDP tunnels */ in bnx2x_udp_port_update()
10193 &switch_update_params->changes); in bnx2x_udp_port_update()
10213 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); in bnx2x_udp_tunnel_sync()
10239 if (!netif_running(bp->dev)) { in bnx2x_sp_rtnl_task()
10244 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { in bnx2x_sp_rtnl_task()
10254 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10263 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10274 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10278 bp->link_vars.link_up = 0; in bnx2x_sp_rtnl_task()
10279 bp->force_link_down = true; in bnx2x_sp_rtnl_task()
10280 netif_carrier_off(bp->dev); in bnx2x_sp_rtnl_task()
10281 BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); in bnx2x_sp_rtnl_task()
10288 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { in bnx2x_sp_rtnl_task()
10299 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10300 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); in bnx2x_sp_rtnl_task()
10301 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10308 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10310 netif_device_detach(bp->dev); in bnx2x_sp_rtnl_task()
10311 bnx2x_close(bp->dev); in bnx2x_sp_rtnl_task()
10316 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10318 "sending set mcast vf pf channel message from rtnl sp-task\n"); in bnx2x_sp_rtnl_task()
10319 bnx2x_vfpf_set_mcast(bp->dev); in bnx2x_sp_rtnl_task()
10322 &bp->sp_rtnl_state)){ in bnx2x_sp_rtnl_task()
10323 if (netif_carrier_ok(bp->dev)) { in bnx2x_sp_rtnl_task()
10329 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10335 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10338 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10344 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10347 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10350 /* work which needs rtnl lock not-taken (as it takes the lock itself and in bnx2x_sp_rtnl_task()
10355 /* enable SR-IOV if applicable */ in bnx2x_sp_rtnl_task()
10357 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10367 if (!netif_running(bp->dev)) in bnx2x_period_task()
10378 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and in bnx2x_period_task()
10382 if (bp->port.pmf) { in bnx2x_period_task()
10383 bnx2x_period_func(&bp->link_params, &bp->link_vars); in bnx2x_period_task()
10385 /* Re-queue task in 1 sec */ in bnx2x_period_task()
10386 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); in bnx2x_period_task()
10401 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; in bnx2x_get_pretend_reg()
10417 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; in bnx2x_prev_unload_close_umac()
10418 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); in bnx2x_prev_unload_close_umac()
10419 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10455 vals->bmac_addr = base_addr + offset; in bnx2x_prev_unload_close_mac()
10456 vals->bmac_val[0] = wb_data[0]; in bnx2x_prev_unload_close_mac()
10457 vals->bmac_val[1] = wb_data[1]; in bnx2x_prev_unload_close_mac()
10459 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10460 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10463 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; in bnx2x_prev_unload_close_mac()
10464 vals->emac_val = REG_RD(bp, vals->emac_addr); in bnx2x_prev_unload_close_mac()
10465 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10476 vals->xmac_addr = base_addr + XMAC_REG_CTRL; in bnx2x_prev_unload_close_mac()
10477 vals->xmac_val = REG_RD(bp, vals->xmac_addr); in bnx2x_prev_unload_close_mac()
10478 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10505 /* UNDI marks its presence in DORQ - in bnx2x_prev_is_after_undi()
10528 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); in bnx2x_prev_unload_undi_inc()
10537 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", in bnx2x_prev_unload_undi_inc()
10547 return -EBUSY; in bnx2x_prev_mcp_done()
10559 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && in bnx2x_prev_path_get_entry()
10560 bp->pdev->bus->number == tmp_list->bus && in bnx2x_prev_path_get_entry()
10561 BP_PATH(bp) == tmp_list->path) in bnx2x_prev_path_get_entry()
10580 tmp_list->aer = 1; in bnx2x_prev_path_mark_eeh()
10602 if (tmp_list->aer) { in bnx2x_prev_is_path_marked()
10625 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); in bnx2x_port_after_undi()
10646 if (!tmp_list->aer) { in bnx2x_prev_mark_path()
10647 BNX2X_ERR("Re-Marking the path.\n"); in bnx2x_prev_mark_path()
10651 tmp_list->aer = 0; in bnx2x_prev_mark_path()
10662 return -ENOMEM; in bnx2x_prev_mark_path()
10665 tmp_list->bus = bp->pdev->bus->number; in bnx2x_prev_mark_path()
10666 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); in bnx2x_prev_mark_path()
10667 tmp_list->path = BP_PATH(bp); in bnx2x_prev_mark_path()
10668 tmp_list->aer = 0; in bnx2x_prev_mark_path()
10669 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; in bnx2x_prev_mark_path()
10676 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", in bnx2x_prev_mark_path()
10678 list_add(&tmp_list->list, &bnx2x_prev_list); in bnx2x_prev_mark_path()
10687 struct pci_dev *dev = bp->pdev; in bnx2x_do_flr()
10691 return -EINVAL; in bnx2x_do_flr()
10695 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { in bnx2x_do_flr()
10697 bp->common.bc_ver); in bnx2x_do_flr()
10698 return -EINVAL; in bnx2x_do_flr()
10702 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); in bnx2x_do_flr()
10782 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10783 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10784 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10785 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10814 timer_count--; in bnx2x_prev_unload_common()
10866 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); in bnx2x_prev_unload()
10892 rc = -EBUSY; in bnx2x_prev_unload()
10903 bnx2x_prev_path_get_entry(bp)->aer); in bnx2x_prev_unload()
10912 /* non-common reply from MCP might require looping */ in bnx2x_prev_unload()
10918 } while (--time_counter); in bnx2x_prev_unload()
10922 rc = -EPROBE_DEFER; in bnx2x_prev_unload()
10927 bp->link_params.feature_config_flags |= in bnx2x_prev_unload()
10941 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ in bnx2x_get_common_hwinfo()
10954 bp->common.chip_id = id; in bnx2x_get_common_hwinfo()
10959 bp->common.chip_id = (CHIP_NUM_57811 << 16) | in bnx2x_get_common_hwinfo()
10960 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10962 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | in bnx2x_get_common_hwinfo()
10963 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10964 bp->common.chip_id |= 0x1; in bnx2x_get_common_hwinfo()
10968 bp->db_size = (1 << BNX2X_DB_SHIFT); in bnx2x_get_common_hwinfo()
10978 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : in bnx2x_get_common_hwinfo()
10982 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ in bnx2x_get_common_hwinfo()
10984 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ in bnx2x_get_common_hwinfo()
10986 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ in bnx2x_get_common_hwinfo()
10987 bp->pfid = bp->pf_num; /* 0..7 */ in bnx2x_get_common_hwinfo()
10990 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); in bnx2x_get_common_hwinfo()
10992 bp->link_params.chip_id = bp->common.chip_id; in bnx2x_get_common_hwinfo()
10996 if ((bp->common.chip_id & 0x1) || in bnx2x_get_common_hwinfo()
10998 bp->flags |= ONE_PORT_FLAG; in bnx2x_get_common_hwinfo()
11003 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << in bnx2x_get_common_hwinfo()
11006 bp->common.flash_size, bp->common.flash_size); in bnx2x_get_common_hwinfo()
11010 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? in bnx2x_get_common_hwinfo()
11014 bp->link_params.shmem_base = bp->common.shmem_base; in bnx2x_get_common_hwinfo()
11015 bp->link_params.shmem2_base = bp->common.shmem2_base; in bnx2x_get_common_hwinfo()
11018 bp->link_params.lfa_base = in bnx2x_get_common_hwinfo()
11019 REG_RD(bp, bp->common.shmem2_base + in bnx2x_get_common_hwinfo()
11023 bp->link_params.lfa_base = 0; in bnx2x_get_common_hwinfo()
11025 bp->common.shmem_base, bp->common.shmem2_base); in bnx2x_get_common_hwinfo()
11027 if (!bp->common.shmem_base) { in bnx2x_get_common_hwinfo()
11029 bp->flags |= NO_MCP_FLAG; in bnx2x_get_common_hwinfo()
11033 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); in bnx2x_get_common_hwinfo()
11034 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); in bnx2x_get_common_hwinfo()
11036 bp->link_params.hw_led_mode = ((bp->common.hw_config & in bnx2x_get_common_hwinfo()
11040 bp->link_params.feature_config_flags = 0; in bnx2x_get_common_hwinfo()
11043 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11046 bp->link_params.feature_config_flags &= in bnx2x_get_common_hwinfo()
11050 bp->common.bc_ver = val; in bnx2x_get_common_hwinfo()
11058 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11062 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11065 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11068 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11072 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
11076 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? in bnx2x_get_common_hwinfo()
11079 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? in bnx2x_get_common_hwinfo()
11082 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? in bnx2x_get_common_hwinfo()
11085 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? in bnx2x_get_common_hwinfo()
11093 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; in bnx2x_get_common_hwinfo()
11096 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; in bnx2x_get_common_hwinfo()
11099 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; in bnx2x_get_common_hwinfo()
11102 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; in bnx2x_get_common_hwinfo()
11106 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); in bnx2x_get_common_hwinfo()
11107 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; in bnx2x_get_common_hwinfo()
11110 (bp->flags & NO_WOL_FLAG) ? "not " : ""); in bnx2x_get_common_hwinfo()
11117 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", in bnx2x_get_common_hwinfo()
11131 bp->igu_base_sb = 0xff; in bnx2x_get_igu_cam_info()
11134 igu_sb_cnt = bp->igu_sb_cnt; in bnx2x_get_igu_cam_info()
11135 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * in bnx2x_get_igu_cam_info()
11138 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + in bnx2x_get_igu_cam_info()
11144 /* IGU in normal mode - read CAM */ in bnx2x_get_igu_cam_info()
11156 bp->igu_dsb_id = igu_sb_id; in bnx2x_get_igu_cam_info()
11158 if (bp->igu_base_sb == 0xff) in bnx2x_get_igu_cam_info()
11159 bp->igu_base_sb = igu_sb_id; in bnx2x_get_igu_cam_info()
11172 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); in bnx2x_get_igu_cam_info()
11177 return -EINVAL; in bnx2x_get_igu_cam_info()
11188 bp->port.supported[0] = 0; in bnx2x_link_settings_supported()
11189 bp->port.supported[1] = 0; in bnx2x_link_settings_supported()
11190 switch (bp->link_params.num_phys) { in bnx2x_link_settings_supported()
11192 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; in bnx2x_link_settings_supported()
11196 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11200 if (bp->link_params.multi_phy_config & in bnx2x_link_settings_supported()
11202 bp->port.supported[1] = in bnx2x_link_settings_supported()
11203 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11204 bp->port.supported[0] = in bnx2x_link_settings_supported()
11205 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11207 bp->port.supported[0] = in bnx2x_link_settings_supported()
11208 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
11209 bp->port.supported[1] = in bnx2x_link_settings_supported()
11210 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
11216 if (!(bp->port.supported[0] || bp->port.supported[1])) { in bnx2x_link_settings_supported()
11226 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); in bnx2x_link_settings_supported()
11230 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11234 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
11239 bp->port.link_config[0]); in bnx2x_link_settings_supported()
11243 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); in bnx2x_link_settings_supported()
11246 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11248 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; in bnx2x_link_settings_supported()
11250 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11252 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; in bnx2x_link_settings_supported()
11254 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11256 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; in bnx2x_link_settings_supported()
11258 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11260 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; in bnx2x_link_settings_supported()
11262 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11264 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | in bnx2x_link_settings_supported()
11267 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11269 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; in bnx2x_link_settings_supported()
11271 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11273 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; in bnx2x_link_settings_supported()
11275 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11277 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; in bnx2x_link_settings_supported()
11280 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], in bnx2x_link_settings_supported()
11281 bp->port.supported[1]); in bnx2x_link_settings_supported()
11287 bp->port.advertising[0] = 0; in bnx2x_link_settings_requested()
11288 bp->port.advertising[1] = 0; in bnx2x_link_settings_requested()
11289 switch (bp->link_params.num_phys) { in bnx2x_link_settings_requested()
11299 bp->link_params.req_duplex[idx] = DUPLEX_FULL; in bnx2x_link_settings_requested()
11300 link_config = bp->port.link_config[idx]; in bnx2x_link_settings_requested()
11303 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { in bnx2x_link_settings_requested()
11304 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11306 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11307 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11308 if (bp->link_params.phy[EXT_PHY1].type == in bnx2x_link_settings_requested()
11310 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11315 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11317 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11325 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { in bnx2x_link_settings_requested()
11326 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11328 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11334 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11340 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { in bnx2x_link_settings_requested()
11341 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11343 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11345 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11351 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11357 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11359 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11361 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11367 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11373 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11375 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11377 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11379 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11385 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11391 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11393 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11395 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11398 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11400 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11402 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11407 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11413 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11415 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11417 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11423 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11429 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11431 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11433 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11436 } else if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11438 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11440 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11446 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11451 bp->link_params.req_line_speed[idx] = SPEED_20000; in bnx2x_link_settings_requested()
11457 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11459 bp->port.advertising[idx] = in bnx2x_link_settings_requested()
11460 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11464 bp->link_params.req_flow_ctrl[idx] = (link_config & in bnx2x_link_settings_requested()
11466 if (bp->link_params.req_flow_ctrl[idx] == in bnx2x_link_settings_requested()
11468 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) in bnx2x_link_settings_requested()
11469 bp->link_params.req_flow_ctrl[idx] = in bnx2x_link_settings_requested()
11476 bp->link_params.req_line_speed[idx], in bnx2x_link_settings_requested()
11477 bp->link_params.req_duplex[idx], in bnx2x_link_settings_requested()
11478 bp->link_params.req_flow_ctrl[idx], in bnx2x_link_settings_requested()
11479 bp->port.advertising[idx]); in bnx2x_link_settings_requested()
11497 bp->link_params.bp = bp; in bnx2x_get_port_hwinfo()
11498 bp->link_params.port = port; in bnx2x_get_port_hwinfo()
11500 bp->link_params.lane_config = in bnx2x_get_port_hwinfo()
11503 bp->link_params.speed_cap_mask[0] = in bnx2x_get_port_hwinfo()
11507 bp->link_params.speed_cap_mask[1] = in bnx2x_get_port_hwinfo()
11511 bp->port.link_config[0] = in bnx2x_get_port_hwinfo()
11514 bp->port.link_config[1] = in bnx2x_get_port_hwinfo()
11517 bp->link_params.multi_phy_config = in bnx2x_get_port_hwinfo()
11523 bp->wol = (!(bp->flags & NO_WOL_FLAG) && in bnx2x_get_port_hwinfo()
11528 bp->flags |= NO_ISCSI_FLAG; in bnx2x_get_port_hwinfo()
11531 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_port_hwinfo()
11534 bp->link_params.lane_config, in bnx2x_get_port_hwinfo()
11535 bp->link_params.speed_cap_mask[0], in bnx2x_get_port_hwinfo()
11536 bp->port.link_config[0]); in bnx2x_get_port_hwinfo()
11538 bp->link_params.switch_cfg = (bp->port.link_config[0] & in bnx2x_get_port_hwinfo()
11540 bnx2x_phy_probe(&bp->link_params); in bnx2x_get_port_hwinfo()
11541 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); in bnx2x_get_port_hwinfo()
11554 bp->mdio.prtad = bp->port.phy_addr; in bnx2x_get_port_hwinfo()
11558 bp->mdio.prtad = in bnx2x_get_port_hwinfo()
11567 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | in bnx2x_get_port_hwinfo()
11571 bp->link_params.eee_mode = 0; in bnx2x_get_port_hwinfo()
11583 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11588 bp->cnic_eth_dev.max_iscsi_conn = in bnx2x_get_iscsi_info()
11593 bp->cnic_eth_dev.max_iscsi_conn); in bnx2x_get_iscsi_info()
11596 * If maximum allowed number of connections is zero - in bnx2x_get_iscsi_info()
11599 if (!bp->cnic_eth_dev.max_iscsi_conn) in bnx2x_get_iscsi_info()
11600 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11606 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_ext_wwn_info()
11608 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_ext_wwn_info()
11612 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_ext_wwn_info()
11614 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_ext_wwn_info()
11669 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11674 bp->cnic_eth_dev.max_fcoe_conn = in bnx2x_get_fcoe_info()
11679 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; in bnx2x_get_fcoe_info()
11683 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; in bnx2x_get_fcoe_info()
11688 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_fcoe_info()
11692 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_fcoe_info()
11698 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_fcoe_info()
11702 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_fcoe_info()
11717 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); in bnx2x_get_fcoe_info()
11720 * If maximum allowed number of connections is zero - in bnx2x_get_fcoe_info()
11723 if (!bp->cnic_eth_dev.max_fcoe_conn) { in bnx2x_get_fcoe_info()
11724 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11725 eth_zero_addr(bp->fip_mac); in bnx2x_get_fcoe_info()
11745 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; in bnx2x_get_cnic_mac_hwinfo()
11746 u8 *fip_mac = bp->fip_mac; in bnx2x_get_cnic_mac_hwinfo()
11765 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11777 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11780 bp->mf_ext_config = cfg; in bnx2x_get_cnic_mac_hwinfo()
11785 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11792 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11799 /* If this is a storage-only interface, use SAN mac as in bnx2x_get_cnic_mac_hwinfo()
11804 eth_hw_addr_set(bp->dev, fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11821 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11827 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11828 eth_zero_addr(bp->fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11840 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11844 eth_hw_addr_random(bp->dev); in bnx2x_get_mac_hwinfo()
11851 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11861 eth_hw_addr_set(bp->dev, addr); in bnx2x_get_mac_hwinfo()
11871 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); in bnx2x_get_mac_hwinfo()
11872 bp->flags |= HAS_PHYS_PORT_ID; in bnx2x_get_mac_hwinfo()
11875 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_mac_hwinfo()
11877 if (!is_valid_ether_addr(bp->dev->dev_addr)) in bnx2x_get_mac_hwinfo()
11878 dev_err(&bp->pdev->dev, in bnx2x_get_mac_hwinfo()
11881 bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11916 bp->mf_mode = MULTI_FUNCTION_SI; in validate_set_si_mode()
11917 bp->mf_config[BP_VN(bp)] = in validate_set_si_mode()
11932 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11934 return -EINVAL; in bnx2x_get_hwinfo()
11943 bp->common.int_block = INT_BLOCK_HC; in bnx2x_get_hwinfo()
11945 bp->igu_dsb_id = DEF_SB_IGU_ID; in bnx2x_get_hwinfo()
11946 bp->igu_base_sb = 0; in bnx2x_get_hwinfo()
11948 bp->common.int_block = INT_BLOCK_IGU; in bnx2x_get_hwinfo()
11965 tout--; in bnx2x_get_hwinfo()
11970 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11974 return -EPERM; in bnx2x_get_hwinfo()
11980 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; in bnx2x_get_hwinfo()
11991 * set base FW non-default (fast path) status block id, this value is in bnx2x_get_hwinfo()
11996 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); in bnx2x_get_hwinfo()
11998 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of in bnx2x_get_hwinfo()
12002 bp->base_fw_ndsb = bp->igu_base_sb; in bnx2x_get_hwinfo()
12005 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, in bnx2x_get_hwinfo()
12006 bp->igu_sb_cnt, bp->base_fw_ndsb); in bnx2x_get_hwinfo()
12011 bp->mf_ov = 0; in bnx2x_get_hwinfo()
12012 bp->mf_mode = 0; in bnx2x_get_hwinfo()
12013 bp->mf_sub_mode = 0; in bnx2x_get_hwinfo()
12018 bp->common.shmem2_base, SHMEM2_RD(bp, size), in bnx2x_get_hwinfo()
12022 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); in bnx2x_get_hwinfo()
12024 bp->common.mf_cfg_base = bp->common.shmem_base + in bnx2x_get_hwinfo()
12031 * for Switch-Independent mode; in bnx2x_get_hwinfo()
12032 * OVLAN must be legal for Switch-Dependent mode in bnx2x_get_hwinfo()
12035 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
12051 bp->mf_mode = MULTI_FUNCTION_AFEX; in bnx2x_get_hwinfo()
12052 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12065 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12066 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
12072 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12073 bp->mf_sub_mode = SUB_MF_MODE_BD; in bnx2x_get_hwinfo()
12074 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12092 bp->dev->mtu = mtu_size; in bnx2x_get_hwinfo()
12096 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
12097 bp->mf_sub_mode = SUB_MF_MODE_UFP; in bnx2x_get_hwinfo()
12098 bp->mf_config[vn] = in bnx2x_get_hwinfo()
12103 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12112 bp->mf_sub_mode = in bnx2x_get_hwinfo()
12117 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12124 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
12132 switch (bp->mf_mode) { in bnx2x_get_hwinfo()
12137 bp->mf_ov = val; in bnx2x_get_hwinfo()
12138 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12141 func, bp->mf_ov, bp->mf_ov); in bnx2x_get_hwinfo()
12142 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || in bnx2x_get_hwinfo()
12143 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { in bnx2x_get_hwinfo()
12144 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12145 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", in bnx2x_get_hwinfo()
12147 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12149 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12152 return -EPERM; in bnx2x_get_hwinfo()
12159 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", in bnx2x_get_hwinfo()
12164 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
12167 return -EPERM; in bnx2x_get_hwinfo()
12178 !bp->path_has_ovlan && in bnx2x_get_hwinfo()
12180 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
12186 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
12192 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); in bnx2x_get_hwinfo()
12212 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); in bnx2x_read_fwinfo()
12214 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); in bnx2x_read_fwinfo()
12229 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { in bnx2x_read_fwinfo()
12230 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); in bnx2x_read_fwinfo()
12231 bp->fw_ver[kw_len] = ' '; in bnx2x_read_fwinfo()
12266 switch (bp->mf_mode) { in bnx2x_set_modes_bitmap()
12293 mutex_init(&bp->port.phy_mutex); in bnx2x_init_bp()
12294 mutex_init(&bp->fw_mb_mutex); in bnx2x_init_bp()
12295 mutex_init(&bp->drv_info_mutex); in bnx2x_init_bp()
12296 sema_init(&bp->stats_lock, 1); in bnx2x_init_bp()
12297 bp->drv_info_mng_owner = false; in bnx2x_init_bp()
12298 INIT_LIST_HEAD(&bp->vlan_reg); in bnx2x_init_bp()
12300 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); in bnx2x_init_bp()
12301 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); in bnx2x_init_bp()
12302 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); in bnx2x_init_bp()
12303 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); in bnx2x_init_bp()
12311 eth_hw_addr_set(bp->dev, zero_addr); in bnx2x_init_bp()
12327 bp->fw_seq = in bnx2x_init_bp()
12330 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); in bnx2x_init_bp()
12340 dev_err(&bp->pdev->dev, "FPGA detected\n"); in bnx2x_init_bp()
12343 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); in bnx2x_init_bp()
12345 bp->disable_tpa = disable_tpa; in bnx2x_init_bp()
12346 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); in bnx2x_init_bp()
12348 bp->disable_tpa |= is_kdump_kernel(); in bnx2x_init_bp()
12351 if (bp->disable_tpa) { in bnx2x_init_bp()
12352 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); in bnx2x_init_bp()
12353 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); in bnx2x_init_bp()
12357 bp->dropless_fc = false; in bnx2x_init_bp()
12359 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); in bnx2x_init_bp()
12361 bp->mrrs = mrrs; in bnx2x_init_bp()
12363 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; in bnx2x_init_bp()
12365 bp->rx_ring_size = MAX_RX_AVAIL; in bnx2x_init_bp()
12368 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12369 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12371 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; in bnx2x_init_bp()
12373 timer_setup(&bp->timer, bnx2x_timer, 0); in bnx2x_init_bp()
12374 bp->timer.expires = jiffies + bp->current_interval; in bnx2x_init_bp()
12389 bp->cnic_base_cl_id = FP_SB_MAX_E1x; in bnx2x_init_bp()
12391 bp->cnic_base_cl_id = FP_SB_MAX_E2; in bnx2x_init_bp()
12395 bp->max_cos = 1; in bnx2x_init_bp()
12397 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; in bnx2x_init_bp()
12399 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; in bnx2x_init_bp()
12401 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; in bnx2x_init_bp()
12405 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); in bnx2x_init_bp()
12407 /* We need at least one default status block for slow-path events, in bnx2x_init_bp()
12412 bp->min_msix_vec_cnt = 1; in bnx2x_init_bp()
12414 bp->min_msix_vec_cnt = 3; in bnx2x_init_bp()
12416 bp->min_msix_vec_cnt = 2; in bnx2x_init_bp()
12417 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); in bnx2x_init_bp()
12419 bp->dump_preset_idx = 1; in bnx2x_init_bp()
12438 bp->stats_init = true; in bnx2x_open()
12477 netdev_info(bp->dev, in bnx2x_open()
12484 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_open()
12489 return -EAGAIN; in bnx2x_open()
12494 bp->recovery_state = BNX2X_RECOVERY_DONE; in bnx2x_open()
12520 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12531 list_del(¤t_mcast_group->mcast_group_link); in bnx2x_free_mcast_macs_list()
12543 int mc_count = netdev_mc_count(bp->dev); in bnx2x_init_mcast_macs_list()
12546 INIT_LIST_HEAD(&p->mcast_list); in bnx2x_init_mcast_macs_list()
12547 netdev_for_each_mc_addr(ha, bp->dev) { in bnx2x_init_mcast_macs_list()
12555 return -ENOMEM; in bnx2x_init_mcast_macs_list()
12557 list_add(¤t_mcast_group->mcast_group_link, in bnx2x_init_mcast_macs_list()
12560 mc_mac = ¤t_mcast_group->mcast_elems[offset]; in bnx2x_init_mcast_macs_list()
12561 mc_mac->mac = bnx2x_mc_addr(ha); in bnx2x_init_mcast_macs_list()
12562 list_add_tail(&mc_mac->link, &p->mcast_list); in bnx2x_init_mcast_macs_list()
12567 p->mcast_list_len = mc_count; in bnx2x_init_mcast_macs_list()
12572 * bnx2x_set_uc_list - configure a new unicast MACs list.
12581 struct net_device *dev = bp->dev; in bnx2x_set_uc_list()
12583 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; in bnx2x_set_uc_list()
12596 if (rc == -EEXIST) { in bnx2x_set_uc_list()
12619 struct net_device *dev = bp->dev; in bnx2x_set_mc_list_e1x()
12623 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list_e1x()
12655 struct net_device *dev = bp->dev; in bnx2x_set_mc_list()
12658 /* On older adapters, we need to flush and re-add filters */ in bnx2x_set_mc_list()
12662 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list()
12688 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12693 if (bp->state != BNX2X_STATE_OPEN) { in bnx2x_set_rx_mode()
12694 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); in bnx2x_set_rx_mode()
12707 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); in bnx2x_set_rx_mode_inner()
12709 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12711 if (bp->dev->flags & IFF_PROMISC) { in bnx2x_set_rx_mode_inner()
12713 } else if ((bp->dev->flags & IFF_ALLMULTI) || in bnx2x_set_rx_mode_inner()
12714 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && in bnx2x_set_rx_mode_inner()
12724 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12727 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12737 bp->rx_mode = rx_mode; in bnx2x_set_rx_mode_inner()
12740 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_set_rx_mode_inner()
12743 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { in bnx2x_set_rx_mode_inner()
12744 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_set_rx_mode_inner()
12745 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12751 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12754 * the VF needs to release the bottom-half lock prior to the in bnx2x_set_rx_mode_inner()
12757 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12777 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); in bnx2x_mdio_read()
12801 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); in bnx2x_mdio_write()
12813 return -EAGAIN; in bnx2x_ioctl()
12820 mdio->phy_id, mdio->reg_num, mdio->val_in); in bnx2x_ioctl()
12821 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); in bnx2x_ioctl()
12833 if (!is_valid_ether_addr(dev->dev_addr)) { in bnx2x_validate_addr()
12834 BNX2X_ERR("Non-valid Ethernet address\n"); in bnx2x_validate_addr()
12835 return -EADDRNOTAVAIL; in bnx2x_validate_addr()
12845 if (!(bp->flags & HAS_PHYS_PORT_ID)) in bnx2x_get_phys_port_id()
12846 return -EOPNOTSUPP; in bnx2x_get_phys_port_id()
12848 ppid->id_len = sizeof(bp->phys_port_id); in bnx2x_get_phys_port_id()
12849 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); in bnx2x_get_phys_port_id()
12872 (skb_shinfo(skb)->gso_size > 9000) && in bnx2x_features_check()
12888 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, in __bnx2x_vlan_configure_vid()
12891 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); in __bnx2x_vlan_configure_vid()
12902 /* Configure all non-configured entries */ in bnx2x_vlan_configure_vid_list()
12903 list_for_each_entry(vlan, &bp->vlan_reg, link) { in bnx2x_vlan_configure_vid_list()
12904 if (vlan->hw) in bnx2x_vlan_configure_vid_list()
12907 if (bp->vlan_cnt >= bp->vlan_credit) in bnx2x_vlan_configure_vid_list()
12908 return -ENOBUFS; in bnx2x_vlan_configure_vid_list()
12910 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); in bnx2x_vlan_configure_vid_list()
12912 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); in bnx2x_vlan_configure_vid_list()
12916 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); in bnx2x_vlan_configure_vid_list()
12917 vlan->hw = true; in bnx2x_vlan_configure_vid_list()
12918 bp->vlan_cnt++; in bnx2x_vlan_configure_vid_list()
12930 if (bp->accept_any_vlan != need_accept_any_vlan) { in bnx2x_vlan_configure()
12931 bp->accept_any_vlan = need_accept_any_vlan; in bnx2x_vlan_configure()
12933 bp->accept_any_vlan ? "raised" : "cleared"); in bnx2x_vlan_configure()
12960 return -ENOMEM; in bnx2x_vlan_rx_add_vid()
12962 vlan->vid = vid; in bnx2x_vlan_rx_add_vid()
12963 vlan->hw = false; in bnx2x_vlan_rx_add_vid()
12964 list_add_tail(&vlan->link, &bp->vlan_reg); in bnx2x_vlan_rx_add_vid()
12981 list_for_each_entry(vlan, &bp->vlan_reg, link) in bnx2x_vlan_rx_kill_vid()
12982 if (vlan->vid == vid) { in bnx2x_vlan_rx_kill_vid()
12988 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); in bnx2x_vlan_rx_kill_vid()
12989 return -EINVAL; in bnx2x_vlan_rx_kill_vid()
12992 if (netif_running(dev) && vlan->hw) { in bnx2x_vlan_rx_kill_vid()
12995 bp->vlan_cnt--; in bnx2x_vlan_rx_kill_vid()
12998 list_del(&vlan->link); in bnx2x_vlan_rx_kill_vid()
13042 if (bp->flags & AER_ENABLED) { in bnx2x_disable_pcie_error_reporting()
13043 pci_disable_pcie_error_reporting(bp->pdev); in bnx2x_disable_pcie_error_reporting()
13044 bp->flags &= ~AER_ENABLED; in bnx2x_disable_pcie_error_reporting()
13057 SET_NETDEV_DEV(dev, &pdev->dev); in bnx2x_init_dev()
13059 bp->dev = dev; in bnx2x_init_dev()
13060 bp->pdev = pdev; in bnx2x_init_dev()
13064 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13070 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13072 rc = -ENODEV; in bnx2x_init_dev()
13077 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); in bnx2x_init_dev()
13078 rc = -ENODEV; in bnx2x_init_dev()
13086 rc = -ENODEV; in bnx2x_init_dev()
13090 if (atomic_read(&pdev->enable_cnt) == 1) { in bnx2x_init_dev()
13093 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13103 if (!pdev->pm_cap) { in bnx2x_init_dev()
13104 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13106 rc = -EIO; in bnx2x_init_dev()
13112 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); in bnx2x_init_dev()
13113 rc = -EIO; in bnx2x_init_dev()
13117 rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64)); in bnx2x_init_dev()
13119 dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n"); in bnx2x_init_dev()
13123 dev->mem_start = pci_resource_start(pdev, 0); in bnx2x_init_dev()
13124 dev->base_addr = dev->mem_start; in bnx2x_init_dev()
13125 dev->mem_end = pci_resource_end(pdev, 0); in bnx2x_init_dev()
13127 dev->irq = pdev->irq; in bnx2x_init_dev()
13129 bp->regview = pci_ioremap_bar(pdev, 0); in bnx2x_init_dev()
13130 if (!bp->regview) { in bnx2x_init_dev()
13131 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
13133 rc = -ENOMEM; in bnx2x_init_dev()
13143 bp->pf_num = PCI_FUNC(pdev->devfn); in bnx2x_init_dev()
13146 pci_read_config_dword(bp->pdev, in bnx2x_init_dev()
13148 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> in bnx2x_init_dev()
13151 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); in bnx2x_init_dev()
13154 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_init_dev()
13158 pdev->needs_freset = 1; in bnx2x_init_dev()
13163 bp->flags |= AER_ENABLED; in bnx2x_init_dev()
13184 /* Enable internal target-read (in case we are probed after PF in bnx2x_init_dev()
13193 dev->watchdog_timeo = TX_TIMEOUT; in bnx2x_init_dev()
13195 dev->netdev_ops = &bnx2x_netdev_ops; in bnx2x_init_dev()
13198 dev->priv_flags |= IFF_UNICAST_FLT; in bnx2x_init_dev()
13200 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | in bnx2x_init_dev()
13205 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | in bnx2x_init_dev()
13211 dev->hw_enc_features = in bnx2x_init_dev()
13219 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | in bnx2x_init_dev()
13223 dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels; in bnx2x_init_dev()
13226 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | in bnx2x_init_dev()
13231 bp->accept_any_vlan = true; in bnx2x_init_dev()
13233 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; in bnx2x_init_dev()
13239 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; in bnx2x_init_dev()
13240 dev->features |= NETIF_F_HIGHDMA; in bnx2x_init_dev()
13241 if (dev->features & NETIF_F_LRO) in bnx2x_init_dev()
13242 dev->features &= ~NETIF_F_GRO_HW; in bnx2x_init_dev()
13245 dev->hw_features |= NETIF_F_LOOPBACK; in bnx2x_init_dev()
13248 dev->dcbnl_ops = &bnx2x_dcbnl_ops; in bnx2x_init_dev()
13251 /* MTU range, 46 - 9600 */ in bnx2x_init_dev()
13252 dev->min_mtu = ETH_MIN_PACKET_SIZE; in bnx2x_init_dev()
13253 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; in bnx2x_init_dev()
13256 bp->mdio.prtad = MDIO_PRTAD_NONE; in bnx2x_init_dev()
13257 bp->mdio.mmds = 0; in bnx2x_init_dev()
13258 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; in bnx2x_init_dev()
13259 bp->mdio.dev = dev; in bnx2x_init_dev()
13260 bp->mdio.mdio_read = bnx2x_mdio_read; in bnx2x_init_dev()
13261 bp->mdio.mdio_write = bnx2x_mdio_write; in bnx2x_init_dev()
13266 if (atomic_read(&pdev->enable_cnt) == 1) in bnx2x_init_dev()
13278 const struct firmware *firmware = bp->firmware; in bnx2x_check_firmware()
13286 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { in bnx2x_check_firmware()
13288 return -EINVAL; in bnx2x_check_firmware()
13291 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; in bnx2x_check_firmware()
13299 if (offset + len > firmware->size) { in bnx2x_check_firmware()
13301 return -EINVAL; in bnx2x_check_firmware()
13306 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); in bnx2x_check_firmware()
13307 ops_offsets = (__force __be16 *)(firmware->data + offset); in bnx2x_check_firmware()
13308 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); in bnx2x_check_firmware()
13310 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { in bnx2x_check_firmware()
13313 return -EINVAL; in bnx2x_check_firmware()
13318 offset = be32_to_cpu(fw_hdr->fw_version.offset); in bnx2x_check_firmware()
13319 fw_ver = firmware->data + offset; in bnx2x_check_firmware()
13320 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || in bnx2x_check_firmware()
13321 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { in bnx2x_check_firmware()
13324 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); in bnx2x_check_firmware()
13325 return -EINVAL; in bnx2x_check_firmware()
13394 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13395 bp->arr = kmalloc(len, GFP_KERNEL); \
13396 if (!bp->arr) \
13398 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13399 (u8 *)bp->arr, len); \
13408 if (bp->firmware) in bnx2x_init_firmware()
13422 return -EINVAL; in bnx2x_init_firmware()
13427 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); in bnx2x_init_firmware()
13432 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); in bnx2x_init_firmware()
13437 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; in bnx2x_init_firmware()
13439 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; in bnx2x_init_firmware()
13440 bp->fw_rev = BCM_5710_FW_REVISION_VERSION; in bnx2x_init_firmware()
13443 bp->fw_major = BCM_5710_FW_MAJOR_VERSION; in bnx2x_init_firmware()
13444 bp->fw_minor = BCM_5710_FW_MINOR_VERSION; in bnx2x_init_firmware()
13445 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; in bnx2x_init_firmware()
13453 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; in bnx2x_init_firmware()
13457 rc = -ENOMEM; in bnx2x_init_firmware()
13468 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13469 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); in bnx2x_init_firmware()
13470 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13471 be32_to_cpu(fw_hdr->tsem_pram_data.offset); in bnx2x_init_firmware()
13472 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13473 be32_to_cpu(fw_hdr->usem_int_table_data.offset); in bnx2x_init_firmware()
13474 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13475 be32_to_cpu(fw_hdr->usem_pram_data.offset); in bnx2x_init_firmware()
13476 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13477 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); in bnx2x_init_firmware()
13478 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13479 be32_to_cpu(fw_hdr->xsem_pram_data.offset); in bnx2x_init_firmware()
13480 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13481 be32_to_cpu(fw_hdr->csem_int_table_data.offset); in bnx2x_init_firmware()
13482 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13483 be32_to_cpu(fw_hdr->csem_pram_data.offset); in bnx2x_init_firmware()
13490 kfree(bp->init_ops_offsets); in bnx2x_init_firmware()
13492 kfree(bp->init_ops); in bnx2x_init_firmware()
13494 kfree(bp->init_data); in bnx2x_init_firmware()
13496 release_firmware(bp->firmware); in bnx2x_init_firmware()
13497 bp->firmware = NULL; in bnx2x_init_firmware()
13504 kfree(bp->init_ops_offsets); in bnx2x_release_firmware()
13505 kfree(bp->init_ops); in bnx2x_release_firmware()
13506 kfree(bp->init_data); in bnx2x_release_firmware()
13507 release_firmware(bp->firmware); in bnx2x_release_firmware()
13508 bp->firmware = NULL; in bnx2x_release_firmware()
13533 bnx2x_init_func_obj(bp, &bp->func_obj, in bnx2x__init_func_obj()
13541 /* must be called after sriov-enable */
13556 * bnx2x_get_num_non_def_sbs - return the number of none default SBs
13567 * If MSI-X is not supported - return number of SBs needed to support in bnx2x_get_num_non_def_sbs()
13570 if (!pdev->msix_cap) { in bnx2x_get_num_non_def_sbs()
13571 dev_info(&pdev->dev, "no msix capability found\n"); in bnx2x_get_num_non_def_sbs()
13574 dev_info(&pdev->dev, "msix capability found\n"); in bnx2x_get_num_non_def_sbs()
13583 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); in bnx2x_get_num_non_def_sbs()
13620 return -ENODEV; in set_max_cos_est()
13660 func_params.f_obj = &bp->func_obj; in bnx2x_send_update_drift_ramrod()
13664 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; in bnx2x_send_update_drift_ramrod()
13665 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; in bnx2x_send_update_drift_ramrod()
13666 set_timesync_params->add_sub_drift_adjust_value = in bnx2x_send_update_drift_ramrod()
13668 set_timesync_params->drift_adjust_value = best_val; in bnx2x_send_update_drift_ramrod()
13669 set_timesync_params->drift_adjust_period = best_period; in bnx2x_send_update_drift_ramrod()
13684 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjfreq()
13687 return -ENETDOWN; in bnx2x_ptp_adjfreq()
13691 ppb = -ppb; in bnx2x_ptp_adjfreq()
13711 dif1 = ppb - (val * 1000000 / period1); in bnx2x_ptp_adjfreq()
13715 dif1 = -dif1; in bnx2x_ptp_adjfreq()
13716 dif2 = ppb - (val * 1000000 / period2); in bnx2x_ptp_adjfreq()
13718 dif2 = -dif2; in bnx2x_ptp_adjfreq()
13733 return -EFAULT; in bnx2x_ptp_adjfreq()
13746 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjtime()
13749 return -ENETDOWN; in bnx2x_ptp_adjtime()
13754 timecounter_adjtime(&bp->timecounter, delta); in bnx2x_ptp_adjtime()
13764 if (!netif_running(bp->dev)) { in bnx2x_ptp_gettime()
13767 return -ENETDOWN; in bnx2x_ptp_gettime()
13770 ns = timecounter_read(&bp->timecounter); in bnx2x_ptp_gettime()
13785 if (!netif_running(bp->dev)) { in bnx2x_ptp_settime()
13788 return -ENETDOWN; in bnx2x_ptp_settime()
13795 /* Re-init the timecounter */ in bnx2x_ptp_settime()
13796 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); in bnx2x_ptp_settime()
13808 return -ENOTSUPP; in bnx2x_ptp_enable()
13814 bp->ptp_clock_info.owner = THIS_MODULE; in bnx2x_register_phc()
13815 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); in bnx2x_register_phc()
13816 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ in bnx2x_register_phc()
13817 bp->ptp_clock_info.n_alarm = 0; in bnx2x_register_phc()
13818 bp->ptp_clock_info.n_ext_ts = 0; in bnx2x_register_phc()
13819 bp->ptp_clock_info.n_per_out = 0; in bnx2x_register_phc()
13820 bp->ptp_clock_info.pps = 0; in bnx2x_register_phc()
13821 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; in bnx2x_register_phc()
13822 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; in bnx2x_register_phc()
13823 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; in bnx2x_register_phc()
13824 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; in bnx2x_register_phc()
13825 bp->ptp_clock_info.enable = bnx2x_ptp_enable; in bnx2x_register_phc()
13827 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); in bnx2x_register_phc()
13828 if (IS_ERR(bp->ptp_clock)) { in bnx2x_register_phc()
13829 bp->ptp_clock = NULL; in bnx2x_register_phc()
13846 * to forget previously living interfaces, allowing a proper re-load. in bnx2x_init_one()
13861 * initialization of bp->max_cos based on the chip versions AND chip in bnx2x_init_one()
13864 max_cos_est = set_max_cos_est(ent->driver_data); in bnx2x_init_one()
13867 is_vf = set_is_vf(ent->driver_data); in bnx2x_init_one()
13876 rss_count = max_non_def_sbs - cnic_cnt; in bnx2x_init_one()
13879 return -EINVAL; in bnx2x_init_one()
13892 return -ENOMEM; in bnx2x_init_one()
13896 bp->flags = 0; in bnx2x_init_one()
13898 bp->flags |= IS_VF_FLAG; in bnx2x_init_one()
13900 bp->igu_sb_cnt = max_non_def_sbs; in bnx2x_init_one()
13901 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; in bnx2x_init_one()
13902 bp->msg_enable = debug; in bnx2x_init_one()
13903 bp->cnic_support = cnic_cnt; in bnx2x_init_one()
13904 bp->cnic_probe = bnx2x_cnic_probe; in bnx2x_init_one()
13908 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); in bnx2x_init_one()
13925 /* Map doorbells here as we need the real value of bp->max_cos which in bnx2x_init_one()
13930 bp->doorbells = bnx2x_vf_doorbells(bp); in bnx2x_init_one()
13937 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13939 rc = -ENOMEM; in bnx2x_init_one()
13942 bp->doorbells = ioremap(pci_resource_start(pdev, 2), in bnx2x_init_one()
13945 if (!bp->doorbells) { in bnx2x_init_one()
13946 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13948 rc = -ENOMEM; in bnx2x_init_one()
13959 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { in bnx2x_init_one()
13960 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; in bnx2x_init_one()
13961 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; in bnx2x_init_one()
13972 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); in bnx2x_init_one()
13973 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); in bnx2x_init_one()
13977 bp->flags |= NO_FCOE_FLAG; in bnx2x_init_one()
13979 /* Set bp->num_queues for MSI-X mode*/ in bnx2x_init_one()
13982 /* Configure interrupt mode: try to enable MSI-X/MSI if in bnx2x_init_one()
13987 dev_err(&pdev->dev, "Cannot set interrupts\n"); in bnx2x_init_one()
13995 dev_err(&pdev->dev, "Cannot register net device\n"); in bnx2x_init_one()
13998 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); in bnx2x_init_one()
14003 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in bnx2x_init_one()
14007 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", in bnx2x_init_one()
14008 board_info[ent->driver_data].name, in bnx2x_init_one()
14010 dev->base_addr, bp->pdev->irq, dev->dev_addr); in bnx2x_init_one()
14011 pcie_print_link_status(bp->pdev); in bnx2x_init_one()
14024 if (bp->regview) in bnx2x_init_one()
14025 iounmap(bp->regview); in bnx2x_init_one()
14027 if (IS_PF(bp) && bp->doorbells) in bnx2x_init_one()
14028 iounmap(bp->doorbells); in bnx2x_init_one()
14032 if (atomic_read(&pdev->enable_cnt) == 1) in bnx2x_init_one()
14048 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in __bnx2x_remove()
14059 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) in __bnx2x_remove()
14062 /* Close the interface - either directly or implicitly */ in __bnx2x_remove()
14084 /* Disable MSI/MSI-X */ in __bnx2x_remove()
14092 cancel_delayed_work_sync(&bp->sp_rtnl_task); in __bnx2x_remove()
14100 pci_wake_from_d3(pdev, bp->wol); in __bnx2x_remove()
14106 if (bp->regview) in __bnx2x_remove()
14107 iounmap(bp->regview); in __bnx2x_remove()
14113 if (bp->doorbells) in __bnx2x_remove()
14114 iounmap(bp->doorbells); in __bnx2x_remove()
14124 if (atomic_read(&pdev->enable_cnt) == 1) in __bnx2x_remove()
14137 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); in bnx2x_remove_one()
14147 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; in bnx2x_eeh_nic_unload()
14149 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_eeh_nic_unload()
14156 netdev_reset_tc(bp->dev); in bnx2x_eeh_nic_unload()
14158 del_timer_sync(&bp->timer); in bnx2x_eeh_nic_unload()
14159 cancel_delayed_work_sync(&bp->sp_task); in bnx2x_eeh_nic_unload()
14160 cancel_delayed_work_sync(&bp->period_task); in bnx2x_eeh_nic_unload()
14162 if (!down_timeout(&bp->stats_lock, HZ / 10)) { in bnx2x_eeh_nic_unload()
14163 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_eeh_nic_unload()
14164 up(&bp->stats_lock); in bnx2x_eeh_nic_unload()
14169 netif_carrier_off(bp->dev); in bnx2x_eeh_nic_unload()
14175 * bnx2x_io_error_detected - called when PCI error is detected
14213 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14216 * Restart the card from scratch, as if from a cold-boot.
14227 dev_err(&pdev->dev, in bnx2x_io_slot_reset()
14228 "Cannot re-enable PCI device after reset\n"); in bnx2x_io_slot_reset()
14241 BNX2X_ERR("IO slot reset --> driver unload\n"); in bnx2x_io_slot_reset()
14270 bp->sp_state = 0; in bnx2x_io_slot_reset()
14271 bp->port.pmf = 0; in bnx2x_io_slot_reset()
14281 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); in bnx2x_io_slot_reset()
14285 bp->state = BNX2X_STATE_CLOSED; in bnx2x_io_slot_reset()
14294 * bnx2x_io_resume - called when traffic can start flowing again
14305 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { in bnx2x_io_resume()
14306 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); in bnx2x_io_resume()
14312 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_io_resume()
14372 return -ENOMEM; in bnx2x_init()
14378 return -ENOMEM; in bnx2x_init()
14417 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14421 * Return 0 if success, -ENODEV if ramrod doesn't return.
14428 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, in bnx2x_set_iscsi_eth_mac_addr()
14429 &bp->iscsi_l2_mac_obj, true, in bnx2x_set_iscsi_eth_mac_addr()
14440 if (unlikely(bp->panic)) in bnx2x_cnic_sp_post()
14444 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14445 BUG_ON(bp->cnic_spq_pending < count); in bnx2x_cnic_sp_post()
14446 bp->cnic_spq_pending -= count; in bnx2x_cnic_sp_post()
14448 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { in bnx2x_cnic_sp_post()
14449 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) in bnx2x_cnic_sp_post()
14452 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) in bnx2x_cnic_sp_post()
14462 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - in bnx2x_cnic_sp_post()
14465 &bp->context[cxt_index]. in bnx2x_cnic_sp_post()
14478 if (!atomic_read(&bp->cq_spq_left)) in bnx2x_cnic_sp_post()
14481 atomic_dec(&bp->cq_spq_left); in bnx2x_cnic_sp_post()
14483 if (!atomic_read(&bp->eq_spq_left)) in bnx2x_cnic_sp_post()
14486 atomic_dec(&bp->eq_spq_left); in bnx2x_cnic_sp_post()
14489 if (bp->cnic_spq_pending >= in bnx2x_cnic_sp_post()
14490 bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_post()
14493 bp->cnic_spq_pending++; in bnx2x_cnic_sp_post()
14501 *spe = *bp->cnic_kwq_cons; in bnx2x_cnic_sp_post()
14504 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); in bnx2x_cnic_sp_post()
14506 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) in bnx2x_cnic_sp_post()
14507 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_cnic_sp_post()
14509 bp->cnic_kwq_cons++; in bnx2x_cnic_sp_post()
14512 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14522 if (unlikely(bp->panic)) { in bnx2x_cnic_sp_queue()
14524 return -EIO; in bnx2x_cnic_sp_queue()
14528 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && in bnx2x_cnic_sp_queue()
14529 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_cnic_sp_queue()
14531 return -EAGAIN; in bnx2x_cnic_sp_queue()
14534 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14539 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) in bnx2x_cnic_sp_queue()
14542 *bp->cnic_kwq_prod = *spe; in bnx2x_cnic_sp_queue()
14544 bp->cnic_kwq_pending++; in bnx2x_cnic_sp_queue()
14547 spe->hdr.conn_and_cmd_data, spe->hdr.type, in bnx2x_cnic_sp_queue()
14548 spe->data.update_data_addr.hi, in bnx2x_cnic_sp_queue()
14549 spe->data.update_data_addr.lo, in bnx2x_cnic_sp_queue()
14550 bp->cnic_kwq_pending); in bnx2x_cnic_sp_queue()
14552 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) in bnx2x_cnic_sp_queue()
14553 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_cnic_sp_queue()
14555 bp->cnic_kwq_prod++; in bnx2x_cnic_sp_queue()
14558 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14560 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_queue()
14571 mutex_lock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14572 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2x_cnic_ctl_send()
14573 lockdep_is_held(&bp->cnic_mutex)); in bnx2x_cnic_ctl_send()
14575 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send()
14576 mutex_unlock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14587 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_cnic_ctl_send_bh()
14589 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send_bh()
14634 * multicasts (in non-promiscuous mode only one Queue per in bnx2x_set_iscsi_eth_rx_mode()
14644 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14649 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14651 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_set_iscsi_eth_rx_mode()
14652 set_bit(sched_state, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14665 switch (ctl->cmd) { in bnx2x_drv_ctl()
14667 u32 index = ctl->data.io.offset; in bnx2x_drv_ctl()
14668 dma_addr_t addr = ctl->data.io.dma_addr; in bnx2x_drv_ctl()
14675 int count = ctl->data.credit.credit_count; in bnx2x_drv_ctl()
14683 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_drv_ctl()
14687 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14688 cp->iscsi_l2_client_id, in bnx2x_drv_ctl()
14689 cp->iscsi_l2_cid, BP_FUNC(bp), in bnx2x_drv_ctl()
14693 &bp->sp_state, BNX2X_OBJ_TYPE_RX, in bnx2x_drv_ctl()
14694 &bp->macs_pool); in bnx2x_drv_ctl()
14738 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14743 int count = ctl->data.credit.credit_count; in bnx2x_drv_ctl()
14746 atomic_add(count, &bp->cq_spq_left); in bnx2x_drv_ctl()
14751 int ulp_type = ctl->data.register_data.ulp_type; in bnx2x_drv_ctl()
14771 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) in bnx2x_drv_ctl()
14774 /* if reached here - should write fcoe capabilities */ in bnx2x_drv_ctl()
14780 host_addr = (u32 *) &(ctl->data.register_data. in bnx2x_drv_ctl()
14792 int ulp_type = ctl->data.ulp_type; in bnx2x_drv_ctl()
14810 BNX2X_ERR("unknown command %x\n", ctl->cmd); in bnx2x_drv_ctl()
14811 rc = -EINVAL; in bnx2x_drv_ctl()
14814 /* For storage-only interfaces, change driver state */ in bnx2x_drv_ctl()
14816 switch (ctl->drv_state) { in bnx2x_drv_ctl()
14832 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); in bnx2x_drv_ctl()
14845 int rc = -EINVAL; in bnx2x_get_fc_npiv()
14851 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); in bnx2x_get_fc_npiv()
14861 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); in bnx2x_get_fc_npiv()
14864 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); in bnx2x_get_fc_npiv()
14868 BNX2X_ERR("Failed to read FC-NPIV table\n"); in bnx2x_get_fc_npiv()
14875 entries = tbl->fc_npiv_cfg.num_of_npiv; in bnx2x_get_fc_npiv()
14877 tbl->fc_npiv_cfg.num_of_npiv = entries; in bnx2x_get_fc_npiv()
14879 if (!tbl->fc_npiv_cfg.num_of_npiv) { in bnx2x_get_fc_npiv()
14881 "No FC-NPIV table [valid, simply not present]\n"); in bnx2x_get_fc_npiv()
14883 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { in bnx2x_get_fc_npiv()
14884 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", in bnx2x_get_fc_npiv()
14885 tbl->fc_npiv_cfg.num_of_npiv); in bnx2x_get_fc_npiv()
14889 tbl->fc_npiv_cfg.num_of_npiv); in bnx2x_get_fc_npiv()
14892 /* Copy the data into cnic-provided struct */ in bnx2x_get_fc_npiv()
14893 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; in bnx2x_get_fc_npiv()
14894 for (i = 0; i < cnic_tbl->count; i++) { in bnx2x_get_fc_npiv()
14895 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); in bnx2x_get_fc_npiv()
14896 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); in bnx2x_get_fc_npiv()
14907 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_irq_info()
14909 if (bp->flags & USING_MSIX_FLAG) { in bnx2x_setup_cnic_irq_info()
14910 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; in bnx2x_setup_cnic_irq_info()
14911 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2x_setup_cnic_irq_info()
14912 cp->irq_arr[0].vector = bp->msix_table[1].vector; in bnx2x_setup_cnic_irq_info()
14914 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; in bnx2x_setup_cnic_irq_info()
14915 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2x_setup_cnic_irq_info()
14918 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; in bnx2x_setup_cnic_irq_info()
14920 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; in bnx2x_setup_cnic_irq_info()
14922 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14923 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14924 cp->irq_arr[1].status_blk = bp->def_status_blk; in bnx2x_setup_cnic_irq_info()
14925 cp->irq_arr[1].status_blk_num = DEF_SB_ID; in bnx2x_setup_cnic_irq_info()
14926 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; in bnx2x_setup_cnic_irq_info()
14928 cp->num_irq = 2; in bnx2x_setup_cnic_irq_info()
14933 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_info()
14935 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_setup_cnic_info()
14937 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_setup_cnic_info()
14938 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_setup_cnic_info()
14939 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_setup_cnic_info()
14941 …P(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp-… in bnx2x_setup_cnic_info()
14942 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, in bnx2x_setup_cnic_info()
14943 cp->iscsi_l2_cid); in bnx2x_setup_cnic_info()
14946 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; in bnx2x_setup_cnic_info()
14953 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_register_cnic()
14960 return -EINVAL; in bnx2x_register_cnic()
14965 return -EOPNOTSUPP; in bnx2x_register_cnic()
14971 BNX2X_ERR("CNIC-related load failed\n"); in bnx2x_register_cnic()
14976 bp->cnic_enabled = true; in bnx2x_register_cnic()
14978 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); in bnx2x_register_cnic()
14979 if (!bp->cnic_kwq) in bnx2x_register_cnic()
14980 return -ENOMEM; in bnx2x_register_cnic()
14982 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_register_cnic()
14983 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_register_cnic()
14984 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; in bnx2x_register_cnic()
14986 bp->cnic_spq_pending = 0; in bnx2x_register_cnic()
14987 bp->cnic_kwq_pending = 0; in bnx2x_register_cnic()
14989 bp->cnic_data = data; in bnx2x_register_cnic()
14991 cp->num_irq = 0; in bnx2x_register_cnic()
14992 cp->drv_state |= CNIC_DRV_STATE_REGD; in bnx2x_register_cnic()
14993 cp->iro_arr = bp->iro_arr; in bnx2x_register_cnic()
14997 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2x_register_cnic()
15008 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_unregister_cnic()
15010 mutex_lock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
15011 cp->drv_state = 0; in bnx2x_unregister_cnic()
15012 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2x_unregister_cnic()
15013 mutex_unlock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
15015 bp->cnic_enabled = false; in bnx2x_unregister_cnic()
15016 kfree(bp->cnic_kwq); in bnx2x_unregister_cnic()
15017 bp->cnic_kwq = NULL; in bnx2x_unregister_cnic()
15025 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_cnic_probe()
15027 /* If both iSCSI and FCoE are disabled - return NULL in in bnx2x_cnic_probe()
15034 cp->drv_owner = THIS_MODULE; in bnx2x_cnic_probe()
15035 cp->chip_id = CHIP_ID(bp); in bnx2x_cnic_probe()
15036 cp->pdev = bp->pdev; in bnx2x_cnic_probe()
15037 cp->io_base = bp->regview; in bnx2x_cnic_probe()
15038 cp->io_base2 = bp->doorbells; in bnx2x_cnic_probe()
15039 cp->max_kwqe_pending = 8; in bnx2x_cnic_probe()
15040 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; in bnx2x_cnic_probe()
15041 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_cnic_probe()
15043 cp->ctx_tbl_len = CNIC_ILT_LINES; in bnx2x_cnic_probe()
15044 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_cnic_probe()
15045 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; in bnx2x_cnic_probe()
15046 cp->drv_ctl = bnx2x_drv_ctl; in bnx2x_cnic_probe()
15047 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; in bnx2x_cnic_probe()
15048 cp->drv_register_cnic = bnx2x_register_cnic; in bnx2x_cnic_probe()
15049 cp->drv_unregister_cnic = bnx2x_unregister_cnic; in bnx2x_cnic_probe()
15050 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_cnic_probe()
15051 cp->iscsi_l2_client_id = in bnx2x_cnic_probe()
15053 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_cnic_probe()
15056 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; in bnx2x_cnic_probe()
15059 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; in bnx2x_cnic_probe()
15062 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; in bnx2x_cnic_probe()
15066 cp->ctx_blk_size, in bnx2x_cnic_probe()
15067 cp->ctx_tbl_offset, in bnx2x_cnic_probe()
15068 cp->ctx_tbl_len, in bnx2x_cnic_probe()
15069 cp->starting_cid); in bnx2x_cnic_probe()
15075 struct bnx2x *bp = fp->bp; in bnx2x_rx_ustorm_prods_offset()
15081 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); in bnx2x_rx_ustorm_prods_offset()
15083 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); in bnx2x_rx_ustorm_prods_offset()
15090 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15098 return -1; in bnx2x_pretend_func()
15118 * still not complete, may indicate an error state - bail out then. in bnx2x_ptp_task()
15141 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_ptp_task()
15145 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); in bnx2x_ptp_task()
15153 bp->eth_stats.ptp_skip_tx_ts++; in bnx2x_ptp_task()
15156 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_ptp_task()
15157 bp->ptp_tx_skb = NULL; in bnx2x_ptp_task()
15175 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_set_rx_ts()
15177 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); in bnx2x_set_rx_ts()
15203 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); in bnx2x_init_cyclecounter()
15204 bp->cyclecounter.read = bnx2x_cyclecounter_read; in bnx2x_init_cyclecounter()
15205 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); in bnx2x_init_cyclecounter()
15206 bp->cyclecounter.shift = 0; in bnx2x_init_cyclecounter()
15207 bp->cyclecounter.mult = 1; in bnx2x_init_cyclecounter()
15220 func_params.f_obj = &bp->func_obj; in bnx2x_send_reset_timesync_ramrod()
15224 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; in bnx2x_send_reset_timesync_ramrod()
15225 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; in bnx2x_send_reset_timesync_ramrod()
15246 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_enable_ptp_packets()
15281 if (!bp->hwtstamp_ioctl_called) in bnx2x_configure_ptp_filters()
15288 switch (bp->tx_type) { in bnx2x_configure_ptp_filters()
15290 bp->flags |= TX_TIMESTAMPING_EN; in bnx2x_configure_ptp_filters()
15296 BNX2X_ERR("One-step timestamping is not supported\n"); in bnx2x_configure_ptp_filters()
15297 return -ERANGE; in bnx2x_configure_ptp_filters()
15304 switch (bp->rx_filter) { in bnx2x_configure_ptp_filters()
15310 bp->rx_filter = HWTSTAMP_FILTER_NONE; in bnx2x_configure_ptp_filters()
15315 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in bnx2x_configure_ptp_filters()
15323 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in bnx2x_configure_ptp_filters()
15331 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in bnx2x_configure_ptp_filters()
15340 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in bnx2x_configure_ptp_filters()
15366 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) in bnx2x_hwtstamp_ioctl()
15367 return -EFAULT; in bnx2x_hwtstamp_ioctl()
15372 bp->hwtstamp_ioctl_called = true; in bnx2x_hwtstamp_ioctl()
15373 bp->tx_type = config.tx_type; in bnx2x_hwtstamp_ioctl()
15374 bp->rx_filter = config.rx_filter; in bnx2x_hwtstamp_ioctl()
15380 config.rx_filter = bp->rx_filter; in bnx2x_hwtstamp_ioctl()
15382 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? in bnx2x_hwtstamp_ioctl()
15383 -EFAULT : 0; in bnx2x_hwtstamp_ioctl()
15392 /* Reset PTP event detection rules - will be configured in the IOCTL */ in bnx2x_configure_ptp()
15402 /* Disable PTP packets to host - will be configured in the IOCTL*/ in bnx2x_configure_ptp()
15410 /* Enable the free-running counter */ in bnx2x_configure_ptp()
15419 return -EFAULT; in bnx2x_configure_ptp()
15431 /* Called during load, to initialize PTP-related stuff */
15444 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); in bnx2x_init_ptp()
15450 if (!bp->timecounter_init_done) { in bnx2x_init_ptp()
15452 timecounter_init(&bp->timecounter, &bp->cyclecounter, in bnx2x_init_ptp()
15454 bp->timecounter_init_done = true; in bnx2x_init_ptp()