134 	ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);  in atl2_set_multi()
137 	ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);  in atl2_set_multi()
172 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);  in atl2_configure()
179 	ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);  in atl2_configure()
182 	ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);  in atl2_configure()
185 	ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,  in atl2_configure()
189 	ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,  in atl2_configure()
191 	ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,  in atl2_configure()
193 	ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,  in atl2_configure()
216 	ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);  in atl2_configure()
226 	ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);  in atl2_configure()
230 	ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);  in atl2_configure()
236 	ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +  in atl2_configure()
240 	ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);  in atl2_configure()
261 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);  in atl2_configure()
262 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);  in atl2_configure()
328 	ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);  in atl2_irq_enable()
338     ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);  in atl2_irq_disable()
364 	ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);  in atl2_vlan_mode()
598 	ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);  in atl2_intr()
603 			ATL2_WRITE_REG(hw, REG_ISR, 0);  in atl2_intr()
604 			ATL2_WRITE_REG(hw, REG_IMR, 0);  in atl2_intr()
613 		ATL2_WRITE_REG(hw, REG_ISR, 0);  in atl2_intr()
614 		ATL2_WRITE_REG(hw, REG_IMR, 0);  in atl2_intr()
635 	ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);  in atl2_intr()
723 	ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,  in atl2_open()
910 	ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN +  in atl2_change_mtu()
1078 	ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |  in atl2_up()
1141 	ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);  in atl2_setup_mac_ctrl()
1161 			ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);  in atl2_check_link()
1218 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);  in atl2_check_link()
1537 		ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);  in atl2_suspend()
1554 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);  in atl2_suspend()
1559 		ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);  in atl2_suspend()
1562 		ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);  in atl2_suspend()
1571 		ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);  in atl2_suspend()
1572 		ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);  in atl2_suspend()
1577 		ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);  in atl2_suspend()
1580 		ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);  in atl2_suspend()
1591 	ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);  in atl2_suspend()
1596 	ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);  in atl2_suspend()
1599 	ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);  in atl2_suspend()
1641 	ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);  in atl2_resume()
2094 	ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);  in atl2_reset_hw()
2132 	ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);  in atl2_spi_read()
2133 	ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);  in atl2_spi_read()
2148 	ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);  in atl2_spi_read()
2152 	ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);  in atl2_spi_read()
2357     ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);  in atl2_init_pcie()
2360     ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);  in atl2_init_pcie()
2404 	ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);  in atl2_init_hw()
2469 	ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);  in atl2_read_phy_reg()
2504 	ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);  in atl2_write_phy_reg()
2694 		ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);  in atl2_check_eeprom_exist()
2714 	ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);  in atl2_read_eeprom()
2716 	ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);  in atl2_read_eeprom()