Lines Matching +full:half +full:- +full:duplex
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
23 s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
24 u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
200 /* IRQ Anti-Lost Timer Initial Value Register */
206 #define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC i…
207 #define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC i…
208 #define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is …
209 #define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is …
210 #define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is…
211 #define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is…
212 #define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is …
213 #define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is …
217 #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to P…
218 #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read f…
245 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has …
246 /* decoder failure or more than 1 cell stuck-to-x failure */
253 #define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has …
254 /* decoder failure or more than 1 cell stuck-to-x failure.*/
269 #define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
271 #define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-byte…
286 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test …
295 …C_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit ti…
299 #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
301 #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
311 /* MAC Half-Duplex Control Register */
318 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately st…
319 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately…
320 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off …
323 …LX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
324 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
329 /* Wake-On-Lan control register */
375 * pointer to prepare for the operation. This bit is then self-cleared
420 … 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read comman…
421 …M_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byt…
433 #define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
459 * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
461 * shall start cut-through forwarding of the received packet.
516 /* RXF-Page 0-3 PageNo & Valid bit */
599 /* RXF-Page 0-3 Offset DMA Address */
633 /* 1000BASE-T Control Register */
649 #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
650 * 100BASE-TX/10BASE-T:
657 /* 1=Enable Extended 10BASE-T distance
658 * (Lower 10BASE-T RX Threshold)
659 * 0=Normal 10BASE-T RX Threshold */
661 /* 1=5-Bit interface in 100BASE-TX
662 * 0=MII interface in 100BASE-TX */
670 #define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
671 #define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */