29 static int port_aaui = -1;
33 #define MAX_TX_ACTIVE	1
34 #define NCMDS_TX	1	/* dma commands per element in tx ring */
36 #define TX_TIMEOUT	HZ	/* 1 second */
168 	rev = addr[0] == 0 && addr[1] == 0xA0;  in mace_probe()
180 	mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);  in mace_probe()
186 	mp->tx_dma_intr = macio_irq(mdev, 1);  in mace_probe()
196 	mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);  in mace_probe()
197 	mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;  in mace_probe()
210 			mp->port_aaui = 1;  in mace_probe()
213 			mp->port_aaui = 1;  in mace_probe()
258 	free_irq(macio_irq(mdev, 1), dev);  in mace_probe()
315 	    udelay(1);  in dbdma_reset()
321     volatile struct mace __iomem *mb = mp->mace;  in mace_reset()  local
327 	out_8(&mb->biucc, SWRST);  in mace_reset()
328 	if (in_8(&mb->biucc) & SWRST) {  in mace_reset()
339     out_8(&mb->imr, 0xff);	/* disable all intrs for now */  in mace_reset()
340     i = in_8(&mb->ir);  in mace_reset()
341     out_8(&mb->maccc, 0);	/* turn off tx, rx */  in mace_reset()
343     out_8(&mb->biucc, XMTSP_64);  in mace_reset()
344     out_8(&mb->utr, RTRD);  in mace_reset()
345     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);  in mace_reset()
346     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */  in mace_reset()
347     out_8(&mb->rcvfc, 0);  in mace_reset()
354 	out_8(&mb->iac, LOGADDR);  in mace_reset()
356 	out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_reset()
357 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_reset()
361 	out_8(&mb->ladrf, 0);  in mace_reset()
365 	out_8(&mb->iac, 0);  in mace_reset()
368 	out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);  in mace_reset()
370 	out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);  in mace_reset()
376     volatile struct mace __iomem *mb = mp->mace;  in __mace_set_address()  local
383 	out_8(&mb->iac, PHYADDR);  in __mace_set_address()
385 	out_8(&mb->iac, ADDRCHG | PHYADDR);  in __mace_set_address()
386 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in __mace_set_address()
390         out_8(&mb->padr, macaddr[i] = p[i]);  in __mace_set_address()
395         out_8(&mb->iac, 0);  in __mace_set_address()
401     volatile struct mace __iomem *mb = mp->mace;  in mace_set_address()  local
409     out_8(&mb->maccc, mp->maccc);  in mace_set_address()
436     volatile struct mace __iomem *mb = mp->mace;  in mace_open()  local
451     for (i = 0; i < N_RX_RING - 1; ++i) {  in mace_open()
496     out_8(&mb->maccc, mp->maccc);  in mace_open()
498     out_8(&mb->imr, RCVINT);  in mace_open()
506     volatile struct mace __iomem *mb = mp->mace;  in mace_close()  local
511     out_8(&mb->maccc, 0);  in mace_close()
512     out_8(&mb->imr, 0xff);		/* disable all intrs */  in mace_close()
531     mp->timeout_active = 1;  in mace_set_timeout()
545     next = fill + 1;  in mace_xmit_start()
550 	mp->tx_fullup = 1;  in mace_xmit_start()
592     volatile struct mace __iomem *mb = mp->mace;  in mace_set_multicast()  local
614 		multicast_filter[i >> 3] |= 1 << (i & 7);  in mace_set_multicast()
625 	    out_8(&mb->iac, LOGADDR);  in mace_set_multicast()
627 	    out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_set_multicast()
628 	    while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_set_multicast()
632 	    out_8(&mb->ladrf, multicast_filter[i]);  in mace_set_multicast()
634 	    out_8(&mb->iac, 0);  in mace_set_multicast()
637     out_8(&mb->maccc, mp->maccc);  in mace_set_multicast()
643     volatile struct mace __iomem *mb = mp->mace;  in mace_handle_misc_intrs()  local
648     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */  in mace_handle_misc_intrs()
651     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */  in mace_handle_misc_intrs()
666     volatile struct mace __iomem *mb = mp->mace;  in mace_interrupt()  local
675     intr = in_8(&mb->ir);		/* read interrupt register */  in mace_interrupt()
676     in_8(&mb->xmtrc);			/* get retries */  in mace_interrupt()
680     while (in_8(&mb->pr) & XMTSV) {  in mace_interrupt()
688 	intr = in_8(&mb->ir);  in mace_interrupt()
692 	    fs = in_8(&mb->xmtfs);  in mace_interrupt()
694 	    out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
704 	xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
717 	    out_8(&mb->xmtfc, DXMTFCS);  in mace_interrupt()
719 	fs = in_8(&mb->xmtfs);  in mace_interrupt()
736 	    udelay(1);  in mace_interrupt()
737 	    x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
740 		mp->tx_bad_runt = 1;  in mace_interrupt()
749 		out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);  in mace_interrupt()
750 		out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);  in mace_interrupt()
751 		udelay(1);  in mace_interrupt()
752 		out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);  in mace_interrupt()
753 		out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
812     volatile struct mace __iomem *mb = mp->mace;  in mace_tx_timeout()  local
825     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);  in mace_tx_timeout()
830     out_8(&mb->maccc, 0);  in mace_tx_timeout()
867     out_8(&mb->imr, RCVINT);  in mace_tx_timeout()
868     out_8(&mb->maccc, mp->maccc);  in mace_tx_timeout()
897 	    next = i + 1;  in mace_rxdma_intr()
954 	next = i + 1;  in mace_rxdma_intr()
1027 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");