1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3  * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
53 #define GET_BIT_VALUE(v, bit)		(((v) >> (bit)) & 0x1)  argument
55 /* MAC Command_Config Register Bit Definitions
57 #define MAC_CMDCFG_TX_ENA			BIT(0)
58 #define MAC_CMDCFG_RX_ENA			BIT(1)
59 #define MAC_CMDCFG_XON_GEN			BIT(2)
60 #define MAC_CMDCFG_ETH_SPEED			BIT(3)
61 #define MAC_CMDCFG_PROMIS_EN			BIT(4)
62 #define MAC_CMDCFG_PAD_EN			BIT(5)
63 #define MAC_CMDCFG_CRC_FWD			BIT(6)
64 #define MAC_CMDCFG_PAUSE_FWD			BIT(7)
65 #define MAC_CMDCFG_PAUSE_IGNORE			BIT(8)
66 #define MAC_CMDCFG_TX_ADDR_INS			BIT(9)
67 #define MAC_CMDCFG_HD_ENA			BIT(10)
68 #define MAC_CMDCFG_EXCESS_COL			BIT(11)
69 #define MAC_CMDCFG_LATE_COL			BIT(12)
70 #define MAC_CMDCFG_SW_RESET			BIT(13)
71 #define MAC_CMDCFG_MHASH_SEL			BIT(14)
72 #define MAC_CMDCFG_LOOP_ENA			BIT(15)
73 #define MAC_CMDCFG_TX_ADDR_SEL(v)		(((v) & 0x7) << 16)  argument
74 #define MAC_CMDCFG_MAGIC_ENA			BIT(19)
75 #define MAC_CMDCFG_SLEEP			BIT(20)
76 #define MAC_CMDCFG_WAKEUP			BIT(21)
77 #define MAC_CMDCFG_XOFF_GEN			BIT(22)
78 #define MAC_CMDCFG_CNTL_FRM_ENA			BIT(23)
79 #define MAC_CMDCFG_NO_LGTH_CHECK		BIT(24)
80 #define MAC_CMDCFG_ENA_10			BIT(25)
81 #define MAC_CMDCFG_RX_ERR_DISC			BIT(26)
82 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT		BIT(27)
83 #define MAC_CMDCFG_CNT_RESET			BIT(31)
85 #define MAC_CMDCFG_TX_ENA_GET(v)		GET_BIT_VALUE(v, 0)  argument
86 #define MAC_CMDCFG_RX_ENA_GET(v)		GET_BIT_VALUE(v, 1)  argument
87 #define MAC_CMDCFG_XON_GEN_GET(v)		GET_BIT_VALUE(v, 2)  argument
88 #define MAC_CMDCFG_ETH_SPEED_GET(v)		GET_BIT_VALUE(v, 3)  argument
89 #define MAC_CMDCFG_PROMIS_EN_GET(v)		GET_BIT_VALUE(v, 4)  argument
90 #define MAC_CMDCFG_PAD_EN_GET(v)		GET_BIT_VALUE(v, 5)  argument
91 #define MAC_CMDCFG_CRC_FWD_GET(v)		GET_BIT_VALUE(v, 6)  argument
92 #define MAC_CMDCFG_PAUSE_FWD_GET(v)		GET_BIT_VALUE(v, 7)  argument
93 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v)		GET_BIT_VALUE(v, 8)  argument
94 #define MAC_CMDCFG_TX_ADDR_INS_GET(v)		GET_BIT_VALUE(v, 9)  argument
95 #define MAC_CMDCFG_HD_ENA_GET(v)		GET_BIT_VALUE(v, 10)  argument
96 #define MAC_CMDCFG_EXCESS_COL_GET(v)		GET_BIT_VALUE(v, 11)  argument
97 #define MAC_CMDCFG_LATE_COL_GET(v)		GET_BIT_VALUE(v, 12)  argument
98 #define MAC_CMDCFG_SW_RESET_GET(v)		GET_BIT_VALUE(v, 13)  argument
99 #define MAC_CMDCFG_MHASH_SEL_GET(v)		GET_BIT_VALUE(v, 14)  argument
100 #define MAC_CMDCFG_LOOP_ENA_GET(v)		GET_BIT_VALUE(v, 15)  argument
101 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v)		(((v) >> 16) & 0x7)  argument
102 #define MAC_CMDCFG_MAGIC_ENA_GET(v)		GET_BIT_VALUE(v, 19)  argument
103 #define MAC_CMDCFG_SLEEP_GET(v)			GET_BIT_VALUE(v, 20)  argument
104 #define MAC_CMDCFG_WAKEUP_GET(v)		GET_BIT_VALUE(v, 21)  argument
105 #define MAC_CMDCFG_XOFF_GEN_GET(v)		GET_BIT_VALUE(v, 22)  argument
106 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v)		GET_BIT_VALUE(v, 23)  argument
107 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v)		GET_BIT_VALUE(v, 24)  argument
108 #define MAC_CMDCFG_ENA_10_GET(v)		GET_BIT_VALUE(v, 25)  argument
109 #define MAC_CMDCFG_RX_ERR_DISC_GET(v)		GET_BIT_VALUE(v, 26)  argument
110 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v)	GET_BIT_VALUE(v, 27)  argument
111 #define MAC_CMDCFG_CNT_RESET_GET(v)		GET_BIT_VALUE(v, 31)  argument
120 	u32 auto_negotiation_advertisement;	/* Auto-negotiation
160 	/* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
172 	/* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 	/* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 	/* 14-bit maximum frame length. The MAC receive logic */
183 	 * Ethernet device, in increments of 512 Ethernet bit times
186 	/* 12-bit receive FIFO section-empty threshold */
188 	/* 12-bit receive FIFO section-full threshold */
190 	/* 12-bit transmit FIFO section-empty threshold */
192 	/* 12-bit transmit FIFO section-full threshold */
194 	/* 12-bit receive FIFO almost-empty threshold */
196 	/* 12-bit receive FIFO almost-full threshold */
198 	/* 12-bit transmit FIFO almost-empty threshold */
200 	/* 12-bit transmit FIFO almost-full threshold */
202 	/* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
204 	/* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
207 	/* Bit[15:0]—16-bit holdoff quanta */
244 	/* IETF MIB (MIB-II) Object Support */
352 /* Transmit and Receive Command Registers Bit Definitions
354 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC		BIT(17)
355 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16	BIT(18)
356 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16	BIT(25)
465 	int phy_addr;		/* PHY's MDIO address, -1 for autodetection */