1 /* SPDX-License-Identifier: GPL-2.0-only */
17 	u32 burst_seq_num;	/* bit 31:24 write burst
18 				 * bit 23:16 read burst
19 				 * bit 15:0  sequence number
21 	u32 stride;		/* bit 31:16 write stride
22 				 * bit 15:0  read stride
29 /* mSGDMA descriptor control field bit definitions
32 #define MSGDMA_DESC_CTL_GEN_SOP		BIT(8)
33 #define MSGDMA_DESC_CTL_GEN_EOP		BIT(9)
34 #define MSGDMA_DESC_CTL_PARK_READS	BIT(10)
35 #define MSGDMA_DESC_CTL_PARK_WRITES	BIT(11)
36 #define MSGDMA_DESC_CTL_END_ON_EOP	BIT(12)
37 #define MSGDMA_DESC_CTL_END_ON_LEN	BIT(13)
38 #define MSGDMA_DESC_CTL_TR_COMP_IRQ	BIT(14)
39 #define MSGDMA_DESC_CTL_EARLY_IRQ	BIT(15)
41 #define MSGDMA_DESC_CTL_EARLY_DONE	BIT(24)
42 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
45 #define MSGDMA_DESC_CTL_GO		BIT(31)
80 	u32 rw_fill_level;	/* bit 31:16 - write fill level
81 				 * bit 15:0  - read fill level
83 	u32 resp_fill_level;	/* bit 15:0 */
84 	u32 rw_seq_num;		/* bit 31:16 - write sequence number
85 				 * bit 15:0  - read sequence number
90 /* mSGDMA CSR status register bit definitions
92 #define MSGDMA_CSR_STAT_BUSY			BIT(0)
93 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY		BIT(1)
94 #define MSGDMA_CSR_STAT_DESC_BUF_FULL		BIT(2)
95 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY		BIT(3)
96 #define MSGDMA_CSR_STAT_RESP_BUF_FULL		BIT(4)
97 #define MSGDMA_CSR_STAT_STOPPED			BIT(5)
98 #define MSGDMA_CSR_STAT_RESETTING		BIT(6)
99 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR		BIT(7)
100 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY	BIT(8)
101 #define MSGDMA_CSR_STAT_IRQ			BIT(9)
105 #define MSGDMA_CSR_STAT_BUSY_GET(v)			GET_BIT_VALUE(v, 0)  argument
106 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v)		GET_BIT_VALUE(v, 1)  argument
107 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v)		GET_BIT_VALUE(v, 2)  argument
108 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v)		GET_BIT_VALUE(v, 3)  argument
109 #define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v)		GET_BIT_VALUE(v, 4)  argument
110 #define MSGDMA_CSR_STAT_STOPPED_GET(v)			GET_BIT_VALUE(v, 5)  argument
111 #define MSGDMA_CSR_STAT_RESETTING_GET(v)		GET_BIT_VALUE(v, 6)  argument
112 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v)		GET_BIT_VALUE(v, 7)  argument
113 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v)		GET_BIT_VALUE(v, 8)  argument
114 #define MSGDMA_CSR_STAT_IRQ_GET(v)			GET_BIT_VALUE(v, 9)  argument
116 /* mSGDMA CSR control register bit definitions
118 #define MSGDMA_CSR_CTL_STOP			BIT(0)
119 #define MSGDMA_CSR_CTL_RESET			BIT(1)
120 #define MSGDMA_CSR_CTL_STOP_ON_ERR		BIT(2)
121 #define MSGDMA_CSR_CTL_STOP_ON_EARLY		BIT(3)
122 #define MSGDMA_CSR_CTL_GLOBAL_INTR		BIT(4)
123 #define MSGDMA_CSR_CTL_STOP_DESCS		BIT(5)
127 #define MSGDMA_CSR_WR_FILL_LEVEL_GET(v)		(((v) & 0xffff0000) >> 16)  argument
128 #define MSGDMA_CSR_RD_FILL_LEVEL_GET(v)		((v) & 0x0000ffff)  argument
129 #define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v)	((v) & 0x0000ffff)  argument
142 /* mSGDMA response register bit definitions
144 #define MSGDMA_RESP_EARLY_TERM	BIT(8)