1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
10 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)  in sja1105_pcs_mdio_read()  argument
12 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_pcs_mdio_read()
13 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_pcs_mdio_read()
14 	u64 addr;  in sja1105_pcs_mdio_read()  local
19 	if (!(reg & MII_ADDR_C45))  in sja1105_pcs_mdio_read()
20 		return -EINVAL;  in sja1105_pcs_mdio_read()
22 	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1105_pcs_mdio_read()
23 	addr = (mmd << 16) | (reg & GENMASK(15, 0));  in sja1105_pcs_mdio_read()
28 	if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)  in sja1105_pcs_mdio_read()
30 	if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)  in sja1105_pcs_mdio_read()
33 	rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);  in sja1105_pcs_mdio_read()
40 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)  in sja1105_pcs_mdio_write()  argument
42 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_pcs_mdio_write()
43 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_pcs_mdio_write()
44 	u64 addr;  in sja1105_pcs_mdio_write()  local
48 	if (!(reg & MII_ADDR_C45))  in sja1105_pcs_mdio_write()
49 		return -EINVAL;  in sja1105_pcs_mdio_write()
51 	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1105_pcs_mdio_write()
52 	addr = (mmd << 16) | (reg & GENMASK(15, 0));  in sja1105_pcs_mdio_write()
56 		return -EINVAL;  in sja1105_pcs_mdio_write()
58 	return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);  in sja1105_pcs_mdio_write()
61 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)  in sja1110_pcs_mdio_read()  argument
63 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1110_pcs_mdio_read()
64 	struct sja1105_private *priv = mdio_priv->priv;  in sja1110_pcs_mdio_read()
65 	const struct sja1105_regs *regs = priv->info->regs;  in sja1110_pcs_mdio_read()
67 	u64 addr;  in sja1110_pcs_mdio_read()  local
72 	if (!(reg & MII_ADDR_C45))  in sja1110_pcs_mdio_read()
73 		return -EINVAL;  in sja1110_pcs_mdio_read()
75 	if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)  in sja1110_pcs_mdio_read()
76 		return -ENODEV;  in sja1110_pcs_mdio_read()
78 	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1110_pcs_mdio_read()
79 	addr = (mmd << 16) | (reg & GENMASK(15, 0));  in sja1110_pcs_mdio_read()
81 	if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)  in sja1110_pcs_mdio_read()
83 	if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)  in sja1110_pcs_mdio_read()
86 	bank = addr >> 8;  in sja1110_pcs_mdio_read()
87 	offset = addr & GENMASK(7, 0);  in sja1110_pcs_mdio_read()
93 		return -ENODEV;  in sja1110_pcs_mdio_read()
98 			      regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,  in sja1110_pcs_mdio_read()
103 	rc = sja1105_xfer_u32(priv, SPI_READ, regs->pcs_base[phy] + offset,  in sja1110_pcs_mdio_read()
111 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)  in sja1110_pcs_mdio_write()  argument
113 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1110_pcs_mdio_write()
114 	struct sja1105_private *priv = mdio_priv->priv;  in sja1110_pcs_mdio_write()
115 	const struct sja1105_regs *regs = priv->info->regs;  in sja1110_pcs_mdio_write()
117 	u64 addr;  in sja1110_pcs_mdio_write()  local
122 	if (!(reg & MII_ADDR_C45))  in sja1110_pcs_mdio_write()
123 		return -EINVAL;  in sja1110_pcs_mdio_write()
125 	if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)  in sja1110_pcs_mdio_write()
126 		return -ENODEV;  in sja1110_pcs_mdio_write()
128 	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1110_pcs_mdio_write()
129 	addr = (mmd << 16) | (reg & GENMASK(15, 0));  in sja1110_pcs_mdio_write()
131 	bank = addr >> 8;  in sja1110_pcs_mdio_write()
132 	offset = addr & GENMASK(7, 0);  in sja1110_pcs_mdio_write()
138 		return -ENODEV;  in sja1110_pcs_mdio_write()
143 			      regs->pcs_base[phy] + SJA1110_PCS_BANK_REG,  in sja1110_pcs_mdio_write()
150 	return sja1105_xfer_u32(priv, SPI_WRITE, regs->pcs_base[phy] + offset,  in sja1110_pcs_mdio_write()
165 	const struct sja1105_regs *regs = priv->info->regs;  in sja1105_base_t1_encode_addr()
167 	return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0);  in sja1105_base_t1_encode_addr()
170 static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)  in sja1105_base_t1_mdio_read()  argument
172 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_base_t1_mdio_read()
173 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_base_t1_mdio_read()
174 	u64 addr;  in sja1105_base_t1_mdio_read()  local
178 	if (reg & MII_ADDR_C45) {  in sja1105_base_t1_mdio_read()
179 		u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1105_base_t1_mdio_read()
181 		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,  in sja1105_base_t1_mdio_read()
184 		tmp = reg & MII_REGADDR_C45_MASK;  in sja1105_base_t1_mdio_read()
186 		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);  in sja1105_base_t1_mdio_read()
190 		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,  in sja1105_base_t1_mdio_read()
193 		rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);  in sja1105_base_t1_mdio_read()
201 	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);  in sja1105_base_t1_mdio_read()
203 	rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);  in sja1105_base_t1_mdio_read()
210 static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg,  in sja1105_base_t1_mdio_write()  argument
213 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_base_t1_mdio_write()
214 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_base_t1_mdio_write()
215 	u64 addr;  in sja1105_base_t1_mdio_write()  local
219 	if (reg & MII_ADDR_C45) {  in sja1105_base_t1_mdio_write()
220 		u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;  in sja1105_base_t1_mdio_write()
222 		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,  in sja1105_base_t1_mdio_write()
225 		tmp = reg & MII_REGADDR_C45_MASK;  in sja1105_base_t1_mdio_write()
227 		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);  in sja1105_base_t1_mdio_write()
231 		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,  in sja1105_base_t1_mdio_write()
236 		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);  in sja1105_base_t1_mdio_write()
244 	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);  in sja1105_base_t1_mdio_write()
248 	return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);  in sja1105_base_t1_mdio_write()
251 static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)  in sja1105_base_tx_mdio_read()  argument
253 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_base_tx_mdio_read()
254 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_base_tx_mdio_read()
255 	const struct sja1105_regs *regs = priv->info->regs;  in sja1105_base_tx_mdio_read()
259 	if (reg & MII_ADDR_C45)  in sja1105_base_tx_mdio_read()
260 		return -EOPNOTSUPP;  in sja1105_base_tx_mdio_read()
262 	rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,  in sja1105_base_tx_mdio_read()
270 static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,  in sja1105_base_tx_mdio_write()  argument
273 	struct sja1105_mdio_private *mdio_priv = bus->priv;  in sja1105_base_tx_mdio_write()
274 	struct sja1105_private *priv = mdio_priv->priv;  in sja1105_base_tx_mdio_write()
275 	const struct sja1105_regs *regs = priv->info->regs;  in sja1105_base_tx_mdio_write()
278 	if (reg & MII_ADDR_C45)  in sja1105_base_tx_mdio_write()
279 		return -EOPNOTSUPP;  in sja1105_base_tx_mdio_write()
281 	return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,  in sja1105_base_tx_mdio_write()
293 	np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-tx-mdio");  in sja1105_mdiobus_base_tx_register()
302 		rc = -ENOMEM;  in sja1105_mdiobus_base_tx_register()
306 	bus->name = "SJA1110 100base-TX MDIO bus";  in sja1105_mdiobus_base_tx_register()
307 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-tx",  in sja1105_mdiobus_base_tx_register()
308 		 dev_name(priv->ds->dev));  in sja1105_mdiobus_base_tx_register()
309 	bus->read = sja1105_base_tx_mdio_read;  in sja1105_mdiobus_base_tx_register()
310 	bus->write = sja1105_base_tx_mdio_write;  in sja1105_mdiobus_base_tx_register()
311 	bus->parent = priv->ds->dev;  in sja1105_mdiobus_base_tx_register()
312 	mdio_priv = bus->priv;  in sja1105_mdiobus_base_tx_register()
313 	mdio_priv->priv = priv;  in sja1105_mdiobus_base_tx_register()
321 	priv->mdio_base_tx = bus;  in sja1105_mdiobus_base_tx_register()
331 	if (!priv->mdio_base_tx)  in sja1105_mdiobus_base_tx_unregister()
334 	mdiobus_unregister(priv->mdio_base_tx);  in sja1105_mdiobus_base_tx_unregister()
335 	mdiobus_free(priv->mdio_base_tx);  in sja1105_mdiobus_base_tx_unregister()
336 	priv->mdio_base_tx = NULL;  in sja1105_mdiobus_base_tx_unregister()
347 	np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-t1-mdio");  in sja1105_mdiobus_base_t1_register()
356 		rc = -ENOMEM;  in sja1105_mdiobus_base_t1_register()
360 	bus->name = "SJA1110 100base-T1 MDIO bus";  in sja1105_mdiobus_base_t1_register()
361 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1",  in sja1105_mdiobus_base_t1_register()
362 		 dev_name(priv->ds->dev));  in sja1105_mdiobus_base_t1_register()
363 	bus->read = sja1105_base_t1_mdio_read;  in sja1105_mdiobus_base_t1_register()
364 	bus->write = sja1105_base_t1_mdio_write;  in sja1105_mdiobus_base_t1_register()
365 	bus->parent = priv->ds->dev;  in sja1105_mdiobus_base_t1_register()
366 	mdio_priv = bus->priv;  in sja1105_mdiobus_base_t1_register()
367 	mdio_priv->priv = priv;  in sja1105_mdiobus_base_t1_register()
375 	priv->mdio_base_t1 = bus;  in sja1105_mdiobus_base_t1_register()
385 	if (!priv->mdio_base_t1)  in sja1105_mdiobus_base_t1_unregister()
388 	mdiobus_unregister(priv->mdio_base_t1);  in sja1105_mdiobus_base_t1_unregister()
389 	mdiobus_free(priv->mdio_base_t1);  in sja1105_mdiobus_base_t1_unregister()
390 	priv->mdio_base_t1 = NULL;  in sja1105_mdiobus_base_t1_unregister()
396 	struct dsa_switch *ds = priv->ds;  in sja1105_mdiobus_pcs_register()
401 	if (!priv->info->pcs_mdio_read || !priv->info->pcs_mdio_write)  in sja1105_mdiobus_pcs_register()
406 		return -ENOMEM;  in sja1105_mdiobus_pcs_register()
408 	bus->name = "SJA1105 PCS MDIO bus";  in sja1105_mdiobus_pcs_register()
409 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs",  in sja1105_mdiobus_pcs_register()
410 		 dev_name(ds->dev));  in sja1105_mdiobus_pcs_register()
411 	bus->read = priv->info->pcs_mdio_read;  in sja1105_mdiobus_pcs_register()
412 	bus->write = priv->info->pcs_mdio_write;  in sja1105_mdiobus_pcs_register()
413 	bus->parent = ds->dev;  in sja1105_mdiobus_pcs_register()
417 	bus->phy_mask = ~0;  in sja1105_mdiobus_pcs_register()
418 	mdio_priv = bus->priv;  in sja1105_mdiobus_pcs_register()
419 	mdio_priv->priv = priv;  in sja1105_mdiobus_pcs_register()
427 	for (port = 0; port < ds->num_ports; port++) {  in sja1105_mdiobus_pcs_register()
434 		if (priv->phy_mode[port] != PHY_INTERFACE_MODE_SGMII &&  in sja1105_mdiobus_pcs_register()
435 		    priv->phy_mode[port] != PHY_INTERFACE_MODE_2500BASEX)  in sja1105_mdiobus_pcs_register()
444 		xpcs = xpcs_create(mdiodev, priv->phy_mode[port]);  in sja1105_mdiobus_pcs_register()
450 		priv->xpcs[port] = xpcs;  in sja1105_mdiobus_pcs_register()
453 	priv->mdio_pcs = bus;  in sja1105_mdiobus_pcs_register()
458 	for (port = 0; port < ds->num_ports; port++) {  in sja1105_mdiobus_pcs_register()
459 		if (!priv->xpcs[port])  in sja1105_mdiobus_pcs_register()
462 		mdio_device_free(priv->xpcs[port]->mdiodev);  in sja1105_mdiobus_pcs_register()
463 		xpcs_destroy(priv->xpcs[port]);  in sja1105_mdiobus_pcs_register()
464 		priv->xpcs[port] = NULL;  in sja1105_mdiobus_pcs_register()
475 	struct dsa_switch *ds = priv->ds;  in sja1105_mdiobus_pcs_unregister()
478 	if (!priv->mdio_pcs)  in sja1105_mdiobus_pcs_unregister()
481 	for (port = 0; port < ds->num_ports; port++) {  in sja1105_mdiobus_pcs_unregister()
482 		if (!priv->xpcs[port])  in sja1105_mdiobus_pcs_unregister()
485 		mdio_device_free(priv->xpcs[port]->mdiodev);  in sja1105_mdiobus_pcs_unregister()
486 		xpcs_destroy(priv->xpcs[port]);  in sja1105_mdiobus_pcs_unregister()
487 		priv->xpcs[port] = NULL;  in sja1105_mdiobus_pcs_unregister()
490 	mdiobus_unregister(priv->mdio_pcs);  in sja1105_mdiobus_pcs_unregister()
491 	mdiobus_free(priv->mdio_pcs);  in sja1105_mdiobus_pcs_unregister()
492 	priv->mdio_pcs = NULL;  in sja1105_mdiobus_pcs_unregister()
497 	struct sja1105_private *priv = ds->priv;  in sja1105_mdiobus_register()
498 	const struct sja1105_regs *regs = priv->info->regs;  in sja1105_mdiobus_register()
499 	struct device_node *switch_node = ds->dev->of_node;  in sja1105_mdiobus_register()
514 	if (regs->mdio_100base_tx != SJA1105_RSV_ADDR) {  in sja1105_mdiobus_register()
520 	if (regs->mdio_100base_t1 != SJA1105_RSV_ADDR) {  in sja1105_mdiobus_register()
542 	struct sja1105_private *priv = ds->priv;  in sja1105_mdiobus_unregister()