Lines Matching +full:50 +full:mhz
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
357 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
480 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
481 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
482 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
483 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
596 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
599 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
602 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ in sja1105_rgmii_clocking_setup()
693 /* PLL1 must be enabled and output 50 Mhz. in sja1105_cgu_rmii_pll_config()
699 /* Step 1: PLL1 setup for 50Mhz */ in sja1105_cgu_rmii_pll_config()
713 dev_err(dev, "failed to configure PLL1 for 50MHz\n"); in sja1105_cgu_rmii_pll_config()
740 /* Configure and enable PLL1 for 50Mhz output */ in sja1105_rmii_clocking_setup()