Lines Matching refs:SJA1105_MAX_NUM_PORTS

78 	u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
79 	u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
80 	u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
81 	u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
82 	u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
83 	u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
84 	u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
85 	u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
86 	u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
87 	u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
88 	u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
89 	u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
90 	u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
93 	u64 pcs_base[SJA1105_MAX_NUM_PORTS];
156 	bool supports_mii[SJA1105_MAX_NUM_PORTS];
157 	bool supports_rmii[SJA1105_MAX_NUM_PORTS];
158 	bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
159 	bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
160 	bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
161 	enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
246 	int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS];
247 	int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS];
248 	phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
249 	bool fixed_link[SJA1105_MAX_NUM_PORTS];
257 	u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
258 	u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
274 	struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];