Lines Matching +full:rtl8367rb +full:- +full:vb
1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC |
22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension |
25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ |
26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ |
29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ |
31 * Interrupt <----------> Link UP/DOWN events |
33 * '-----------------------------------'
38 * partner of the extension port - either via a fixed-link or other phy-handle.
40 * driver has only been tested with a fixed-link, but in principle it should not
55 * This Linux driver is written based on an OS-agnostic vendor driver from
56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
61 * common hardware revision, there exist examples of chips with the suffix -VC
72 * - RTL8363NB
73 * - RTL8363NB-VB
74 * - RTL8363SC
75 * - RTL8363SC-VB
76 * - RTL8364NB
77 * - RTL8364NB-VB
78 * - RTL8365MB-VC
79 * - RTL8366SC
80 * - RTL8367RB-VB
81 * - RTL8367SB
82 * - RTL8367S
83 * - RTL8370MB
84 * - RTL8310SR
88 * things will work out-of-the-box for other chips, and a careful review of the
89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
104 /* Family-specific data and limits */
107 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
131 /* Interrupt control/status register - enable/check specific interrupt types */
160 /* Per-port interrupt type status registers */
191 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */
231 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
253 /* CPU port mask register - controls which ports are treated as CPU ports */
282 /* MSTP port state registers - indexed by tree instance */
480 * struct rtl8365mb_extint - external interface info
485 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded
495 * struct rtl8365mb_chip_info - static chip-specific info
496 * @name: human-readable chip name
500 * @jam_table: chip-specific initialization jam table
520 .name = "RTL8365MB-VC",
543 .name = "RTL8367RB-VB",
586 * struct rtl8365mb_cpu - CPU port configuration
587 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
590 * @insert: CPU tag insertion mode in switch->CPU frames
609 * struct rtl8365mb_port - private per-port data
626 * struct rtl8365mb - driver private data
629 * @chip_info: chip-specific info about the attached switch
632 * @ports: per-port data
649 return regmap_read_poll_timeout(priv->map_nolock, in rtl8365mb_phy_poll_busy()
663 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, in rtl8365mb_phy_ocp_prepare()
676 ret = regmap_write(priv->map_nolock, in rtl8365mb_phy_ocp_prepare()
690 mutex_lock(&priv->map_lock); in rtl8365mb_phy_ocp_read()
705 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, in rtl8365mb_phy_ocp_read()
715 ret = regmap_read(priv->map_nolock, in rtl8365mb_phy_ocp_read()
723 mutex_unlock(&priv->map_lock); in rtl8365mb_phy_ocp_read()
734 mutex_lock(&priv->map_lock); in rtl8365mb_phy_ocp_write()
745 ret = regmap_write(priv->map_nolock, in rtl8365mb_phy_ocp_write()
755 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, in rtl8365mb_phy_ocp_write()
765 mutex_unlock(&priv->map_lock); in rtl8365mb_phy_ocp_write()
777 return -EINVAL; in rtl8365mb_phy_read()
780 return -EINVAL; in rtl8365mb_phy_read()
786 dev_err(priv->dev, in rtl8365mb_phy_read()
792 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", in rtl8365mb_phy_read()
805 return -EINVAL; in rtl8365mb_phy_write()
808 return -EINVAL; in rtl8365mb_phy_write()
814 dev_err(priv->dev, in rtl8365mb_phy_write()
820 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", in rtl8365mb_phy_write()
828 return rtl8365mb_phy_read(ds->priv, phy, regnum); in rtl8365mb_dsa_phy_read()
834 return rtl8365mb_phy_write(ds->priv, phy, regnum, val); in rtl8365mb_dsa_phy_write()
840 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_get_port_extint()
845 &mb->chip_info->extints[i]; in rtl8365mb_get_port_extint()
847 if (!extint->supported_interfaces) in rtl8365mb_get_port_extint()
850 if (extint->port == port) in rtl8365mb_get_port_extint()
861 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_tag_protocol()
865 mb = priv->chip_data; in rtl8365mb_get_tag_protocol()
866 cpu = &mb->cpu; in rtl8365mb_get_tag_protocol()
868 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC) in rtl8365mb_get_tag_protocol()
887 return -ENODEV; in rtl8365mb_ext_config_rgmii()
889 dp = dsa_to_port(priv->ds, port); in rtl8365mb_ext_config_rgmii()
890 dn = dp->dn; in rtl8365mb_ext_config_rgmii()
909 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is in rtl8365mb_ext_config_rgmii()
911 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only in rtl8365mb_ext_config_rgmii()
914 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { in rtl8365mb_ext_config_rgmii()
920 dev_warn(priv->dev, in rtl8365mb_ext_config_rgmii()
924 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { in rtl8365mb_ext_config_rgmii()
930 dev_warn(priv->dev, in rtl8365mb_ext_config_rgmii()
935 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id), in rtl8365mb_ext_config_rgmii()
944 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id), in rtl8365mb_ext_config_rgmii()
945 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id), in rtl8365mb_ext_config_rgmii()
948 extint->id)); in rtl8365mb_ext_config_rgmii()
970 return -ENODEV; in rtl8365mb_ext_config_forcemode()
985 dev_err(priv->dev, "unsupported port speed %s\n", in rtl8365mb_ext_config_forcemode()
987 return -EINVAL; in rtl8365mb_ext_config_forcemode()
995 dev_err(priv->dev, "unsupported duplex %s\n", in rtl8365mb_ext_config_forcemode()
997 return -EINVAL; in rtl8365mb_ext_config_forcemode()
1017 ret = regmap_write(priv->map, in rtl8365mb_ext_config_forcemode()
1018 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), in rtl8365mb_ext_config_forcemode()
1030 rtl8365mb_get_port_extint(ds->priv, port); in rtl8365mb_phylink_get_caps()
1032 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | in rtl8365mb_phylink_get_caps()
1037 config->supported_interfaces); in rtl8365mb_phylink_get_caps()
1043 config->supported_interfaces); in rtl8365mb_phylink_get_caps()
1052 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) in rtl8365mb_phylink_get_caps()
1053 phy_interface_set_rgmii(config->supported_interfaces); in rtl8365mb_phylink_get_caps()
1060 struct realtek_priv *priv = ds->priv; in rtl8365mb_phylink_mac_config()
1064 dev_err(priv->dev, in rtl8365mb_phylink_mac_config()
1065 "port %d supports only conventional PHY or fixed-link\n", in rtl8365mb_phylink_mac_config()
1070 if (phy_interface_mode_is_rgmii(state->interface)) { in rtl8365mb_phylink_mac_config()
1071 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); in rtl8365mb_phylink_mac_config()
1073 dev_err(priv->dev, in rtl8365mb_phylink_mac_config()
1079 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also in rtl8365mb_phylink_mac_config()
1088 struct realtek_priv *priv = ds->priv; in rtl8365mb_phylink_mac_link_down()
1093 mb = priv->chip_data; in rtl8365mb_phylink_mac_link_down()
1094 p = &mb->ports[port]; in rtl8365mb_phylink_mac_link_down()
1095 cancel_delayed_work_sync(&p->mib_work); in rtl8365mb_phylink_mac_link_down()
1101 dev_err(priv->dev, in rtl8365mb_phylink_mac_link_down()
1116 struct realtek_priv *priv = ds->priv; in rtl8365mb_phylink_mac_link_up()
1121 mb = priv->chip_data; in rtl8365mb_phylink_mac_link_up()
1122 p = &mb->ports[port]; in rtl8365mb_phylink_mac_link_up()
1123 schedule_delayed_work(&p->mib_work, 0); in rtl8365mb_phylink_mac_link_up()
1130 dev_err(priv->dev, in rtl8365mb_phylink_mac_link_up()
1141 struct realtek_priv *priv = ds->priv; in rtl8365mb_port_stp_state_set()
1160 dev_err(priv->dev, "invalid STP state: %u\n", state); in rtl8365mb_port_stp_state_set()
1164 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), in rtl8365mb_port_stp_state_set()
1177 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), in rtl8365mb_port_set_learning()
1184 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); in rtl8365mb_port_set_isolation()
1199 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, in rtl8365mb_mib_counter_read()
1205 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, in rtl8365mb_mib_counter_read()
1213 return -EIO; in rtl8365mb_mib_counter_read()
1227 ret = regmap_read(priv->map, in rtl8365mb_mib_counter_read()
1228 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); in rtl8365mb_mib_counter_read()
1243 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_ethtool_stats()
1248 mb = priv->chip_data; in rtl8365mb_get_ethtool_stats()
1250 mutex_lock(&mb->mib_lock); in rtl8365mb_get_ethtool_stats()
1254 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, in rtl8365mb_get_ethtool_stats()
1255 mib->length, &data[i]); in rtl8365mb_get_ethtool_stats()
1257 dev_err(priv->dev, in rtl8365mb_get_ethtool_stats()
1263 mutex_unlock(&mb->mib_lock); in rtl8365mb_get_ethtool_stats()
1276 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); in rtl8365mb_get_strings()
1283 return -EOPNOTSUPP; in rtl8365mb_get_sset_count()
1291 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_phy_stats()
1295 mb = priv->chip_data; in rtl8365mb_get_phy_stats()
1298 mutex_lock(&mb->mib_lock); in rtl8365mb_get_phy_stats()
1299 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, in rtl8365mb_get_phy_stats()
1300 &phy_stats->SymbolErrorDuringCarrier); in rtl8365mb_get_phy_stats()
1301 mutex_unlock(&mb->mib_lock); in rtl8365mb_get_phy_stats()
1327 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_mac_stats()
1332 mb = priv->chip_data; in rtl8365mb_get_mac_stats()
1334 mutex_lock(&mb->mib_lock); in rtl8365mb_get_mac_stats()
1342 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, in rtl8365mb_get_mac_stats()
1343 mib->length, &cnt[i]); in rtl8365mb_get_mac_stats()
1347 mutex_unlock(&mb->mib_lock); in rtl8365mb_get_mac_stats()
1349 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into in rtl8365mb_get_mac_stats()
1355 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + in rtl8365mb_get_mac_stats()
1358 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - in rtl8365mb_get_mac_stats()
1360 mac_stats->SingleCollisionFrames = in rtl8365mb_get_mac_stats()
1362 mac_stats->MultipleCollisionFrames = in rtl8365mb_get_mac_stats()
1364 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + in rtl8365mb_get_mac_stats()
1368 mac_stats->FrameCheckSequenceErrors = in rtl8365mb_get_mac_stats()
1370 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - in rtl8365mb_get_mac_stats()
1371 18 * mac_stats->FramesTransmittedOK; in rtl8365mb_get_mac_stats()
1372 mac_stats->FramesWithDeferredXmissions = in rtl8365mb_get_mac_stats()
1374 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; in rtl8365mb_get_mac_stats()
1375 mac_stats->FramesAbortedDueToXSColls = in rtl8365mb_get_mac_stats()
1377 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - in rtl8365mb_get_mac_stats()
1378 18 * mac_stats->FramesReceivedOK; in rtl8365mb_get_mac_stats()
1379 mac_stats->MulticastFramesXmittedOK = in rtl8365mb_get_mac_stats()
1381 mac_stats->BroadcastFramesXmittedOK = in rtl8365mb_get_mac_stats()
1383 mac_stats->MulticastFramesReceivedOK = in rtl8365mb_get_mac_stats()
1385 mac_stats->BroadcastFramesReceivedOK = in rtl8365mb_get_mac_stats()
1392 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_ctrl_stats()
1396 mb = priv->chip_data; in rtl8365mb_get_ctrl_stats()
1399 mutex_lock(&mb->mib_lock); in rtl8365mb_get_ctrl_stats()
1400 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, in rtl8365mb_get_ctrl_stats()
1401 &ctrl_stats->UnsupportedOpcodesReceived); in rtl8365mb_get_ctrl_stats()
1402 mutex_unlock(&mb->mib_lock); in rtl8365mb_get_ctrl_stats()
1424 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_stats_update()
1429 stats = &mb->ports[port].stats; in rtl8365mb_stats_update()
1431 mutex_lock(&mb->mib_lock); in rtl8365mb_stats_update()
1439 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, in rtl8365mb_stats_update()
1440 c->length, &cnt[i]); in rtl8365mb_stats_update()
1444 mutex_unlock(&mb->mib_lock); in rtl8365mb_stats_update()
1450 spin_lock(&mb->ports[port].stats_lock); in rtl8365mb_stats_update()
1452 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + in rtl8365mb_stats_update()
1454 cnt[RTL8365MB_MIB_ifInBroadcastPkts] - in rtl8365mb_stats_update()
1457 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + in rtl8365mb_stats_update()
1461 /* if{In,Out}Octets includes FCS - remove it */ in rtl8365mb_stats_update()
1462 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; in rtl8365mb_stats_update()
1463 stats->tx_bytes = in rtl8365mb_stats_update()
1464 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; in rtl8365mb_stats_update()
1466 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; in rtl8365mb_stats_update()
1467 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; in rtl8365mb_stats_update()
1469 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; in rtl8365mb_stats_update()
1470 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; in rtl8365mb_stats_update()
1472 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + in rtl8365mb_stats_update()
1474 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; in rtl8365mb_stats_update()
1475 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; in rtl8365mb_stats_update()
1477 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; in rtl8365mb_stats_update()
1478 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; in rtl8365mb_stats_update()
1479 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; in rtl8365mb_stats_update()
1481 spin_unlock(&mb->ports[port].stats_lock); in rtl8365mb_stats_update()
1489 struct realtek_priv *priv = p->priv; in rtl8365mb_stats_poll()
1491 rtl8365mb_stats_update(priv, p->index); in rtl8365mb_stats_poll()
1493 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); in rtl8365mb_stats_poll()
1499 struct realtek_priv *priv = ds->priv; in rtl8365mb_get_stats64()
1503 mb = priv->chip_data; in rtl8365mb_get_stats64()
1504 p = &mb->ports[port]; in rtl8365mb_get_stats64()
1506 spin_lock(&p->stats_lock); in rtl8365mb_get_stats64()
1507 memcpy(s, &p->stats, sizeof(*s)); in rtl8365mb_get_stats64()
1508 spin_unlock(&p->stats_lock); in rtl8365mb_get_stats64()
1513 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_stats_setup()
1516 /* Per-chip global mutex to protect MIB counter access, since doing in rtl8365mb_stats_setup()
1519 mutex_init(&mb->mib_lock); in rtl8365mb_stats_setup()
1521 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_stats_setup()
1522 struct rtl8365mb_port *p = &mb->ports[i]; in rtl8365mb_stats_setup()
1524 if (dsa_is_unused_port(priv->ds, i)) in rtl8365mb_stats_setup()
1527 /* Per-port spinlock to protect the stats64 data */ in rtl8365mb_stats_setup()
1528 spin_lock_init(&p->stats_lock); in rtl8365mb_stats_setup()
1531 * up-to-date. in rtl8365mb_stats_setup()
1533 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); in rtl8365mb_stats_setup()
1539 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_stats_teardown()
1542 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_stats_teardown()
1543 struct rtl8365mb_port *p = &mb->ports[i]; in rtl8365mb_stats_teardown()
1545 if (dsa_is_unused_port(priv->ds, i)) in rtl8365mb_stats_teardown()
1548 cancel_delayed_work_sync(&p->mib_work); in rtl8365mb_stats_teardown()
1557 ret = regmap_read(priv->map, reg, val); in rtl8365mb_get_and_clear_status_reg()
1561 return regmap_write(priv->map, reg, *val); in rtl8365mb_get_and_clear_status_reg()
1602 for_each_set_bit(line, &line_changes, priv->num_ports) { in rtl8365mb_irq()
1603 int child_irq = irq_find_mapping(priv->irqdomain, line); in rtl8365mb_irq()
1611 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); in rtl8365mb_irq()
1619 /* The hardware doesn't support masking IRQs on a per-port basis */
1625 irq_set_chip_data(irq, domain->host_data); in rtl8365mb_irq_map()
1648 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, in rtl8365mb_set_irq_enable()
1666 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_irq_setup()
1675 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); in rtl8365mb_irq_setup()
1677 dev_err(priv->dev, "missing child interrupt-controller node\n"); in rtl8365mb_irq_setup()
1678 return -EINVAL; in rtl8365mb_irq_setup()
1684 if (irq != -EPROBE_DEFER) in rtl8365mb_irq_setup()
1685 dev_err(priv->dev, "failed to get parent irq: %d\n", in rtl8365mb_irq_setup()
1687 ret = irq ? irq : -EINVAL; in rtl8365mb_irq_setup()
1691 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, in rtl8365mb_irq_setup()
1693 if (!priv->irqdomain) { in rtl8365mb_irq_setup()
1694 dev_err(priv->dev, "failed to add irq domain\n"); in rtl8365mb_irq_setup()
1695 ret = -ENOMEM; in rtl8365mb_irq_setup()
1699 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_irq_setup()
1700 virq = irq_create_mapping(priv->irqdomain, i); in rtl8365mb_irq_setup()
1702 dev_err(priv->dev, in rtl8365mb_irq_setup()
1704 ret = -EINVAL; in rtl8365mb_irq_setup()
1723 dev_err(priv->dev, "unsupported irq trigger type %u\n", in rtl8365mb_irq_setup()
1725 ret = -EINVAL; in rtl8365mb_irq_setup()
1729 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, in rtl8365mb_irq_setup()
1741 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, in rtl8365mb_irq_setup()
1749 dev_err(priv->dev, "failed to request irq: %d\n", ret); in rtl8365mb_irq_setup()
1754 mb->irq = irq; in rtl8365mb_irq_setup()
1765 free_irq(mb->irq, priv); in rtl8365mb_irq_setup()
1766 mb->irq = 0; in rtl8365mb_irq_setup()
1769 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_irq_setup()
1770 virq = irq_find_mapping(priv->irqdomain, i); in rtl8365mb_irq_setup()
1774 irq_domain_remove(priv->irqdomain); in rtl8365mb_irq_setup()
1775 priv->irqdomain = NULL; in rtl8365mb_irq_setup()
1785 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_irq_teardown()
1789 if (mb->irq) { in rtl8365mb_irq_teardown()
1790 free_irq(mb->irq, priv); in rtl8365mb_irq_teardown()
1791 mb->irq = 0; in rtl8365mb_irq_teardown()
1794 if (priv->irqdomain) { in rtl8365mb_irq_teardown()
1795 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_irq_teardown()
1796 virq = irq_find_mapping(priv->irqdomain, i); in rtl8365mb_irq_teardown()
1800 irq_domain_remove(priv->irqdomain); in rtl8365mb_irq_teardown()
1801 priv->irqdomain = NULL; in rtl8365mb_irq_teardown()
1807 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_cpu_config()
1808 struct rtl8365mb_cpu *cpu = &mb->cpu; in rtl8365mb_cpu_config()
1812 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, in rtl8365mb_cpu_config()
1815 cpu->mask)); in rtl8365mb_cpu_config()
1819 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | in rtl8365mb_cpu_config()
1820 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | in rtl8365mb_cpu_config()
1821 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | in rtl8365mb_cpu_config()
1822 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | in rtl8365mb_cpu_config()
1823 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | in rtl8365mb_cpu_config()
1824 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | in rtl8365mb_cpu_config()
1826 cpu->trap_port >> 3 & 0x1); in rtl8365mb_cpu_config()
1827 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); in rtl8365mb_cpu_config()
1837 struct realtek_priv *priv = ds->priv; in rtl8365mb_change_tag_protocol()
1841 mb = priv->chip_data; in rtl8365mb_change_tag_protocol()
1842 cpu = &mb->cpu; in rtl8365mb_change_tag_protocol()
1846 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; in rtl8365mb_change_tag_protocol()
1847 cpu->position = RTL8365MB_CPU_POS_AFTER_SA; in rtl8365mb_change_tag_protocol()
1850 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; in rtl8365mb_change_tag_protocol()
1851 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC; in rtl8365mb_change_tag_protocol()
1853 /* The switch also supports a 4-byte format, similar to rtl4a but with in rtl8365mb_change_tag_protocol()
1854 * the same 0x04 8-bit version and probably 8-bit port source/dest. in rtl8365mb_change_tag_protocol()
1859 return -EPROTONOSUPPORT; in rtl8365mb_change_tag_protocol()
1867 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_switch_init()
1872 ci = mb->chip_info; in rtl8365mb_switch_init()
1874 /* Do any chip-specific init jam before getting to the common stuff */ in rtl8365mb_switch_init()
1875 if (ci->jam_table) { in rtl8365mb_switch_init()
1876 for (i = 0; i < ci->jam_size; i++) { in rtl8365mb_switch_init()
1877 ret = regmap_write(priv->map, ci->jam_table[i].reg, in rtl8365mb_switch_init()
1878 ci->jam_table[i].val); in rtl8365mb_switch_init()
1886 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, in rtl8365mb_switch_init()
1899 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, in rtl8365mb_reset_chip()
1906 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, in rtl8365mb_reset_chip()
1913 struct realtek_priv *priv = ds->priv; in rtl8365mb_setup()
1920 mb = priv->chip_data; in rtl8365mb_setup()
1921 cpu = &mb->cpu; in rtl8365mb_setup()
1925 dev_err(priv->dev, "failed to reset chip: %d\n", ret); in rtl8365mb_setup()
1929 /* Configure switch to vendor-defined initial state */ in rtl8365mb_setup()
1932 dev_err(priv->dev, "failed to initialize switch: %d\n", ret); in rtl8365mb_setup()
1938 if (ret == -EPROBE_DEFER) in rtl8365mb_setup()
1941 dev_info(priv->dev, "no interrupt support\n"); in rtl8365mb_setup()
1944 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) { in rtl8365mb_setup()
1945 cpu->mask |= BIT(cpu_dp->index); in rtl8365mb_setup()
1947 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS) in rtl8365mb_setup()
1948 cpu->trap_port = cpu_dp->index; in rtl8365mb_setup()
1950 cpu->enable = cpu->mask > 0; in rtl8365mb_setup()
1956 for (i = 0; i < priv->num_ports; i++) { in rtl8365mb_setup()
1957 struct rtl8365mb_port *p = &mb->ports[i]; in rtl8365mb_setup()
1959 if (dsa_is_unused_port(priv->ds, i)) in rtl8365mb_setup()
1963 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask); in rtl8365mb_setup()
1976 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); in rtl8365mb_setup()
1978 /* Set up per-port private data */ in rtl8365mb_setup()
1979 p->priv = priv; in rtl8365mb_setup()
1980 p->index = i; in rtl8365mb_setup()
1984 ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, in rtl8365mb_setup()
1990 if (priv->setup_interface) { in rtl8365mb_setup()
1991 ret = priv->setup_interface(ds); in rtl8365mb_setup()
1993 dev_err(priv->dev, "could not set up MDIO bus\n"); in rtl8365mb_setup()
2012 struct realtek_priv *priv = ds->priv; in rtl8365mb_teardown()
2047 struct rtl8365mb *mb = priv->chip_data; in rtl8365mb_detect()
2053 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); in rtl8365mb_detect()
2055 dev_err(priv->dev, "failed to read chip id and version: %d\n", in rtl8365mb_detect()
2063 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) { in rtl8365mb_detect()
2064 mb->chip_info = ci; in rtl8365mb_detect()
2069 if (!mb->chip_info) { in rtl8365mb_detect()
2070 dev_err(priv->dev, in rtl8365mb_detect()
2073 return -ENODEV; in rtl8365mb_detect()
2076 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name); in rtl8365mb_detect()
2078 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; in rtl8365mb_detect()
2079 mb->priv = priv; in rtl8365mb_detect()
2080 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; in rtl8365mb_detect()
2081 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; in rtl8365mb_detect()
2082 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; in rtl8365mb_detect()
2083 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; in rtl8365mb_detect()
2084 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; in rtl8365mb_detect()
2146 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2147 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");