Lines Matching +full:sgmii +full:- +full:txclk +full:- +full:falling +full:- +full:edge
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
42 u16 *cached_lo = &priv->mdio_cache.lo; in qca8k_set_lo()
43 struct mii_bus *bus = priv->bus; in qca8k_set_lo()
49 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_set_lo()
51 dev_err_ratelimited(&bus->dev, in qca8k_set_lo()
61 u16 *cached_hi = &priv->mdio_cache.hi; in qca8k_set_hi()
62 struct mii_bus *bus = priv->bus; in qca8k_set_hi()
68 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_set_hi()
70 dev_err_ratelimited(&bus->dev, in qca8k_set_hi()
82 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read32()
85 ret = bus->read(bus, phy_id, regnum + 1); in qca8k_mii_read32()
90 dev_err_ratelimited(&bus->dev, in qca8k_mii_read32()
116 u16 *cached_page = &priv->mdio_cache.page; in qca8k_set_page()
117 struct mii_bus *bus = priv->bus; in qca8k_set_page()
123 ret = bus->write(bus, 0x18, 0, page); in qca8k_set_page()
125 dev_err_ratelimited(&bus->dev, in qca8k_set_page()
138 struct qca8k_priv *priv = ds->priv; in qca8k_rw_reg_ack_handler()
145 mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_rw_reg_ack_handler()
147 command = get_unaligned_le32(&mgmt_ethhdr->command); in qca8k_rw_reg_ack_handler()
152 if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq) in qca8k_rw_reg_ack_handler()
153 mgmt_eth_data->ack = true; in qca8k_rw_reg_ack_handler()
156 u32 *val = mgmt_eth_data->data; in qca8k_rw_reg_ack_handler()
158 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data); in qca8k_rw_reg_ack_handler()
164 __le32 *data2 = (__le32 *)skb->data; in qca8k_rw_reg_ack_handler()
166 len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_rw_reg_ack_handler()
178 complete(&mgmt_eth_data->rw_done); in qca8k_rw_reg_ack_handler()
199 * 1-4: first 4 byte in qca8k_alloc_mdio_header()
200 * 5-6: first 12 byte in qca8k_alloc_mdio_header()
201 * 7-15: all 16 byte in qca8k_alloc_mdio_header()
209 skb_set_network_header(skb, skb->len); in qca8k_alloc_mdio_header()
225 put_unaligned_le32(command, &mgmt_ethhdr->command); in qca8k_alloc_mdio_header()
228 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data); in qca8k_alloc_mdio_header()
230 mgmt_ethhdr->hdr = htons(hdr); in qca8k_alloc_mdio_header()
235 len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_alloc_mdio_header()
255 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data; in qca8k_mdio_header_fill_seq_num()
256 put_unaligned_le32(seq, &mgmt_ethhdr->seq); in qca8k_mdio_header_fill_seq_num()
261 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_read_eth()
269 return -ENOMEM; in qca8k_read_eth()
271 mutex_lock(&mgmt_eth_data->mutex); in qca8k_read_eth()
274 if (!priv->mgmt_master) { in qca8k_read_eth()
276 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_read_eth()
277 return -EINVAL; in qca8k_read_eth()
280 skb->dev = priv->mgmt_master; in qca8k_read_eth()
282 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_read_eth()
285 mgmt_eth_data->seq++; in qca8k_read_eth()
286 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_read_eth()
287 mgmt_eth_data->ack = false; in qca8k_read_eth()
291 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_read_eth()
294 *val = mgmt_eth_data->data[0]; in qca8k_read_eth()
296 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_read_eth()
298 ack = mgmt_eth_data->ack; in qca8k_read_eth()
300 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_read_eth()
303 return -ETIMEDOUT; in qca8k_read_eth()
306 return -EINVAL; in qca8k_read_eth()
313 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_write_eth()
321 return -ENOMEM; in qca8k_write_eth()
323 mutex_lock(&mgmt_eth_data->mutex); in qca8k_write_eth()
326 if (!priv->mgmt_master) { in qca8k_write_eth()
328 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_write_eth()
329 return -EINVAL; in qca8k_write_eth()
332 skb->dev = priv->mgmt_master; in qca8k_write_eth()
334 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_write_eth()
337 mgmt_eth_data->seq++; in qca8k_write_eth()
338 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_write_eth()
339 mgmt_eth_data->ack = false; in qca8k_write_eth()
343 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_write_eth()
346 ack = mgmt_eth_data->ack; in qca8k_write_eth()
348 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_write_eth()
351 return -ETIMEDOUT; in qca8k_write_eth()
354 return -EINVAL; in qca8k_write_eth()
379 struct mii_bus *bus = priv->bus; in qca8k_regmap_read()
388 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_regmap_read()
397 mutex_unlock(&bus->mdio_lock); in qca8k_regmap_read()
405 struct mii_bus *bus = priv->bus; in qca8k_regmap_write()
414 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_regmap_write()
423 mutex_unlock(&bus->mdio_lock); in qca8k_regmap_write()
431 struct mii_bus *bus = priv->bus; in qca8k_regmap_update_bits()
441 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_regmap_update_bits()
456 mutex_unlock(&bus->mdio_lock); in qca8k_regmap_update_bits()
465 .max_register = 0x16ac, /* end MIB - Port6 range */
482 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_busy_wait()
485 mgmt_eth_data->seq++; in qca8k_phy_eth_busy_wait()
486 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_phy_eth_busy_wait()
487 mgmt_eth_data->ack = false; in qca8k_phy_eth_busy_wait()
491 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_busy_wait()
494 ack = mgmt_eth_data->ack; in qca8k_phy_eth_busy_wait()
497 return -ETIMEDOUT; in qca8k_phy_eth_busy_wait()
500 return -EINVAL; in qca8k_phy_eth_busy_wait()
502 *val = mgmt_eth_data->data[0]; in qca8k_phy_eth_busy_wait()
519 return -EINVAL; in qca8k_phy_eth_command()
521 mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_phy_eth_command()
538 return -ENOMEM; in qca8k_phy_eth_command()
543 ret = -ENOMEM; in qca8k_phy_eth_command()
550 ret = -ENOMEM; in qca8k_phy_eth_command()
560 mutex_lock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
563 mgmt_master = priv->mgmt_master; in qca8k_phy_eth_command()
565 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
566 ret = -EINVAL; in qca8k_phy_eth_command()
570 read_skb->dev = mgmt_master; in qca8k_phy_eth_command()
571 clear_skb->dev = mgmt_master; in qca8k_phy_eth_command()
572 write_skb->dev = mgmt_master; in qca8k_phy_eth_command()
574 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
577 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
578 qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
579 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
583 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
586 ack = mgmt_eth_data->ack; in qca8k_phy_eth_command()
589 ret = -ETIMEDOUT; in qca8k_phy_eth_command()
595 ret = -EINVAL; in qca8k_phy_eth_command()
611 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
614 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
615 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
616 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
620 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
623 ack = mgmt_eth_data->ack; in qca8k_phy_eth_command()
626 ret = -ETIMEDOUT; in qca8k_phy_eth_command()
631 ret = -EINVAL; in qca8k_phy_eth_command()
635 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK; in qca8k_phy_eth_command()
640 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
643 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
644 qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
645 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
649 wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
652 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
679 return port - 1; in qca8k_port_to_phy()
696 * before returnting -ETIMEDOUT in qca8k_mdio_busy_wait()
707 struct mii_bus *bus = priv->bus; in qca8k_mdio_write()
713 return -EINVAL; in qca8k_mdio_write()
722 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_write()
737 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_write()
745 struct mii_bus *bus = priv->bus; in qca8k_mdio_read()
751 return -EINVAL; in qca8k_mdio_read()
759 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_read()
778 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_read()
789 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_write()
803 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_read()
838 struct dsa_switch *ds = priv->ds; in qca8k_mdio_register()
842 bus = devm_mdiobus_alloc(ds->dev); in qca8k_mdio_register()
844 return -ENOMEM; in qca8k_mdio_register()
846 bus->priv = (void *)priv; in qca8k_mdio_register()
847 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d", in qca8k_mdio_register()
848 ds->dst->index, ds->index); in qca8k_mdio_register()
849 bus->parent = ds->dev; in qca8k_mdio_register()
850 bus->phy_mask = ~ds->phys_mii_mask; in qca8k_mdio_register()
851 ds->slave_mii_bus = bus; in qca8k_mdio_register()
854 mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); in qca8k_mdio_register()
856 bus->name = "qca8k slave mii"; in qca8k_mdio_register()
857 bus->read = qca8k_internal_mdio_read; in qca8k_mdio_register()
858 bus->write = qca8k_internal_mdio_write; in qca8k_mdio_register()
859 return devm_of_mdiobus_register(priv->dev, bus, mdio); in qca8k_mdio_register()
865 bus->name = "qca8k-legacy slave mii"; in qca8k_mdio_register()
866 bus->read = qca8k_legacy_mdio_read; in qca8k_mdio_register()
867 bus->write = qca8k_legacy_mdio_write; in qca8k_mdio_register()
868 return devm_mdiobus_register(priv->dev, bus); in qca8k_mdio_register()
879 ports = of_get_child_by_name(priv->dev->of_node, "ports"); in qca8k_setup_mdio_bus()
881 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); in qca8k_setup_mdio_bus()
884 return -EINVAL; in qca8k_setup_mdio_bus()
894 if (!dsa_is_user_port(priv->ds, reg)) in qca8k_setup_mdio_bus()
899 if (of_property_read_bool(port, "phy-handle") && in qca8k_setup_mdio_bus()
908 dev_err(priv->dev, "no PHYs are defined.\n"); in qca8k_setup_mdio_bus()
909 return -EINVAL; in qca8k_setup_mdio_bus()
918 * If the external mdio-bus driver is capable magically disabling in qca8k_setup_mdio_bus()
919 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's in qca8k_setup_mdio_bus()
924 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); in qca8k_setup_mdio_bus()
925 return -EINVAL; in qca8k_setup_mdio_bus()
930 * a dt-overlay and driver reload changed the configuration in qca8k_setup_mdio_bus()
933 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL, in qca8k_setup_mdio_bus()
969 struct qca8k_priv *priv = ds->priv; in qca8k_find_cpu_port()
975 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); in qca8k_find_cpu_port()
980 return -EINVAL; in qca8k_find_cpu_port()
986 const struct qca8k_match_data *data = priv->info; in qca8k_setup_of_pws_reg()
987 struct device_node *node = priv->dev->of_node; in qca8k_setup_of_pws_reg()
995 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_setup_of_pws_reg()
997 if (data->reduced_package) in qca8k_setup_of_pws_reg()
1006 if (of_property_read_bool(node, "qca,ignore-power-on-sel")) in qca8k_setup_of_pws_reg()
1009 if (of_property_read_bool(node, "qca,led-open-drain")) { in qca8k_setup_of_pws_reg()
1011 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); in qca8k_setup_of_pws_reg()
1012 return -EINVAL; in qca8k_setup_of_pws_reg()
1026 int port, cpu_port_index = -1, ret; in qca8k_parse_port_config()
1038 dp = dsa_to_port(priv->ds, port); in qca8k_parse_port_config()
1039 port_dn = dp->dn; in qca8k_parse_port_config()
1057 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) in qca8k_parse_port_config()
1065 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_parse_port_config()
1069 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; in qca8k_parse_port_config()
1073 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) in qca8k_parse_port_config()
1081 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_parse_port_config()
1085 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; in qca8k_parse_port_config()
1087 /* Skip sgmii parsing for rgmii* mode */ in qca8k_parse_port_config()
1094 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) in qca8k_parse_port_config()
1095 priv->ports_config.sgmii_tx_clk_falling_edge = true; in qca8k_parse_port_config()
1097 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) in qca8k_parse_port_config()
1098 priv->ports_config.sgmii_rx_clk_falling_edge = true; in qca8k_parse_port_config()
1100 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { in qca8k_parse_port_config()
1101 priv->ports_config.sgmii_enable_pll = true; in qca8k_parse_port_config()
1103 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_parse_port_config()
1104 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); in qca8k_parse_port_config()
1105 priv->ports_config.sgmii_enable_pll = false; in qca8k_parse_port_config()
1108 if (priv->switch_revision < 2) in qca8k_parse_port_config()
1109 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); in qca8k_parse_port_config()
1129 * Mode to rgmii and internal-delay standard binding defined in qca8k_mac_config_setup_internal_delay()
1130 * rgmii-id or rgmii-tx/rx phy mode set. in qca8k_mac_config_setup_internal_delay()
1136 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { in qca8k_mac_config_setup_internal_delay()
1137 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; in qca8k_mac_config_setup_internal_delay()
1143 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { in qca8k_mac_config_setup_internal_delay()
1144 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; in qca8k_mac_config_setup_internal_delay()
1158 dev_err(priv->dev, "Failed to set internal delay for CPU port%d", in qca8k_mac_config_setup_internal_delay()
1166 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_select_pcs()
1174 pcs = &priv->pcs_port_0.pcs; in qca8k_phylink_mac_select_pcs()
1178 pcs = &priv->pcs_port_6.pcs; in qca8k_phylink_mac_select_pcs()
1194 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_config()
1200 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1201 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1202 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1203 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1204 state->interface != PHY_INTERFACE_MODE_SGMII) in qca8k_phylink_mac_config()
1218 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1219 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1220 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1221 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1222 state->interface != PHY_INTERFACE_MODE_SGMII && in qca8k_phylink_mac_config()
1223 state->interface != PHY_INTERFACE_MODE_1000BASEX) in qca8k_phylink_mac_config()
1230 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); in qca8k_phylink_mac_config()
1235 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in qca8k_phylink_mac_config()
1240 switch (state->interface) { in qca8k_phylink_mac_config()
1254 if (priv->switch_id == QCA8K_ID_QCA8337) in qca8k_phylink_mac_config()
1260 /* Enable SGMII on the port */ in qca8k_phylink_mac_config()
1264 dev_err(ds->dev, "xMII mode %s not supported for port %d\n", in qca8k_phylink_mac_config()
1265 phy_modes(state->interface), port); in qca8k_phylink_mac_config()
1275 phy_interface_set_rgmii(config->supported_interfaces); in qca8k_phylink_get_caps()
1277 config->supported_interfaces); in qca8k_phylink_get_caps()
1287 config->supported_interfaces); in qca8k_phylink_get_caps()
1289 config->supported_interfaces); in qca8k_phylink_get_caps()
1293 phy_interface_set_rgmii(config->supported_interfaces); in qca8k_phylink_get_caps()
1295 config->supported_interfaces); in qca8k_phylink_get_caps()
1297 config->supported_interfaces); in qca8k_phylink_get_caps()
1301 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in qca8k_phylink_get_caps()
1304 config->legacy_pre_march2020 = false; in qca8k_phylink_get_caps()
1311 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_down()
1321 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_up()
1365 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; in qca8k_pcs_get_state()
1366 int port = pcs_to_qca8k_pcs(pcs)->port; in qca8k_pcs_get_state()
1372 state->link = false; in qca8k_pcs_get_state()
1376 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); in qca8k_pcs_get_state()
1377 state->an_complete = state->link; in qca8k_pcs_get_state()
1378 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO); in qca8k_pcs_get_state()
1379 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : in qca8k_pcs_get_state()
1384 state->speed = SPEED_10; in qca8k_pcs_get_state()
1387 state->speed = SPEED_100; in qca8k_pcs_get_state()
1390 state->speed = SPEED_1000; in qca8k_pcs_get_state()
1393 state->speed = SPEED_UNKNOWN; in qca8k_pcs_get_state()
1398 state->pause |= MLO_PAUSE_RX; in qca8k_pcs_get_state()
1400 state->pause |= MLO_PAUSE_TX; in qca8k_pcs_get_state()
1408 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; in qca8k_pcs_config()
1412 port = pcs_to_qca8k_pcs(pcs)->port; in qca8k_pcs_config()
1426 return -EINVAL; in qca8k_pcs_config()
1429 /* Enable/disable SerDes auto-negotiation as necessary */ in qca8k_pcs_config()
1439 /* Configure the SGMII parameters */ in qca8k_pcs_config()
1446 if (priv->ports_config.sgmii_enable_pll) in qca8k_pcs_config()
1450 if (dsa_is_cpu_port(priv->ds, port)) { in qca8k_pcs_config()
1464 /* From original code is reported port instability as SGMII also in qca8k_pcs_config()
1469 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and in qca8k_pcs_config()
1470 * falling edge is set writing in the PORT0 PAD reg in qca8k_pcs_config()
1472 if (priv->switch_id == QCA8K_ID_QCA8327 || in qca8k_pcs_config()
1473 priv->switch_id == QCA8K_ID_QCA8337) in qca8k_pcs_config()
1478 /* SGMII Clock phase configuration */ in qca8k_pcs_config()
1479 if (priv->ports_config.sgmii_rx_clk_falling_edge) in qca8k_pcs_config()
1482 if (priv->ports_config.sgmii_tx_clk_falling_edge) in qca8k_pcs_config()
1507 qpcs->pcs.ops = &qca8k_pcs_ops; in qca8k_setup_pcs()
1510 qpcs->pcs.poll = true; in qca8k_setup_pcs()
1511 qpcs->priv = priv; in qca8k_setup_pcs()
1512 qpcs->port = port; in qca8k_setup_pcs()
1518 struct qca8k_priv *priv = ds->priv; in qca8k_mib_autocast_handler()
1526 mib_eth_data = &priv->mib_eth_data; in qca8k_mib_autocast_handler()
1531 port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr)); in qca8k_mib_autocast_handler()
1532 if (port != mib_eth_data->req_port) in qca8k_mib_autocast_handler()
1535 data2 = (__le32 *)skb->data; in qca8k_mib_autocast_handler()
1537 for (i = 0; i < priv->info->mib_count; i++) { in qca8k_mib_autocast_handler()
1542 mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i); in qca8k_mib_autocast_handler()
1547 if (mib->size == 2) in qca8k_mib_autocast_handler()
1548 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2); in qca8k_mib_autocast_handler()
1550 mib_eth_data->data[i] = get_unaligned_le32(data2); in qca8k_mib_autocast_handler()
1552 data2 += mib->size; in qca8k_mib_autocast_handler()
1557 if (refcount_dec_and_test(&mib_eth_data->port_parsed)) in qca8k_mib_autocast_handler()
1558 complete(&mib_eth_data->rw_done); in qca8k_mib_autocast_handler()
1566 struct qca8k_priv *priv = ds->priv; in qca8k_get_ethtool_stats_eth()
1569 mib_eth_data = &priv->mib_eth_data; in qca8k_get_ethtool_stats_eth()
1571 mutex_lock(&mib_eth_data->mutex); in qca8k_get_ethtool_stats_eth()
1573 reinit_completion(&mib_eth_data->rw_done); in qca8k_get_ethtool_stats_eth()
1575 mib_eth_data->req_port = dp->index; in qca8k_get_ethtool_stats_eth()
1576 mib_eth_data->data = data; in qca8k_get_ethtool_stats_eth()
1577 refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS); in qca8k_get_ethtool_stats_eth()
1579 mutex_lock(&priv->reg_mutex); in qca8k_get_ethtool_stats_eth()
1582 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, in qca8k_get_ethtool_stats_eth()
1587 mutex_unlock(&priv->reg_mutex); in qca8k_get_ethtool_stats_eth()
1592 ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT); in qca8k_get_ethtool_stats_eth()
1595 mutex_unlock(&mib_eth_data->mutex); in qca8k_get_ethtool_stats_eth()
1602 struct qca8k_priv *priv = ds->priv; in qca8k_get_phy_flags()
1611 return priv->switch_revision; in qca8k_get_phy_flags()
1627 struct dsa_port *dp = master->dsa_ptr; in qca8k_master_change()
1628 struct qca8k_priv *priv = ds->priv; in qca8k_master_change()
1631 if (dp->index != 0) in qca8k_master_change()
1634 mutex_lock(&priv->mgmt_eth_data.mutex); in qca8k_master_change()
1635 mutex_lock(&priv->mib_eth_data.mutex); in qca8k_master_change()
1637 priv->mgmt_master = operational ? (struct net_device *)master : NULL; in qca8k_master_change()
1639 mutex_unlock(&priv->mib_eth_data.mutex); in qca8k_master_change()
1640 mutex_unlock(&priv->mgmt_eth_data.mutex); in qca8k_master_change()
1650 tagger_data = ds->tagger_data; in qca8k_connect_tag_protocol()
1652 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler; in qca8k_connect_tag_protocol()
1653 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler; in qca8k_connect_tag_protocol()
1657 return -EOPNOTSUPP; in qca8k_connect_tag_protocol()
1666 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_setup()
1672 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); in qca8k_setup()
1693 qca8k_setup_pcs(priv, &priv->pcs_port_0, 0); in qca8k_setup()
1694 qca8k_setup_pcs(priv, &priv->pcs_port_6, 6); in qca8k_setup()
1697 ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL, in qca8k_setup()
1700 dev_err(priv->dev, "failed disabling MAC06 exchange"); in qca8k_setup()
1705 ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, in qca8k_setup()
1708 dev_err(priv->dev, "failed enabling CPU port"); in qca8k_setup()
1715 dev_warn(priv->dev, "mib init failed"); in qca8k_setup()
1731 dev_err(priv->dev, "failed enabling QCA header mode"); in qca8k_setup()
1742 * Notice that in multi-cpu config only one port should be set in qca8k_setup()
1773 /* Enable ARP Auto-learning by default */ in qca8k_setup()
1774 ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i), in qca8k_setup()
1801 if (priv->switch_id == QCA8K_ID_QCA8337) { in qca8k_setup()
1840 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_setup()
1852 dev_warn(priv->dev, "failed setting MTU settings"); in qca8k_setup()
1858 ds->ageing_time_min = 7000; in qca8k_setup()
1859 ds->ageing_time_max = 458745000; in qca8k_setup()
1862 ds->num_lag_ids = QCA8K_NUM_LAGS; in qca8k_setup()
1915 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in qca8k_sw_probe()
1917 return -ENOMEM; in qca8k_sw_probe()
1919 priv->bus = mdiodev->bus; in qca8k_sw_probe()
1920 priv->dev = &mdiodev->dev; in qca8k_sw_probe()
1921 priv->info = of_device_get_match_data(priv->dev); in qca8k_sw_probe()
1923 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", in qca8k_sw_probe()
1925 if (IS_ERR(priv->reset_gpio)) in qca8k_sw_probe()
1926 return PTR_ERR(priv->reset_gpio); in qca8k_sw_probe()
1928 if (priv->reset_gpio) { in qca8k_sw_probe()
1929 gpiod_set_value_cansleep(priv->reset_gpio, 1); in qca8k_sw_probe()
1934 gpiod_set_value_cansleep(priv->reset_gpio, 0); in qca8k_sw_probe()
1938 priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv, in qca8k_sw_probe()
1940 if (IS_ERR(priv->regmap)) { in qca8k_sw_probe()
1941 dev_err(priv->dev, "regmap initialization failed"); in qca8k_sw_probe()
1942 return PTR_ERR(priv->regmap); in qca8k_sw_probe()
1945 priv->mdio_cache.page = 0xffff; in qca8k_sw_probe()
1946 priv->mdio_cache.lo = 0xffff; in qca8k_sw_probe()
1947 priv->mdio_cache.hi = 0xffff; in qca8k_sw_probe()
1954 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in qca8k_sw_probe()
1955 if (!priv->ds) in qca8k_sw_probe()
1956 return -ENOMEM; in qca8k_sw_probe()
1958 mutex_init(&priv->mgmt_eth_data.mutex); in qca8k_sw_probe()
1959 init_completion(&priv->mgmt_eth_data.rw_done); in qca8k_sw_probe()
1961 mutex_init(&priv->mib_eth_data.mutex); in qca8k_sw_probe()
1962 init_completion(&priv->mib_eth_data.rw_done); in qca8k_sw_probe()
1964 priv->ds->dev = &mdiodev->dev; in qca8k_sw_probe()
1965 priv->ds->num_ports = QCA8K_NUM_PORTS; in qca8k_sw_probe()
1966 priv->ds->priv = priv; in qca8k_sw_probe()
1967 priv->ds->ops = &qca8k_switch_ops; in qca8k_sw_probe()
1968 mutex_init(&priv->reg_mutex); in qca8k_sw_probe()
1969 dev_set_drvdata(&mdiodev->dev, priv); in qca8k_sw_probe()
1971 return dsa_register_switch(priv->ds); in qca8k_sw_probe()
1977 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_remove()
1986 dsa_unregister_switch(priv->ds); in qca8k_sw_remove()
1991 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_shutdown()
1996 dsa_switch_shutdown(priv->ds); in qca8k_sw_shutdown()
1998 dev_set_drvdata(&mdiodev->dev, NULL); in qca8k_sw_shutdown()
2011 if (!(priv->port_enabled_map & BIT(port))) in qca8k_set_pm()
2024 return dsa_switch_suspend(priv->ds); in qca8k_suspend()
2033 return dsa_switch_resume(priv->ds); in qca8k_resume()