Lines Matching +full:0 +full:x404
10 /* 0 - Operation */
11 #define REG_GLOBAL_CTRL_0 0x0007
17 #define REG_SW_INT_STATUS__4 0x0010
18 #define REG_SW_INT_MASK__4 0x0014
32 #define REG_SW_PORT_INT_STATUS__4 0x0018
33 #define REG_SW_PORT_INT_MASK__4 0x001C
36 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
38 #define SW_CLK25_ENB BIT(0)
41 #define REG_SW_OPERATION 0x0300
47 #define REG_SW_LUE_CTRL_0 0x0310
51 #define SW_AGE_CNT_M 0x7
55 #define REG_SW_LUE_CTRL_1 0x0311
63 #define SW_LINK_AUTO_AGING BIT(0)
65 #define REG_SW_AGE_PERIOD__1 0x0313
66 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)
68 #define REG_SW_AGE_PERIOD__2 0x0320
71 #define REG_SW_MAC_CTRL_0 0x0330
74 #define SW_AGGR_BACKOFF BIT(0)
76 #define REG_SW_MAC_CTRL_1 0x0331
83 #define SW_PASS_SHORT_FRAME BIT(0)
85 #define REG_SW_MAC_CTRL_6 0x0336
90 #define REG_SW_ALU_STAT_CTRL__4 0x041C
92 #define REG_SW_ALU_VAL_B 0x0424
95 #define ALU_V_PORT_MAP 0xFF
98 #define REG_VPHY_IND_ADDR__2 0x075C
99 #define REG_VPHY_IND_DATA__2 0x0760
101 #define REG_VPHY_IND_CTRL__2 0x0768
104 #define VPHY_IND_BUSY BIT(0)
106 #define REG_VPHY_SPECIAL_CTRL__2 0x077C
111 #define VPHY_PORT_MODE_M 0x3
113 #define VPHY_MODE_RGMII 0
118 #define VPHY_SPEED_DUPLEX_STAT_M 0x7
126 /* 0 - Operation */
127 #define REG_PORT_INT_STATUS 0x001B
128 #define REG_PORT_INT_MASK 0x001F
135 #define PORT_ACL_INT BIT(0)
139 #define REG_PORT_CTRL_0 0x0020
146 #define PORT_QUEUE_SPLIT_ENABLE 0x3
149 #define REG_PORT_T1_PHY_CTRL_BASE 0x0100
153 #define PORT_GRXC_ENABLE BIT(0)
157 #define REG_PORT_XMII_CTRL_4 0x0304
158 #define REG_PORT_XMII_CTRL_5 0x0306
164 #define REG_PORT_MAC_CTRL_0 0x0400
167 #define PORT_JUMBO_PACKET BIT(0)
169 #define REG_PORT_MAC_CTRL_1 0x0401
171 #define PORT_PASS_ALL BIT(0)
173 #define PORT_MAX_FR_SIZE 0x404
177 #define REG_PORT_MRI_PRIO_CTRL 0x0801
184 #define PORT_ACL_PRIO_ENABLE BIT(0)
196 #define RGMII_2_TX_DELAY_2NS 0
197 #define RGMII_1_RX_DELAY_2NS 0x1B
198 #define RGMII_2_RX_DELAY_2NS 0x14