Lines Matching +full:soft +full:- +full:compensation +full:- +full:method
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
85 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
87 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
139 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
140 #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (TDC) Enable */
155 /* TX-FIFO-empty interrupt available */
186 * struct xcan_priv - This definition define CAN driver instance
285 /* Transmission Delay Compensation constants for CANFD 1.0 */
295 /* Transmission Delay Compensation constants for CANFD 2.0 */
306 * xcan_write_reg_le - Write a value to the device register little endian
316 iowrite32(val, priv->reg_base + reg); in xcan_write_reg_le()
320 * xcan_read_reg_le - Read a value from the device register little endian
329 return ioread32(priv->reg_base + reg); in xcan_read_reg_le()
333 * xcan_write_reg_be - Write a value to the device register big endian
343 iowrite32be(val, priv->reg_base + reg); in xcan_write_reg_be()
347 * xcan_read_reg_be - Read a value from the device register big endian
356 return ioread32be(priv->reg_base + reg); in xcan_read_reg_be()
360 * xcan_rx_int_mask - Get the mask for the receive interrupt
368 * while the FIFO is non-empty, but CAN FD HW does not have it in xcan_rx_int_mask()
370 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_int_mask()
377 * set_reset_mode - Resets the CAN device mode
390 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
393 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { in set_reset_mode()
396 return -ETIMEDOUT; in set_reset_mode()
402 priv->tx_head = 0; in set_reset_mode()
403 priv->tx_tail = 0; in set_reset_mode()
409 * xcan_set_bittiming - CAN set bit timing routine
418 struct can_bittiming *bt = &priv->can.bittiming; in xcan_set_bittiming()
419 struct can_bittiming *dbt = &priv->can.data_bittiming; in xcan_set_bittiming()
426 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_set_bittiming()
430 "BUG! Cannot set bittiming - CAN is not in config mode\n"); in xcan_set_bittiming()
431 return -EPERM; in xcan_set_bittiming()
435 btr0 = (bt->brp - 1); in xcan_set_bittiming()
438 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); in xcan_set_bittiming()
441 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
444 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
446 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
447 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
449 if (priv->devtype.cantype == XAXI_CANFD || in xcan_set_bittiming()
450 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_set_bittiming()
452 btr0 = dbt->brp - 1; in xcan_set_bittiming()
453 if (can_tdc_is_enabled(&priv->can)) { in xcan_set_bittiming()
454 if (priv->devtype.cantype == XAXI_CANFD) in xcan_set_bittiming()
455 btr0 |= FIELD_PREP(XCAN_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
458 btr0 |= FIELD_PREP(XCAN_2_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
463 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; in xcan_set_bittiming()
466 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
469 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
471 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); in xcan_set_bittiming()
472 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); in xcan_set_bittiming()
476 priv->read_reg(priv, XCAN_BRPR_OFFSET), in xcan_set_bittiming()
477 priv->read_reg(priv, XCAN_BTR_OFFSET)); in xcan_set_bittiming()
483 * xcan_chip_start - This the drivers start routine
520 if (priv->devtype.flags & XCAN_FLAG_RXMNF) in xcan_chip_start()
523 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_chip_start()
526 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in xcan_chip_start()
532 * filtering default to non-receipt if all filters are disabled in xcan_chip_start()
534 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) in xcan_chip_start()
535 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); in xcan_chip_start()
537 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
538 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
541 priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_chip_start()
543 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_chip_start()
548 * xcan_do_set_mode - This sets the mode of the driver
570 ret = -EOPNOTSUPP; in xcan_do_set_mode()
578 * xcan_write_frame - Write a frame to HW
587 struct canfd_frame *cf = (struct canfd_frame *)skb->data; in xcan_write_frame()
592 if (cf->can_id & CAN_EFF_FLAG) { in xcan_write_frame()
594 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & in xcan_write_frame()
596 id |= (((cf->can_id & CAN_EFF_MASK) >> in xcan_write_frame()
597 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << in xcan_write_frame()
605 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
610 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & in xcan_write_frame()
613 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
618 dlc = can_fd_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; in xcan_write_frame()
620 if (cf->flags & CANFD_BRS) in xcan_write_frame()
625 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_write_frame()
626 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) in xcan_write_frame()
627 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max, 0); in xcan_write_frame()
631 priv->tx_head++; in xcan_write_frame()
633 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); in xcan_write_frame()
637 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); in xcan_write_frame()
638 if (priv->devtype.cantype == XAXI_CANFD || in xcan_write_frame()
639 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_write_frame()
640 for (i = 0; i < cf->len; i += 4) { in xcan_write_frame()
643 priv->write_reg(priv, ramoff, in xcan_write_frame()
644 be32_to_cpup((__be32 *)(cf->data + i))); in xcan_write_frame()
648 if (cf->len > 0) in xcan_write_frame()
649 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); in xcan_write_frame()
650 if (cf->len > 4) in xcan_write_frame()
651 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); in xcan_write_frame()
653 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_write_frame()
654 priv->write_reg(priv, in xcan_write_frame()
660 priv->write_reg(priv, in xcan_write_frame()
668 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
672 * Return: 0 on success, -ENOSPC if FIFO is full.
680 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_start_xmit_fifo()
682 return -ENOSPC; in xcan_start_xmit_fifo()
684 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
688 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ in xcan_start_xmit_fifo()
689 if (priv->tx_max > 1) in xcan_start_xmit_fifo()
690 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); in xcan_start_xmit_fifo()
693 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) in xcan_start_xmit_fifo()
696 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
702 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
706 * Return: 0 on success, -ENOSPC if there is no space
713 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & in xcan_start_xmit_mailbox()
715 return -ENOSPC; in xcan_start_xmit_mailbox()
717 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
723 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); in xcan_start_xmit_mailbox()
727 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
733 * xcan_start_xmit - Starts the transmission
749 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) in xcan_start_xmit()
764 * xcan_rx - Is called from CAN isr to complete the received
777 struct net_device_stats *stats = &ndev->stats; in xcan_rx()
784 stats->rx_dropped++; in xcan_rx()
789 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcan_rx()
790 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> in xcan_rx()
794 cf->len = can_cc_dlc2len(dlc); in xcan_rx()
799 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcan_rx()
800 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcan_rx()
802 cf->can_id |= CAN_EFF_FLAG; in xcan_rx()
804 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
807 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcan_rx()
810 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
814 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); in xcan_rx()
815 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); in xcan_rx()
817 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_rx()
819 if (cf->len > 0) in xcan_rx()
820 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); in xcan_rx()
821 if (cf->len > 4) in xcan_rx()
822 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); in xcan_rx()
824 stats->rx_bytes += cf->len; in xcan_rx()
826 stats->rx_packets++; in xcan_rx()
834 * xcanfd_rx - Is called from CAN isr to complete the received
847 struct net_device_stats *stats = &ndev->stats; in xcanfd_rx()
852 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcanfd_rx()
853 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); in xcanfd_rx()
860 stats->rx_dropped++; in xcanfd_rx()
868 cf->len = can_fd_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
871 cf->len = can_cc_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
877 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcanfd_rx()
878 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcanfd_rx()
880 cf->can_id |= CAN_EFF_FLAG; in xcanfd_rx()
882 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
885 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcanfd_rx()
889 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
894 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
897 data[0] = priv->read_reg(priv, dw_offset); in xcanfd_rx()
898 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
902 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
904 data[0] = priv->read_reg(priv, dw_offset + i); in xcanfd_rx()
905 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
909 if (!(cf->can_id & CAN_RTR_FLAG)) in xcanfd_rx()
910 stats->rx_bytes += cf->len; in xcanfd_rx()
911 stats->rx_packets++; in xcanfd_rx()
919 * xcan_current_error_state - Get current error state from HW
932 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); in xcan_current_error_state()
943 * xcan_set_error_state - Set new CAN error state
956 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); in xcan_set_error_state()
962 /* non-ERROR states are handled elsewhere */ in xcan_set_error_state()
969 cf->can_id |= CAN_ERR_CNT; in xcan_set_error_state()
970 cf->data[6] = txerr; in xcan_set_error_state()
971 cf->data[7] = rxerr; in xcan_set_error_state()
976 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
979 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
986 enum can_state old_state = priv->can.state; in xcan_update_error_state_after_rxtx()
1012 * xcan_err_interrupt - error frame Isr
1023 struct net_device_stats *stats = &ndev->stats; in xcan_err_interrupt()
1027 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); in xcan_err_interrupt()
1028 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); in xcan_err_interrupt()
1031 priv->can.state = CAN_STATE_BUS_OFF; in xcan_err_interrupt()
1032 priv->can.can_stats.bus_off++; in xcan_err_interrupt()
1033 /* Leave device in Config Mode in bus-off state */ in xcan_err_interrupt()
1034 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in xcan_err_interrupt()
1040 if (new_state != priv->can.state) in xcan_err_interrupt()
1046 priv->can.can_stats.arbitration_lost++; in xcan_err_interrupt()
1053 stats->rx_over_errors++; in xcan_err_interrupt()
1054 stats->rx_errors++; in xcan_err_interrupt()
1061 stats->rx_dropped++; in xcan_err_interrupt()
1062 stats->rx_errors++; in xcan_err_interrupt()
1072 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in xcan_err_interrupt()
1079 stats->tx_errors++; in xcan_err_interrupt()
1088 stats->tx_errors++; in xcan_err_interrupt()
1097 stats->rx_errors++; in xcan_err_interrupt()
1106 stats->rx_errors++; in xcan_err_interrupt()
1115 stats->rx_errors++; in xcan_err_interrupt()
1121 priv->can.can_stats.bus_error++; in xcan_err_interrupt()
1129 skb_cf->can_id |= cf.can_id; in xcan_err_interrupt()
1130 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); in xcan_err_interrupt()
1136 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); in xcan_err_interrupt()
1140 * xcan_state_interrupt - It will check the state of the CAN device
1153 priv->can.state = CAN_STATE_SLEEPING; in xcan_state_interrupt()
1157 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_state_interrupt()
1161 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1170 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { in xcan_rx_fifo_get_next_frame()
1173 /* clear RXOK before the is-empty check so that any newly in xcan_rx_fifo_get_next_frame()
1176 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); in xcan_rx_fifo_get_next_frame()
1178 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); in xcan_rx_fifo_get_next_frame()
1181 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1187 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1189 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1198 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & in xcan_rx_fifo_get_next_frame()
1200 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1210 * xcan_rx_poll - Poll routine for rx packets (NAPI)
1221 struct net_device *ndev = napi->dev; in xcan_rx_poll()
1234 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_poll()
1236 priv->write_reg(priv, XCAN_FSR_OFFSET, in xcan_rx_poll()
1239 /* clear rx-not-empty (will actually clear only if in xcan_rx_poll()
1242 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_rx_poll()
1251 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_rx_poll()
1253 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_rx_poll()
1260 * xcan_tx_interrupt - Tx Done Isr
1267 struct net_device_stats *stats = &ndev->stats; in xcan_tx_interrupt()
1279 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_tx_interrupt()
1281 frames_in_fifo = priv->tx_head - priv->tx_tail; in xcan_tx_interrupt()
1285 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1286 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1294 WARN_ON(frames_in_fifo > priv->tx_max); in xcan_tx_interrupt()
1297 * (1) isr variable is up-to-date at least up to TXOK clear in xcan_tx_interrupt()
1308 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_tx_interrupt()
1310 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_tx_interrupt()
1319 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1322 while (frames_sent--) { in xcan_tx_interrupt()
1323 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % in xcan_tx_interrupt()
1324 priv->tx_max, NULL); in xcan_tx_interrupt()
1325 priv->tx_tail++; in xcan_tx_interrupt()
1326 stats->tx_packets++; in xcan_tx_interrupt()
1331 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1337 * xcan_interrupt - CAN Isr
1345 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
1356 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_interrupt()
1362 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | in xcan_interrupt()
1376 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); in xcan_interrupt()
1382 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_interrupt()
1384 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_interrupt()
1385 napi_schedule(&priv->napi); in xcan_interrupt()
1391 * xcan_chip_stop - Driver stop routine
1407 priv->can.state = CAN_STATE_STOPPED; in xcan_chip_stop()
1411 * xcan_open - Driver open routine
1422 ret = pm_runtime_get_sync(priv->dev); in xcan_open()
1429 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, in xcan_open()
1430 ndev->name, ndev); in xcan_open()
1454 napi_enable(&priv->napi); in xcan_open()
1462 free_irq(ndev->irq, ndev); in xcan_open()
1464 pm_runtime_put(priv->dev); in xcan_open()
1470 * xcan_close - Driver close routine
1480 napi_disable(&priv->napi); in xcan_close()
1482 free_irq(ndev->irq, ndev); in xcan_close()
1485 pm_runtime_put(priv->dev); in xcan_close()
1491 * xcan_get_berr_counter - error counter routine
1504 ret = pm_runtime_get_sync(priv->dev); in xcan_get_berr_counter()
1508 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1512 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; in xcan_get_berr_counter()
1513 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & in xcan_get_berr_counter()
1516 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1522 * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value
1532 *tdcv = FIELD_GET(XCAN_SR_TDCV_MASK, priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_get_auto_tdcv()
1549 * xcan_suspend - Suspend method for the driver
1569 * xcan_resume - Resume from suspend
1601 * xcan_runtime_suspend - Runtime suspend method for the driver
1612 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_suspend()
1613 clk_disable_unprepare(priv->can_clk); in xcan_runtime_suspend()
1619 * xcan_runtime_resume - Runtime resume from suspend
1631 ret = clk_prepare_enable(priv->bus_clk); in xcan_runtime_resume()
1636 ret = clk_prepare_enable(priv->can_clk); in xcan_runtime_resume()
1639 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_resume()
1695 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1696 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
1697 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1698 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
1704 * xcan_probe - Platform registration call
1731 of_id = of_match_device(xcan_of_match, &pdev->dev); in xcan_probe()
1732 if (of_id && of_id->data) in xcan_probe()
1733 devtype = of_id->data; in xcan_probe()
1735 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? in xcan_probe()
1736 "tx-mailbox-count" : "tx-fifo-depth"; in xcan_probe()
1738 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, in xcan_probe()
1741 dev_err(&pdev->dev, "missing %s property\n", in xcan_probe()
1746 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", in xcan_probe()
1749 dev_err(&pdev->dev, in xcan_probe()
1750 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); in xcan_probe()
1764 * sent), which is not a sensible state - possibly TXFWMEMP is not in xcan_probe()
1772 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_probe()
1773 (devtype->flags & XCAN_FLAG_TXFEMP)) in xcan_probe()
1783 return -ENOMEM; in xcan_probe()
1786 priv->dev = &pdev->dev; in xcan_probe()
1787 priv->can.bittiming_const = devtype->bittiming_const; in xcan_probe()
1788 priv->can.do_set_mode = xcan_do_set_mode; in xcan_probe()
1789 priv->can.do_get_berr_counter = xcan_get_berr_counter; in xcan_probe()
1790 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in xcan_probe()
1793 if (devtype->cantype == XAXI_CANFD) { in xcan_probe()
1794 priv->can.data_bittiming_const = in xcan_probe()
1796 priv->can.tdc_const = &xcan_tdc_const_canfd; in xcan_probe()
1799 if (devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1800 priv->can.data_bittiming_const = in xcan_probe()
1802 priv->can.tdc_const = &xcan_tdc_const_canfd2; in xcan_probe()
1805 if (devtype->cantype == XAXI_CANFD || in xcan_probe()
1806 devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1807 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | in xcan_probe()
1809 priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv; in xcan_probe()
1812 priv->reg_base = addr; in xcan_probe()
1813 priv->tx_max = tx_max; in xcan_probe()
1814 priv->devtype = *devtype; in xcan_probe()
1815 spin_lock_init(&priv->tx_lock); in xcan_probe()
1822 ndev->irq = ret; in xcan_probe()
1824 ndev->flags |= IFF_ECHO; /* We support local echo */ in xcan_probe()
1827 SET_NETDEV_DEV(ndev, &pdev->dev); in xcan_probe()
1828 ndev->netdev_ops = &xcan_netdev_ops; in xcan_probe()
1829 ndev->ethtool_ops = &xcan_ethtool_ops; in xcan_probe()
1832 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); in xcan_probe()
1833 if (IS_ERR(priv->can_clk)) { in xcan_probe()
1834 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->can_clk), in xcan_probe()
1839 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); in xcan_probe()
1840 if (IS_ERR(priv->bus_clk)) { in xcan_probe()
1841 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->bus_clk), in xcan_probe()
1846 priv->write_reg = xcan_write_reg_le; in xcan_probe()
1847 priv->read_reg = xcan_read_reg_le; in xcan_probe()
1849 pm_runtime_enable(&pdev->dev); in xcan_probe()
1850 ret = pm_runtime_get_sync(&pdev->dev); in xcan_probe()
1857 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { in xcan_probe()
1858 priv->write_reg = xcan_write_reg_be; in xcan_probe()
1859 priv->read_reg = xcan_read_reg_be; in xcan_probe()
1862 priv->can.clock.freq = clk_get_rate(priv->can_clk); in xcan_probe()
1864 netif_napi_add_weight(ndev, &priv->napi, xcan_rx_poll, rx_max); in xcan_probe()
1868 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); in xcan_probe()
1872 pm_runtime_put(&pdev->dev); in xcan_probe()
1874 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { in xcan_probe()
1875 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); in xcan_probe()
1876 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); in xcan_probe()
1880 priv->reg_base, ndev->irq, priv->can.clock.freq, in xcan_probe()
1881 hw_tx_max, priv->tx_max); in xcan_probe()
1886 pm_runtime_put(priv->dev); in xcan_probe()
1887 pm_runtime_disable(&pdev->dev); in xcan_probe()
1895 * xcan_remove - Unregister the device after releasing the resources
1906 pm_runtime_disable(&pdev->dev); in xcan_remove()