Lines Matching +full:pins +full:- +full:are +full:- +full:numbered
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
29 #include <linux/can/rx-offload.h>
37 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
38 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
43 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
56 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
57 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
61 * The remaining mailboxes are used for reception and are delivered
63 * changed while CAN-bus traffic is being received.
65 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
66 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
94 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
95 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
114 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
116 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
195 return priv->tx_head & HECC_TX_MB_MASK; in get_tx_head_mb()
200 return priv->tx_tail & HECC_TX_MB_MASK; in get_tx_tail_mb()
205 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; in get_tx_head_prio()
210 __raw_writel(val, priv->hecc_ram + mbxno * 4); in hecc_write_lam()
215 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); in hecc_read_stamp()
221 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); in hecc_write_mbx()
226 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); in hecc_read_mbx()
231 __raw_writel(val, priv->base + reg); in hecc_write()
236 return __raw_readl(priv->base + reg); in hecc_read()
258 struct can_bittiming *bit_timing = &priv->can.bittiming; in ti_hecc_set_btc()
261 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; in ti_hecc_set_btc()
262 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) in ti_hecc_set_btc()
264 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { in ti_hecc_set_btc()
265 if (bit_timing->brp > 4) in ti_hecc_set_btc()
268 netdev_warn(priv->ndev, in ti_hecc_set_btc()
271 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; in ti_hecc_set_btc()
272 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; in ti_hecc_set_btc()
277 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); in ti_hecc_set_btc()
285 if (!priv->reg_xceiver) in ti_hecc_transceiver_switch()
289 return regulator_enable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
291 return regulator_disable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
311 --cnt; in ti_hecc_reset()
316 * it is expected that the can bittiming parameters are set via ip in ti_hecc_reset()
324 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on in ti_hecc_reset()
333 --cnt; in ti_hecc_reset()
337 /* Enable TX and RX I/O Control pins */ in ti_hecc_reset()
361 priv->tx_head = HECC_TX_MASK; in ti_hecc_start()
362 priv->tx_tail = HECC_TX_MASK; in ti_hecc_start()
369 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; in ti_hecc_start()
380 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); in ti_hecc_start()
382 /* Prevent message over-write to create a rx fifo, but not for in ti_hecc_start()
391 if (priv->use_hecc1int) { in ti_hecc_start()
400 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_start()
414 priv->can.state = CAN_STATE_STOPPED; in ti_hecc_stop()
427 ret = -EOPNOTSUPP; in ti_hecc_do_set_mode()
439 bec->txerr = hecc_read(priv, HECC_CANTEC); in ti_hecc_get_berr_counter()
440 bec->rxerr = hecc_read(priv, HECC_CANREC); in ti_hecc_get_berr_counter()
451 * priority field the highest numbered mailbox is transmitted first.
454 * highest numbered mailbox with highest priority level and move on to the next
457 * until we reach the lowest priority level on the lowest numbered mailbox
458 * when we stop transmission until all mailboxes are transmitted and then
459 * restart at highest numbered mailbox with highest priority.
461 * Two counters (head and tail) are used to track the next mailbox to transmit
463 * is stopped when all the mailboxes are busy or when there is a priority
464 * value roll-over happens.
469 struct can_frame *cf = (struct can_frame *)skb->data; in ti_hecc_xmit()
478 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
480 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
482 netdev_err(priv->ndev, in ti_hecc_xmit()
484 priv->tx_head, priv->tx_tail); in ti_hecc_xmit()
487 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
490 data = cf->len | (get_tx_head_prio(priv) << 8); in ti_hecc_xmit()
491 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ in ti_hecc_xmit()
495 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ in ti_hecc_xmit()
496 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; in ti_hecc_xmit()
498 data = (cf->can_id & CAN_SFF_MASK) << 18; in ti_hecc_xmit()
501 be32_to_cpu(*(__be32 *)(cf->data))); in ti_hecc_xmit()
502 if (cf->len > 4) in ti_hecc_xmit()
504 be32_to_cpu(*(__be32 *)(cf->data + 4))); in ti_hecc_xmit()
506 *(u32 *)(cf->data + 4) = 0; in ti_hecc_xmit()
509 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
510 --priv->tx_head; in ti_hecc_xmit()
512 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { in ti_hecc_xmit()
516 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
541 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
545 skb = alloc_can_skb(offload->dev, &cf); in ti_hecc_mailbox_read()
547 skb = ERR_PTR(-ENOMEM); in ti_hecc_mailbox_read()
553 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; in ti_hecc_mailbox_read()
555 cf->can_id = (data >> 18) & CAN_SFF_MASK; in ti_hecc_mailbox_read()
559 cf->can_id |= CAN_RTR_FLAG; in ti_hecc_mailbox_read()
560 cf->len = can_cc_dlc2len(data & 0xF); in ti_hecc_mailbox_read()
563 *(__be32 *)(cf->data) = cpu_to_be32(data); in ti_hecc_mailbox_read()
564 if (cf->len > 4) { in ti_hecc_mailbox_read()
566 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); in ti_hecc_mailbox_read()
581 * Return an error to let rx-offload discard this CAN frame. in ti_hecc_mailbox_read()
585 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
607 netdev_err(priv->ndev, in ti_hecc_error()
610 return -ENOMEM; in ti_hecc_error()
613 ++priv->can.can_stats.bus_error; in ti_hecc_error()
614 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; in ti_hecc_error()
616 cf->data[2] |= CAN_ERR_PROT_FORM; in ti_hecc_error()
618 cf->data[2] |= CAN_ERR_PROT_BIT; in ti_hecc_error()
620 cf->data[2] |= CAN_ERR_PROT_STUFF; in ti_hecc_error()
622 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in ti_hecc_error()
624 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in ti_hecc_error()
627 err = can_rx_offload_queue_timestamp(&priv->offload, skb, in ti_hecc_error()
630 ndev->stats.rx_fifo_errors++; in ti_hecc_error()
648 skb = alloc_can_err_skb(priv->ndev, &cf); in ti_hecc_change_state()
650 priv->can.state = max(tx_state, rx_state); in ti_hecc_change_state()
654 can_change_state(priv->ndev, cf, tx_state, rx_state); in ti_hecc_change_state()
657 cf->can_id |= CAN_ERR_CNT; in ti_hecc_change_state()
658 cf->data[6] = hecc_read(priv, HECC_CANTEC); in ti_hecc_change_state()
659 cf->data[7] = hecc_read(priv, HECC_CANREC); in ti_hecc_change_state()
663 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); in ti_hecc_change_state()
665 ndev->stats.rx_fifo_errors++; in ti_hecc_change_state()
672 struct net_device_stats *stats = &ndev->stats; in ti_hecc_interrupt()
678 priv->use_hecc1int ? in ti_hecc_interrupt()
697 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); in ti_hecc_interrupt()
705 netdev_dbg(priv->ndev, "Error passive interrupt\n"); in ti_hecc_interrupt()
713 netdev_dbg(priv->ndev, "Bus off interrupt\n"); in ti_hecc_interrupt()
720 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) { in ti_hecc_interrupt()
732 if (new_state < priv->can.state) { in ti_hecc_interrupt()
740 while (priv->tx_tail - priv->tx_head > 0) { in ti_hecc_interrupt()
746 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_interrupt()
748 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_interrupt()
750 stats->tx_bytes += in ti_hecc_interrupt()
751 can_rx_offload_get_echo_skb(&priv->offload, in ti_hecc_interrupt()
753 stats->tx_packets++; in ti_hecc_interrupt()
754 --priv->tx_tail; in ti_hecc_interrupt()
757 /* restart queue if wrap-up or if queue stalled on last pkt */ in ti_hecc_interrupt()
758 if ((priv->tx_head == priv->tx_tail && in ti_hecc_interrupt()
759 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || in ti_hecc_interrupt()
760 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && in ti_hecc_interrupt()
761 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) in ti_hecc_interrupt()
766 can_rx_offload_irq_offload_timestamp(&priv->offload, in ti_hecc_interrupt()
771 /* clear all interrupt conditions - read back to avoid spurious ints */ in ti_hecc_interrupt()
772 if (priv->use_hecc1int) { in ti_hecc_interrupt()
780 can_rx_offload_irq_finish(&priv->offload); in ti_hecc_interrupt()
790 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, in ti_hecc_open()
791 ndev->name, ndev); in ti_hecc_open()
804 free_irq(ndev->irq, ndev); in ti_hecc_open()
809 can_rx_offload_enable(&priv->offload); in ti_hecc_open()
820 can_rx_offload_disable(&priv->offload); in ti_hecc_close()
822 free_irq(ndev->irq, ndev); in ti_hecc_close()
842 .compatible = "ti,am3517-hecc",
852 struct device_node *np = pdev->dev.of_node; in ti_hecc_probe()
854 int err = -ENODEV; in ti_hecc_probe()
857 return -EINVAL; in ti_hecc_probe()
859 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); in ti_hecc_probe()
860 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in ti_hecc_probe()
861 return -EPROBE_DEFER; in ti_hecc_probe()
867 dev_err(&pdev->dev, "alloc_candev failed\n"); in ti_hecc_probe()
868 return -ENOMEM; in ti_hecc_probe()
873 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc"); in ti_hecc_probe()
874 if (IS_ERR(priv->base)) { in ti_hecc_probe()
875 dev_err(&pdev->dev, "hecc ioremap failed\n"); in ti_hecc_probe()
876 err = PTR_ERR(priv->base); in ti_hecc_probe()
880 /* handle hecc-ram memory */ in ti_hecc_probe()
881 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev, in ti_hecc_probe()
882 "hecc-ram"); in ti_hecc_probe()
883 if (IS_ERR(priv->hecc_ram)) { in ti_hecc_probe()
884 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); in ti_hecc_probe()
885 err = PTR_ERR(priv->hecc_ram); in ti_hecc_probe()
890 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx"); in ti_hecc_probe()
891 if (IS_ERR(priv->mbx)) { in ti_hecc_probe()
892 dev_err(&pdev->dev, "mbx ioremap failed\n"); in ti_hecc_probe()
893 err = PTR_ERR(priv->mbx); in ti_hecc_probe()
897 ndev->irq = platform_get_irq(pdev, 0); in ti_hecc_probe()
898 if (ndev->irq < 0) { in ti_hecc_probe()
899 err = ndev->irq; in ti_hecc_probe()
903 priv->ndev = ndev; in ti_hecc_probe()
904 priv->reg_xceiver = reg_xceiver; in ti_hecc_probe()
905 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); in ti_hecc_probe()
907 priv->can.bittiming_const = &ti_hecc_bittiming_const; in ti_hecc_probe()
908 priv->can.do_set_mode = ti_hecc_do_set_mode; in ti_hecc_probe()
909 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; in ti_hecc_probe()
910 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; in ti_hecc_probe()
912 spin_lock_init(&priv->mbx_lock); in ti_hecc_probe()
913 ndev->flags |= IFF_ECHO; in ti_hecc_probe()
915 SET_NETDEV_DEV(ndev, &pdev->dev); in ti_hecc_probe()
916 ndev->netdev_ops = &ti_hecc_netdev_ops; in ti_hecc_probe()
917 ndev->ethtool_ops = &ti_hecc_ethtool_ops; in ti_hecc_probe()
919 priv->clk = clk_get(&pdev->dev, "hecc_ck"); in ti_hecc_probe()
920 if (IS_ERR(priv->clk)) { in ti_hecc_probe()
921 dev_err(&pdev->dev, "No clock available\n"); in ti_hecc_probe()
922 err = PTR_ERR(priv->clk); in ti_hecc_probe()
923 priv->clk = NULL; in ti_hecc_probe()
926 priv->can.clock.freq = clk_get_rate(priv->clk); in ti_hecc_probe()
928 err = clk_prepare_enable(priv->clk); in ti_hecc_probe()
930 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); in ti_hecc_probe()
934 priv->offload.mailbox_read = ti_hecc_mailbox_read; in ti_hecc_probe()
935 priv->offload.mb_first = HECC_RX_FIRST_MBOX; in ti_hecc_probe()
936 priv->offload.mb_last = HECC_RX_LAST_MBOX; in ti_hecc_probe()
937 err = can_rx_offload_add_timestamp(ndev, &priv->offload); in ti_hecc_probe()
939 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); in ti_hecc_probe()
945 dev_err(&pdev->dev, "register_candev() failed\n"); in ti_hecc_probe()
949 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", in ti_hecc_probe()
950 priv->base, (u32)ndev->irq); in ti_hecc_probe()
955 can_rx_offload_del(&priv->offload); in ti_hecc_probe()
957 clk_disable_unprepare(priv->clk); in ti_hecc_probe()
959 clk_put(priv->clk); in ti_hecc_probe()
972 clk_disable_unprepare(priv->clk); in ti_hecc_remove()
973 clk_put(priv->clk); in ti_hecc_remove()
974 can_rx_offload_del(&priv->offload); in ti_hecc_remove()
992 priv->can.state = CAN_STATE_SLEEPING; in ti_hecc_suspend()
994 clk_disable_unprepare(priv->clk); in ti_hecc_suspend()
1005 err = clk_prepare_enable(priv->clk); in ti_hecc_resume()
1010 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_resume()