Lines Matching +full:64 +full:- +full:byte
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
50 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_en()
58 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_octal_dtr_en()
62 nor->read_dummy = 24; in cypress_nor_octal_dtr_en()
69 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_octal_dtr_en()
76 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_en()
80 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_en()
81 return -EINVAL; in cypress_nor_octal_dtr_en()
89 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_dis()
93 * The register is 1-byte wide, but 1-byte transactions are not allowed in cypress_nor_octal_dtr_dis()
94 * in 8D-8D-8D mode. Since there is no register at the next location, in cypress_nor_octal_dtr_dis()
108 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_dis()
112 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_dis()
113 return -EINVAL; in cypress_nor_octal_dtr_dis()
119 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
124 * to a risk of the non-volatile registers corruption by power interrupt. This
126 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
128 * also set during Flash power-up.
130 * Return: 0 on success, -errno otherwise.
135 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in cypress_nor_quad_enable_volatile()
142 nor->bouncebuf); in cypress_nor_quad_enable_volatile()
144 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile()
148 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN) in cypress_nor_quad_enable_volatile()
152 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN; in cypress_nor_quad_enable_volatile()
156 nor->bouncebuf); in cypress_nor_quad_enable_volatile()
157 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile()
161 cfr1v_written = nor->bouncebuf[0]; in cypress_nor_quad_enable_volatile()
167 nor->bouncebuf); in cypress_nor_quad_enable_volatile()
168 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile()
172 if (nor->bouncebuf[0] != cfr1v_written) { in cypress_nor_quad_enable_volatile()
173 dev_err(nor->dev, "CFR1: Read back test failed\n"); in cypress_nor_quad_enable_volatile()
174 return -EIO; in cypress_nor_quad_enable_volatile()
181 * cypress_nor_set_page_size() - Set page size which corresponds to the flash
189 * Return: 0 on success, -errno otherwise.
195 nor->bouncebuf); in cypress_nor_set_page_size()
198 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_set_page_size()
202 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) in cypress_nor_set_page_size()
203 nor->params->page_size = 512; in cypress_nor_set_page_size()
205 nor->params->page_size = 256; in cypress_nor_set_page_size()
216 nor->params->quad_enable = cypress_nor_quad_enable_volatile; in s25hx_t_post_bfpt_fixup()
224 nor->params->erase_map.erase_type; in s25hx_t_post_sfdp_fixup()
228 * In some parts, 3byte erase opcodes are advertised by 4BAIT. in s25hx_t_post_sfdp_fixup()
229 * Convert them to 4byte erase opcodes. in s25hx_t_post_sfdp_fixup()
247 struct spi_nor_flash_parameter *params = nor->params; in s25hx_t_late_init()
250 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; in s25hx_t_late_init()
253 params->writesize = 16; in s25hx_t_late_init()
263 * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
270 * Return: 0 on success, -errno otherwise.
280 nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; in s28hs512t_default_init()
281 nor->params->writesize = 16; in s28hs512t_default_init()
288 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. in s28hs512t_post_sfdp_fixup()
290 if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) in s28hs512t_post_sfdp_fixup()
291 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = in s28hs512t_post_sfdp_fixup()
294 /* This flash is also missing the 4-byte Page Program opcode bit. */ in s28hs512t_post_sfdp_fixup()
295 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], in s28hs512t_post_sfdp_fixup()
301 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], in s28hs512t_post_sfdp_fixup()
309 nor->params->rdsr_addr_nbytes = 4; in s28hs512t_post_sfdp_fixup()
331 * The S25FS-S chip family reports 512-byte pages in BFPT but in s25fs_s_nor_post_bfpt_fixups()
336 nor->params->page_size = 256; in s25fs_s_nor_post_bfpt_fixups()
346 /* Spansion/Cypress -- single (large) sector size only, at least
349 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
351 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
353 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
357 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
366 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
375 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
383 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
391 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
392 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
393 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
397 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
401 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
402 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
403 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
404 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
405 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
406 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
409 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
412 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
415 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
418 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
421 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
423 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
425 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
427 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
429 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
432 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
435 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
464 * spansion_nor_clear_sr() - Clear the Status Register.
471 if (nor->spimem) { in spansion_nor_clear_sr()
474 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spansion_nor_clear_sr()
476 ret = spi_mem_exec_op(nor->spimem, &op); in spansion_nor_clear_sr()
483 dev_dbg(nor->dev, "error %d clearing SR\n", ret); in spansion_nor_clear_sr()
487 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
491 * Return: 1 if ready, 0 if not ready, -errno on errors.
497 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spansion_nor_sr_ready_and_clear()
501 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in spansion_nor_sr_ready_and_clear()
502 if (nor->bouncebuf[0] & SR_E_ERR) in spansion_nor_sr_ready_and_clear()
503 dev_err(nor->dev, "Erase Error occurred\n"); in spansion_nor_sr_ready_and_clear()
505 dev_err(nor->dev, "Programming Error occurred\n"); in spansion_nor_sr_ready_and_clear()
519 return -EIO; in spansion_nor_sr_ready_and_clear()
522 return !(nor->bouncebuf[0] & SR_WIP); in spansion_nor_sr_ready_and_clear()
527 if (nor->params->size > SZ_16M) { in spansion_nor_late_init()
528 nor->flags |= SNOR_F_4B_OPCODES; in spansion_nor_late_init()
529 /* No small sector erase for 4-byte command set */ in spansion_nor_late_init()
530 nor->erase_opcode = SPINOR_OP_SE; in spansion_nor_late_init()
531 nor->mtd.erasesize = nor->info->sector_size; in spansion_nor_late_init()
534 if (nor->info->mfr_flags & USE_CLSR) in spansion_nor_late_init()
535 nor->params->ready = spansion_nor_sr_ready_and_clear; in spansion_nor_late_init()