Lines Matching +full:64 +full:- +full:byte
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
53 u8 *buf = nor->bouncebuf; in micron_st_nor_octal_dtr_en()
60 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in micron_st_nor_octal_dtr_en()
67 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in micron_st_nor_octal_dtr_en()
74 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); in micron_st_nor_octal_dtr_en()
78 if (memcmp(buf, nor->info->id, nor->info->id_len)) in micron_st_nor_octal_dtr_en()
79 return -EINVAL; in micron_st_nor_octal_dtr_en()
87 u8 *buf = nor->bouncebuf; in micron_st_nor_octal_dtr_dis()
91 * The register is 1-byte wide, but 1-byte transactions are not allowed in micron_st_nor_octal_dtr_dis()
92 * in 8D-8D-8D mode. The next register is the dummy cycle configuration in micron_st_nor_octal_dtr_dis()
95 * because the value was changed when enabling 8D-8D-8D mode, it should in micron_st_nor_octal_dtr_dis()
109 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); in micron_st_nor_octal_dtr_dis()
113 if (memcmp(buf, nor->info->id, nor->info->id_len)) in micron_st_nor_octal_dtr_dis()
114 return -EINVAL; in micron_st_nor_octal_dtr_dis()
127 nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable; in mt35xu512aba_default_init()
133 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; in mt35xu512aba_post_sfdp_fixup()
134 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], in mt35xu512aba_post_sfdp_fixup()
138 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; in mt35xu512aba_post_sfdp_fixup()
139 nor->params->rdsr_dummy = 8; in mt35xu512aba_post_sfdp_fixup()
140 nor->params->rdsr_addr_nbytes = 0; in mt35xu512aba_post_sfdp_fixup()
147 nor->params->quad_enable = NULL; in mt35xu512aba_post_sfdp_fixup()
171 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
173 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
175 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64)
177 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
179 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
181 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
187 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
193 { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
198 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
203 { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
208 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
212 { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
217 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
223 { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
228 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
234 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
240 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
245 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
250 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
259 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) },
260 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) },
261 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) },
262 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) },
263 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) },
264 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) },
265 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) },
267 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2) },
268 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4) },
269 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4) },
270 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8) },
271 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16) },
272 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32) },
273 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64) },
274 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128) },
275 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64) },
277 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) },
278 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) },
279 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) },
281 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) },
282 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) },
283 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32)
286 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32)
288 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64)
290 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64)
292 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64)
294 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) },
295 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) },
299 * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and
302 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
305 * Return: 0 on success, -errno otherwise.
323 * micron_st_nor_read_fsr() - Read the Flag Status Register.
325 * @fsr: pointer to a DMA-able buffer where the value of the
329 * Return: 0 on success, -errno otherwise.
335 if (nor->spimem) { in micron_st_nor_read_fsr()
338 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { in micron_st_nor_read_fsr()
339 op.addr.nbytes = nor->params->rdsr_addr_nbytes; in micron_st_nor_read_fsr()
340 op.dummy.nbytes = nor->params->rdsr_dummy; in micron_st_nor_read_fsr()
342 * We don't want to read only one byte in DTR mode. So, in micron_st_nor_read_fsr()
343 * read 2 and then discard the second byte. in micron_st_nor_read_fsr()
348 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in micron_st_nor_read_fsr()
350 ret = spi_mem_exec_op(nor->spimem, &op); in micron_st_nor_read_fsr()
357 dev_dbg(nor->dev, "error %d reading FSR\n", ret); in micron_st_nor_read_fsr()
363 * micron_st_nor_clear_fsr() - Clear the Flag Status Register.
370 if (nor->spimem) { in micron_st_nor_clear_fsr()
373 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in micron_st_nor_clear_fsr()
375 ret = spi_mem_exec_op(nor->spimem, &op); in micron_st_nor_clear_fsr()
382 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); in micron_st_nor_clear_fsr()
386 * micron_st_nor_ready() - Query the Status Register as well as the Flag Status
391 * Return: 1 if ready, 0 if not ready, -errno on errors.
401 ret = micron_st_nor_read_fsr(nor, nor->bouncebuf); in micron_st_nor_ready()
410 return ret == -EOPNOTSUPP ? sr_ready : ret; in micron_st_nor_ready()
413 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { in micron_st_nor_ready()
414 if (nor->bouncebuf[0] & FSR_E_ERR) in micron_st_nor_ready()
415 dev_err(nor->dev, "Erase operation failed.\n"); in micron_st_nor_ready()
417 dev_err(nor->dev, "Program operation failed.\n"); in micron_st_nor_ready()
419 if (nor->bouncebuf[0] & FSR_PT_ERR) in micron_st_nor_ready()
420 dev_err(nor->dev, in micron_st_nor_ready()
435 return -EIO; in micron_st_nor_ready()
438 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); in micron_st_nor_ready()
443 nor->flags |= SNOR_F_HAS_LOCK; in micron_st_nor_default_init()
444 nor->flags &= ~SNOR_F_HAS_16BIT_SR; in micron_st_nor_default_init()
445 nor->params->quad_enable = NULL; in micron_st_nor_default_init()
446 nor->params->set_4byte_addr_mode = micron_st_nor_set_4byte_addr_mode; in micron_st_nor_default_init()
451 if (nor->info->mfr_flags & USE_FSR) in micron_st_nor_late_init()
452 nor->params->ready = micron_st_nor_ready; in micron_st_nor_late_init()