Lines Matching +full:spba +full:- +full:bus
4 * Slightly murky pre-git history of the driver:
41 /*--------------------------------------------------------------------------*/
72 #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
73 #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
74 #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
102 /*--------------------------------------------------------------------------*/
128 /*--------------------------------------------------------------------------*/
154 tmio_iowrite8(mode, tmio->fcr + FCR_MODE); in tmio_nand_hwcontrol()
155 tmio->read_good = 0; in tmio_nand_hwcontrol()
159 tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W); in tmio_nand_hwcontrol()
166 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); in tmio_nand_dev_ready()
174 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_irq()
175 complete(&tmio->comp); in tmio_irq()
194 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); in tmio_nand_wait()
195 reinit_completion(&tmio->comp); in tmio_nand_wait()
196 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); in tmio_nand_wait()
199 timeout = wait_for_completion_timeout(&tmio->comp, in tmio_nand_wait()
203 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
204 dev_warn(&tmio->dev->dev, "still busy after 400 ms\n"); in tmio_nand_wait()
207 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
208 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); in tmio_nand_wait()
216 *The TMIO controller combines two 8-bit data bytes into one 16-bit
221 *tmio->read_good.
228 if (tmio->read_good--) in tmio_nand_read_byte()
229 return tmio->read; in tmio_nand_read_byte()
231 data = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_read_byte()
232 tmio->read = data >> 8; in tmio_nand_read_byte()
237 *The TMIO controller converts an 8-bit NAND interface to a 16-bit
238 *bus interface, so all data reads and writes must be 16-bit wide.
239 *Thus, we implement 16-bit versions of the read, write, and verify
247 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); in tmio_nand_write_buf()
254 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); in tmio_nand_read_buf()
261 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); in tmio_nand_enable_hwecc()
262 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ in tmio_nand_enable_hwecc()
263 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); in tmio_nand_enable_hwecc()
272 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); in tmio_nand_calculate_ecc()
274 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
275 ecc_code[1] = ecc; /* 000-255 LP7-0 */ in tmio_nand_calculate_ecc()
276 ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ in tmio_nand_calculate_ecc()
277 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
278 ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ in tmio_nand_calculate_ecc()
279 ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ in tmio_nand_calculate_ecc()
280 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_calculate_ecc()
281 ecc_code[3] = ecc; /* 256-511 LP15-8 */ in tmio_nand_calculate_ecc()
282 ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ in tmio_nand_calculate_ecc()
284 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); in tmio_nand_calculate_ecc()
310 if (cell->enable) { in tmio_hw_init()
311 ret = cell->enable(dev); in tmio_hw_init()
317 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); in tmio_hw_init()
319 /* (10h)BaseAddress 0x1000 spba.spba2 */ in tmio_hw_init()
320 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); in tmio_hw_init()
321 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); in tmio_hw_init()
324 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); in tmio_hw_init()
327 /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ in tmio_hw_init()
328 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); in tmio_hw_init()
331 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); in tmio_hw_init()
334 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); in tmio_hw_init()
337 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); in tmio_hw_init()
338 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); in tmio_hw_init()
339 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); in tmio_hw_init()
342 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); in tmio_hw_init()
353 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); in tmio_hw_stop()
354 if (cell->disable) in tmio_hw_stop()
355 cell->disable(dev); in tmio_hw_stop()
360 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in tmio_attach_chip()
363 chip->ecc.size = 512; in tmio_attach_chip()
364 chip->ecc.bytes = 6; in tmio_attach_chip()
365 chip->ecc.strength = 2; in tmio_attach_chip()
366 chip->ecc.hwctl = tmio_nand_enable_hwecc; in tmio_attach_chip()
367 chip->ecc.calculate = tmio_nand_calculate_ecc; in tmio_attach_chip()
368 chip->ecc.correct = tmio_nand_correct_data; in tmio_attach_chip()
379 struct tmio_nand_data *data = dev_get_platdata(&dev->dev); in tmio_probe()
391 dev_warn(&dev->dev, "NULL platform data!\n"); in tmio_probe()
394 return -EINVAL; in tmio_probe()
396 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL); in tmio_probe()
398 return -ENOMEM; in tmio_probe()
400 init_completion(&tmio->comp); in tmio_probe()
402 tmio->dev = dev; in tmio_probe()
405 nand_chip = &tmio->chip; in tmio_probe()
407 mtd->name = "tmio-nand"; in tmio_probe()
408 mtd->dev.parent = &dev->dev; in tmio_probe()
410 nand_controller_init(&tmio->controller); in tmio_probe()
411 tmio->controller.ops = &tmio_ops; in tmio_probe()
412 nand_chip->controller = &tmio->controller; in tmio_probe()
414 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr)); in tmio_probe()
415 if (!tmio->ccr) in tmio_probe()
416 return -EIO; in tmio_probe()
418 tmio->fcr_base = fcr->start & 0xfffff; in tmio_probe()
419 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr)); in tmio_probe()
420 if (!tmio->fcr) in tmio_probe()
421 return -EIO; in tmio_probe()
428 nand_chip->legacy.IO_ADDR_R = tmio->fcr; in tmio_probe()
429 nand_chip->legacy.IO_ADDR_W = tmio->fcr; in tmio_probe()
432 nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol; in tmio_probe()
433 nand_chip->legacy.dev_ready = tmio_nand_dev_ready; in tmio_probe()
434 nand_chip->legacy.read_byte = tmio_nand_read_byte; in tmio_probe()
435 nand_chip->legacy.write_buf = tmio_nand_write_buf; in tmio_probe()
436 nand_chip->legacy.read_buf = tmio_nand_read_buf; in tmio_probe()
439 nand_chip->badblock_pattern = data->badblock_pattern; in tmio_probe()
442 nand_chip->legacy.chip_delay = 15; in tmio_probe()
444 retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0, in tmio_probe()
445 dev_name(&dev->dev), tmio); in tmio_probe()
447 dev_err(&dev->dev, "request_irq error %d\n", retval); in tmio_probe()
451 tmio->irq = irq; in tmio_probe()
452 nand_chip->legacy.waitfunc = tmio_nand_wait; in tmio_probe()
461 data ? data->part_parsers : NULL, in tmio_probe()
463 data ? data->partition : NULL, in tmio_probe()
464 data ? data->num_partitions : 0); in tmio_probe()
478 struct nand_chip *chip = &tmio->chip; in tmio_remove()
493 if (cell->suspend) in tmio_suspend()
494 cell->suspend(dev); in tmio_suspend()
504 /* FIXME - is this required or merely another attack of the broken in tmio_resume()
509 if (cell->resume) in tmio_resume()
510 cell->resume(dev); in tmio_resume()
520 .driver.name = "tmio-nand",
533 MODULE_ALIAS("platform:tmio-nand");