Lines Matching full:ecc
171 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
185 /* ECC modes supported by the controller */
441 * by ECC (value in pages)
443 * by ECC (value in pages)
461 * protected by ECC
465 * of a page, consisting of all data, ecc, spare
468 * by ECC
469 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
476 * ecc/non-ecc mode for the current nand flash
483 * @use_ecc: request the controller to use ECC for the
485 * @bch_enabled: flag to tell whether BCH ECC mode is used
520 * @ecc_modes - ecc mode for NAND
735 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) in qcom_nandc_is_last_cw() argument
737 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
745 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc() local
748 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
753 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
1210 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read() local
1214 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1533 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors() local
1537 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; in parse_erase_write_errors()
1583 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_command() local
1618 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_command()
1654 * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1657 * when using RS ECC, the HW reports the same erros when reading an erased CW,
1661 * verify if the page is erased or not, and fix up the page for RS ECC by
1733 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw() local
1742 raw_cw = ecc->steps - 1; in qcom_nandc_read_cw_raw()
1749 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
1752 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in qcom_nandc_read_cw_raw()
1753 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
1754 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
1755 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
1800 * number of 0 in each CW for which ECC engine returns the uncorrectable
1802 * equal to the ecc->strength for each CW.
1810 * The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1820 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page() local
1832 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
1833 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in check_for_erased_page()
1834 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
1835 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
1843 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
1857 0, ecc->strength); in check_for_erased_page()
1871 * errors. this is equivalent to what 'ecc->correct()' would do.
1879 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors() local
1889 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
1893 if (qcom_nandc_is_last_cw(ecc, i)) { in parse_read_errors()
1894 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
1895 oob_len = ecc->steps << 2; in parse_read_errors()
1906 * Check ECC failure for each codeword. ECC failure can in parse_read_errors()
1908 * 1. If number of bitflips are greater than ECC engine in parse_read_errors()
1915 * For BCH ECC, ignore erased codeword errors, if in parse_read_errors()
1921 * For RS ECC, HW reports the erased CW by placing in parse_read_errors()
1944 * No ECC or operational errors happened. Check the number of in parse_read_errors()
1958 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
1973 * helper to perform the actual page read operation, used by ecc->read_page(),
1974 * ecc->read_oob()
1981 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc() local
1988 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
1991 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in read_page_ecc()
1992 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
1993 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
2020 * when ecc is enabled, the controller doesn't read the real in read_page_ecc()
2022 * consistent layout across RAW and ECC reads, we just in read_page_ecc()
2061 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw() local
2072 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
2073 update_rw_regs(host, 1, true, ecc->steps - 1); in copy_last_cw()
2075 config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1); in copy_last_cw()
2151 /* implements ecc->read_page() */
2171 /* implements ecc->read_page_raw() */
2177 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw() local
2184 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
2191 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
2197 /* implements ecc->read_oob() */
2202 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob() local
2212 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_oob()
2217 /* implements ecc->write_page() */
2223 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page() local
2239 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page()
2242 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
2245 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page()
2246 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
2247 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
2251 oob_size = ecc->bytes; in qcom_nandc_write_page()
2256 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
2259 * when ECC is enabled, we don't really need to write anything in qcom_nandc_write_page()
2261 * just contain ECC bytes that's written by the controller in qcom_nandc_write_page()
2265 if (qcom_nandc_is_last_cw(ecc, i)) { in qcom_nandc_write_page()
2290 /* implements ecc->write_page_raw() */
2298 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw() local
2313 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page_raw()
2316 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
2320 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
2323 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page_raw()
2324 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
2325 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
2326 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
2367 * implements ecc->write_oob()
2370 * since ECC is calculated for the combined codeword. So update the OOB from
2378 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob() local
2390 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
2398 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
2423 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad() local
2430 * the beginning of the last codeword, we don't care about reading ecc in qcom_nandc_block_bad()
2446 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
2460 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad() local
2477 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
2478 update_rw_regs(host, 1, false, ecc->steps - 1); in qcom_nandc_block_markbad()
2558 * Layout with ECC enabled:
2562 * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
2570 * . = ECC bytes
2580 * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2581 * the number of ECC bytes vary based on the ECC strength and the bus width.
2584 * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2587 * When we access a page with ECC enabled, the reserved bytes(s) are not
2592 * Layout with ECC disabled:
2596 * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
2604 * . = ECC bytes
2611 * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2615 * In order to have a consistent layout between RAW and ECC modes, we assume
2620 * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
2628 * . = ECC bytes
2630 * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2632 * b = Real bad block byte(s) (inaccessible when ECC enabled)
2634 * This layout is read as is when ECC is disabled. When ECC is enabled, the
2636 * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2637 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2645 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc() local
2651 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
2667 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free() local
2672 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
2673 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
2679 .ecc = qcom_nand_ooblayout_ecc,
2695 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip() local
2702 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2707 * Each CW has 4 available OOB bytes which will be protected with ECC in qcom_nand_attach_chip()
2708 * so remaining bytes can be used for ECC. in qcom_nand_attach_chip()
2713 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2717 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
2718 /* 8 bit ECC defaults to BCH ECC on all platforms */ in qcom_nand_attach_chip()
2733 * if the controller supports BCH for 4 bit ECC, the controller in qcom_nand_attach_chip()
2734 * uses lesser bytes for ECC. If RS is used, the ECC bytes is in qcom_nand_attach_chip()
2766 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
2768 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit in qcom_nand_attach_chip()
2769 * ECC and 12 bytes for 4 bit ECC in qcom_nand_attach_chip()
2771 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
2773 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
2774 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
2775 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
2776 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
2777 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
2778 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
2780 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
2802 * spare data with ECC too. We protect spare data by default, so we set in qcom_nand_attach_chip()
2808 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes in qcom_nand_attach_chip()
2809 * for 8 bit ECC in qcom_nand_attach_chip()
2811 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
2864 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
3148 * of a page with ECC disabled. currently, the nand_base and nand_bbt in qcom_nand_host_init_and_register()
3149 * helpers don't allow us to read BB from a nand chip with ECC in qcom_nand_host_init_and_register()