1 // SPDX-License-Identifier: GPL-2.0-or-later
6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20  * struct hynix_read_retry - read-retry data
21  * @nregs: number of register to set when applying a new read-retry mode
22  * @regs: register offsets (NAND chip dependent)
27 	int nregs;
33  * struct hynix_nand - private Hynix NAND struct
35  * @read_retry: read-retry information
42  * struct hynix_read_retry_otp - structure describing how the read-retry OTP
48  * @page: the address to pass to the READ_PAGE command. Depends on the NAND
50  * @size: size of the read-retry OTP section
53 	int nregs;
56 	int page;
57 	int size;
63 	int ret;  in hynix_nand_has_valid_jedecid()
72 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)  in hynix_nand_cmd_op()
78 		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);  in hynix_nand_cmd_op()
83 	chip->legacy.cmdfunc(chip, cmd, -1, -1);  in hynix_nand_cmd_op()
88 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)  in hynix_nand_reg_write_op()
97 		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);  in hynix_nand_reg_write_op()
102 	chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);  in hynix_nand_reg_write_op()
103 	chip->legacy.write_byte(chip, val);  in hynix_nand_reg_write_op()
108 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)  in hynix_nand_setup_read_retry()
112 	int i, ret;  in hynix_nand_setup_read_retry()
114 	values = hynix->read_retry->values +  in hynix_nand_setup_read_retry()
115 		 (retry_mode * hynix->read_retry->nregs);  in hynix_nand_setup_read_retry()
123 	 * Configure the NAND in the requested read-retry mode.  in hynix_nand_setup_read_retry()
124 	 * This is done by setting pre-defined values in internal NAND  in hynix_nand_setup_read_retry()
127 	 * The set of registers is NAND specific, and the values are either  in hynix_nand_setup_read_retry()
128 	 * predefined or extracted from an OTP area on the NAND (values are  in hynix_nand_setup_read_retry()
131 	for (i = 0; i < hynix->read_retry->nregs; i++) {  in hynix_nand_setup_read_retry()
132 		ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],  in hynix_nand_setup_read_retry()
143  * hynix_get_majority - get the value that is occurring the most in a given
151  * the read-retry parameters.
156  * Let's hope this dummy algorithm prevents us from losing the read-retry
159 static int hynix_get_majority(const u8 *in, int repeat, u8 *out)  in hynix_get_majority()
161 	int i, j, half = repeat / 2;  in hynix_get_majority()
172 		int cnt = 0;  in hynix_get_majority()
188 	return -EIO;  in hynix_get_majority()
191 static int hynix_read_rr_otp(struct nand_chip *chip,  in hynix_read_rr_otp()
195 	int i, ret;  in hynix_read_rr_otp()
205 	for (i = 0; i < info->nregs; i++) {  in hynix_read_rr_otp()
206 		ret = hynix_nand_reg_write_op(chip, info->regs[i],  in hynix_read_rr_otp()
207 					      info->values[i]);  in hynix_read_rr_otp()
230 	ret = nand_read_page_op(chip, info->page, 0, buf, info->size);  in hynix_read_rr_otp()
259 static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs,  in hynix_mlc_1xnm_rr_value()
260 				   int mode, int reg, bool inv, u8 *val)  in hynix_mlc_1xnm_rr_value()
263 	int val_offs = (mode * nregs) + reg;  in hynix_mlc_1xnm_rr_value()
264 	int set_size = nmodes * nregs;  in hynix_mlc_1xnm_rr_value()
265 	int i, ret;  in hynix_mlc_1xnm_rr_value()
268 		int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv);  in hynix_mlc_1xnm_rr_value()
287 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,  in hynix_mlc_1xnm_rr_init()
292 	int ret, i, j;  in hynix_mlc_1xnm_rr_init()
296 	buf = kmalloc(info->size, GFP_KERNEL);  in hynix_mlc_1xnm_rr_init()
298 		return -ENOMEM;  in hynix_mlc_1xnm_rr_init()
317 		ret = -ENOMEM;  in hynix_mlc_1xnm_rr_init()
323 			u8 *val = rr->values + (i * nregs);  in hynix_mlc_1xnm_rr_init()
337 	rr->nregs = nregs;  in hynix_mlc_1xnm_rr_init()
338 	rr->regs = hynix_1xnm_mlc_read_retry_regs;  in hynix_mlc_1xnm_rr_init()
339 	hynix->read_retry = rr;  in hynix_mlc_1xnm_rr_init()
340 	chip->ops.setup_read_retry = hynix_nand_setup_read_retry;  in hynix_mlc_1xnm_rr_init()
341 	chip->read_retries = nmodes;  in hynix_mlc_1xnm_rr_init()
372 static int hynix_nand_rr_init(struct nand_chip *chip)  in hynix_nand_rr_init()
374 	int i, ret = 0;  in hynix_nand_rr_init()
380 	 * We only support read-retry for 1xnm NANDs, and those NANDs all  in hynix_nand_rr_init()
384 		u8 nand_tech = chip->id.data[5] >> 4;  in hynix_nand_rr_init()
392 				 * read-retry OTP area into a normal page.  in hynix_nand_rr_init()
403 		pr_warn("failed to initialize read-retry infrastructure");  in hynix_nand_rr_init()
415 	memorg = nanddev_get_memorg(&chip->base);  in hynix_nand_extract_oobsize()
417 	oobsize = ((chip->id.data[3] >> 2) & 0x3) |  in hynix_nand_extract_oobsize()
418 		  ((chip->id.data[3] >> 4) & 0x4);  in hynix_nand_extract_oobsize()
423 			memorg->oobsize = 2048;  in hynix_nand_extract_oobsize()
426 			memorg->oobsize = 1664;  in hynix_nand_extract_oobsize()
429 			memorg->oobsize = 1024;  in hynix_nand_extract_oobsize()
432 			memorg->oobsize = 640;  in hynix_nand_extract_oobsize()
447 			memorg->oobsize = 128;  in hynix_nand_extract_oobsize()
450 			memorg->oobsize = 224;  in hynix_nand_extract_oobsize()
453 			memorg->oobsize = 448;  in hynix_nand_extract_oobsize()
456 			memorg->oobsize = 64;  in hynix_nand_extract_oobsize()
459 			memorg->oobsize = 32;  in hynix_nand_extract_oobsize()
462 			memorg->oobsize = 16;  in hynix_nand_extract_oobsize()
465 			memorg->oobsize = 640;  in hynix_nand_extract_oobsize()
488 		if (chip->id.data[1] == 0xde)  in hynix_nand_extract_oobsize()
489 			memorg->oobsize *= memorg->pagesize / SZ_8K;  in hynix_nand_extract_oobsize()
492 	mtd->oobsize = memorg->oobsize;  in hynix_nand_extract_oobsize()
498 	struct nand_device *base = &chip->base;  in hynix_nand_extract_ecc_requirements()  local
500 	u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;  in hynix_nand_extract_ecc_requirements()
541 		 * NAND technology.  in hynix_nand_extract_ecc_requirements()
543 		u8 nand_tech = chip->id.data[5] & 0x7;  in hynix_nand_extract_ecc_requirements()
572 				requirements.strength = 1 << (ecc_level - 1);  in hynix_nand_extract_ecc_requirements()
576 							(8 * (ecc_level - 5));  in hynix_nand_extract_ecc_requirements()
581 	nanddev_set_ecc_requirements(base, &requirements);  in hynix_nand_extract_ecc_requirements()
590 	if (nanddev_bits_per_cell(&chip->base) > 2)  in hynix_nand_extract_scrambling_requirements()
591 		chip->options |= NAND_NEED_SCRAMBLING;  in hynix_nand_extract_scrambling_requirements()
593 	/* And on MLC NANDs with sub-3xnm process */  in hynix_nand_extract_scrambling_requirements()
595 		nand_tech = chip->id.data[5] >> 4;  in hynix_nand_extract_scrambling_requirements()
599 			chip->options |= NAND_NEED_SCRAMBLING;  in hynix_nand_extract_scrambling_requirements()
601 		nand_tech = chip->id.data[5] & 0x7;  in hynix_nand_extract_scrambling_requirements()
605 			chip->options |= NAND_NEED_SCRAMBLING;  in hynix_nand_extract_scrambling_requirements()
616 	memorg = nanddev_get_memorg(&chip->base);  in hynix_nand_decode_id()
625 	if (chip->id.len < 6 || nand_is_slc(chip)) {  in hynix_nand_decode_id()
631 	memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);  in hynix_nand_decode_id()
632 	mtd->writesize = memorg->pagesize;  in hynix_nand_decode_id()
634 	tmp = (chip->id.data[3] >> 4) & 0x3;  in hynix_nand_decode_id()
642 	if (chip->id.data[3] & 0x80) {  in hynix_nand_decode_id()
643 		memorg->pages_per_eraseblock = (SZ_1M << tmp) /  in hynix_nand_decode_id()
644 					       memorg->pagesize;  in hynix_nand_decode_id()
645 		mtd->erasesize = SZ_1M << tmp;  in hynix_nand_decode_id()
647 		memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /  in hynix_nand_decode_id()
648 					       memorg->pagesize;  in hynix_nand_decode_id()
649 		mtd->erasesize = SZ_512K + SZ_256K;  in hynix_nand_decode_id()
651 		memorg->pages_per_eraseblock = (SZ_128K << tmp) /  in hynix_nand_decode_id()
652 					       memorg->pagesize;  in hynix_nand_decode_id()
653 		mtd->erasesize = SZ_128K << tmp;  in hynix_nand_decode_id()
659 	 * These NANDs use a different NAND ID scheme.  in hynix_nand_decode_id()
675 	kfree(hynix->read_retry);  in hynix_nand_cleanup()
680 static int
689 static int h27ucg8t2etrbc_init(struct nand_chip *chip)  in h27ucg8t2etrbc_init()
693 	chip->options |= NAND_NEED_SCRAMBLING;  in h27ucg8t2etrbc_init()
699 static int hynix_nand_init(struct nand_chip *chip)  in hynix_nand_init()
702 	int ret;  in hynix_nand_init()
705 		chip->options |= NAND_BBM_LASTPAGE;  in hynix_nand_init()
707 		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;  in hynix_nand_init()
711 		return -ENOMEM;  in hynix_nand_init()
715 	if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,  in hynix_nand_init()
716 		     sizeof("H27UCG8T2ATR-BC") - 1))  in hynix_nand_init()
717 		chip->ops.choose_interface_config =  in hynix_nand_init()
720 	if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model,  in hynix_nand_init()
721 		     sizeof("H27UCG8T2ETR-BC") - 1))  in hynix_nand_init()