Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
53 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
60 info->group = 0; in nand_pairing_dist3_get_info()
61 info->pair = (page + 1) / 2; in nand_pairing_dist3_get_info()
63 info->group = 1; in nand_pairing_dist3_get_info()
64 info->pair = (page + 1 - dist) / 2; in nand_pairing_dist3_get_info()
73 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2; in nand_pairing_dist3_get_wunit()
74 int page = info->pair * 2; in nand_pairing_dist3_get_wunit()
77 if (!info->group && !info->pair) in nand_pairing_dist3_get_wunit()
80 if (info->pair == lastpair && info->group) in nand_pairing_dist3_get_wunit()
83 if (!info->group) in nand_pairing_dist3_get_wunit()
84 page--; in nand_pairing_dist3_get_wunit()
85 else if (info->pair) in nand_pairing_dist3_get_wunit()
86 page += dist - 1; in nand_pairing_dist3_get_wunit()
88 if (page >= mtd->erasesize / mtd->writesize) in nand_pairing_dist3_get_wunit()
89 return -EINVAL; in nand_pairing_dist3_get_wunit()
105 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
107 ret = -EINVAL; in check_offs_len()
111 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
113 ret = -EINVAL; in check_offs_len()
120 * nand_extract_bits - Copy unaligned bits from one buffer to another one
140 n = min3(8 - dst_off, 8 - src_off, nbits); in nand_extract_bits()
142 tmp = (*src >> src_off) & GENMASK(n - 1, 0); in nand_extract_bits()
143 *dst &= ~GENMASK(n - 1 + dst_off, dst_off); in nand_extract_bits()
149 dst_off -= 8; in nand_extract_bits()
155 src_off -= 8; in nand_extract_bits()
158 nbits -= n; in nand_extract_bits()
164 * nand_select_target() - Select a NAND target (A.K.A. die)
165 * @chip: NAND chip object
169 * Select a NAND target so that further operations executed on @chip go to the
170 * selected NAND target.
178 if (WARN_ON(cs > nanddev_ntargets(&chip->base))) in nand_select_target()
181 chip->cur_cs = cs; in nand_select_target()
183 if (chip->legacy.select_chip) in nand_select_target()
184 chip->legacy.select_chip(chip, cs); in nand_select_target()
189 * nand_deselect_target() - Deselect the currently selected target
190 * @chip: NAND chip object
192 * Deselect the currently selected NAND target. The result of operations
197 if (chip->legacy.select_chip) in nand_deselect_target()
198 chip->legacy.select_chip(chip, -1); in nand_deselect_target()
200 chip->cur_cs = -1; in nand_deselect_target()
205 * nand_release_device - [GENERIC] release chip
206 * @chip: NAND chip object
213 mutex_unlock(&chip->controller->lock); in nand_release_device()
214 mutex_unlock(&chip->lock); in nand_release_device()
218 * nand_bbm_get_next_page - Get the next page for bad block markers
219 * @chip: NAND chip object
224 * available, -EINVAL is returned.
229 int last_page = ((mtd->erasesize - mtd->writesize) >> in nand_bbm_get_next_page()
230 chip->page_shift) & chip->pagemask; in nand_bbm_get_next_page()
234 if (page == 0 && !(chip->options & bbm_flags)) in nand_bbm_get_next_page()
236 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) in nand_bbm_get_next_page()
238 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) in nand_bbm_get_next_page()
240 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) in nand_bbm_get_next_page()
243 return -EINVAL; in nand_bbm_get_next_page()
247 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
248 * @chip: NAND chip object
259 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; in nand_block_bad()
263 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
267 bad = chip->oob_poi[chip->badblockpos]; in nand_block_bad()
269 if (likely(chip->badblockbits == 8)) in nand_block_bad()
272 res = hweight8(bad) < chip->badblockbits; in nand_block_bad()
283 * nand_region_is_secured() - Check if the region is secured
284 * @chip: NAND chip object
297 for (i = 0; i < chip->nr_secure_regions; i++) { in nand_region_is_secured()
298 const struct nand_secure_region *region = &chip->secure_regions[i]; in nand_region_is_secured()
300 if (offset + size <= region->offset || in nand_region_is_secured()
301 offset >= region->offset + region->size) in nand_region_is_secured()
304 pr_debug("%s: Region 0x%llx - 0x%llx is secured!", in nand_region_is_secured()
317 if (chip->options & NAND_NO_BBM_QUIRK) in nand_isbad_bbm()
321 if (nand_region_is_secured(chip, ofs, mtd->erasesize)) in nand_isbad_bbm()
322 return -EIO; in nand_isbad_bbm()
327 if (chip->legacy.block_bad) in nand_isbad_bbm()
328 return chip->legacy.block_bad(chip, ofs); in nand_isbad_bbm()
334 * nand_get_device - [GENERIC] Get chip for selected access
335 * @chip: NAND chip structure
343 mutex_lock(&chip->lock); in nand_get_device()
344 if (!chip->suspended) { in nand_get_device()
345 mutex_lock(&chip->controller->lock); in nand_get_device()
348 mutex_unlock(&chip->lock); in nand_get_device()
350 wait_event(chip->resume_wq, !chip->suspended); in nand_get_device()
355 * nand_check_wp - [GENERIC] check if the chip is write protected
356 * @chip: NAND chip object
367 if (chip->options & NAND_BROKEN_XD) in nand_check_wp()
379 * nand_fill_oob - [INTERN] Transfer client buffer to oob
380 * @chip: NAND chip object
395 memset(chip->oob_poi, 0xff, mtd->oobsize); in nand_fill_oob()
397 switch (ops->mode) { in nand_fill_oob()
401 memcpy(chip->oob_poi + ops->ooboffs, oob, len); in nand_fill_oob()
405 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, in nand_fill_oob()
406 ops->ooboffs, len); in nand_fill_oob()
417 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
418 * @chip: NAND chip object
422 * NAND write out-of-band.
431 __func__, (unsigned int)to, (int)ops->ooblen); in nand_do_write_oob()
436 if ((ops->ooboffs + ops->ooblen) > len) { in nand_do_write_oob()
439 return -EINVAL; in nand_do_write_oob()
443 if (nand_region_is_secured(chip, to, ops->ooblen)) in nand_do_write_oob()
444 return -EIO; in nand_do_write_oob()
446 chipnr = (int)(to >> chip->chip_shift); in nand_do_write_oob()
461 page = (int)(to >> chip->page_shift); in nand_do_write_oob()
466 return -EROFS; in nand_do_write_oob()
470 if (page == chip->pagecache.page) in nand_do_write_oob()
471 chip->pagecache.page = -1; in nand_do_write_oob()
473 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); in nand_do_write_oob()
475 if (ops->mode == MTD_OPS_RAW) in nand_do_write_oob()
476 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
478 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
485 ops->oobretlen = ops->ooblen; in nand_do_write_oob()
491 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
492 * @chip: NAND chip object
508 ops.ooboffs = chip->badblockpos; in nand_default_block_markbad()
509 if (chip->options & NAND_BUSWIDTH_16) { in nand_default_block_markbad()
521 ofs + (page_offset * mtd->writesize), in nand_default_block_markbad()
534 * nand_markbad_bbm - mark a block by updating the BBM
535 * @chip: NAND chip object
540 if (chip->legacy.block_markbad) in nand_markbad_bbm()
541 return chip->legacy.block_markbad(chip, ofs); in nand_markbad_bbm()
547 * nand_block_markbad_lowlevel - mark a block bad
548 * @chip: NAND chip object
551 * This function performs the generic NAND bad block marking steps (i.e., bad
553 * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
570 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { in nand_block_markbad_lowlevel()
576 einfo.len = 1ULL << chip->phys_erase_shift; in nand_block_markbad_lowlevel()
587 if (chip->bbt) { in nand_block_markbad_lowlevel()
594 mtd->ecc_stats.badblocks++; in nand_block_markbad_lowlevel()
600 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
610 if (!chip->bbt) in nand_block_isreserved()
617 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
618 * @chip: NAND chip object
628 if (chip->bbt) in nand_block_checkbad()
635 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
636 * @chip: NAND chip structure
639 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
640 * If that does not happen whitin the specified timeout, -ETIMEDOUT is
644 * to the NAND R/B pin.
646 * Be aware that calling this helper from an ->exec_op() implementation means
647 * ->exec_op() must be re-entrant.
649 * Return 0 if the NAND chip is ready, a negative error otherwise.
658 return -ENOTSUPP; in nand_soft_waitrdy()
671 * small jiffy fraction - possibly leading to false timeout in nand_soft_waitrdy()
701 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; in nand_soft_waitrdy()
706 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready
707 * @chip: NAND chip structure
712 * whitin the specified timeout, -ETIMEDOUT is returned.
715 * NAND R/B pin over GPIO.
727 * small jiffy fraction - possibly leading to false timeout. in nand_gpio_waitrdy()
737 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT; in nand_gpio_waitrdy()
742 * panic_nand_wait - [GENERIC] wait until the command is done
743 * @chip: NAND chip structure
754 if (chip->legacy.dev_ready) { in panic_nand_wait()
755 if (chip->legacy.dev_ready(chip)) in panic_nand_wait()
775 return (chip->parameters.supports_set_get_features && in nand_supports_get_features()
776 test_bit(addr, chip->parameters.get_feature_list)); in nand_supports_get_features()
781 return (chip->parameters.supports_set_get_features && in nand_supports_set_features()
782 test_bit(addr, chip->parameters.set_feature_list)); in nand_supports_set_features()
786 * nand_reset_interface - Reset data interface and timings
787 * @chip: The NAND chip
796 const struct nand_controller_ops *ops = chip->controller->ops; in nand_reset_interface()
805 * To transition from NV-DDR or NV-DDR2 to the SDR data in nand_reset_interface()
816 chip->current_interface_config = nand_get_reset_interface_config(); in nand_reset_interface()
817 ret = ops->setup_interface(chip, chipnr, in nand_reset_interface()
818 chip->current_interface_config); in nand_reset_interface()
826 * nand_setup_interface - Setup the best data interface and timings
827 * @chip: The NAND chip
830 * Configure what has been reported to be the best data interface and NAND
837 const struct nand_controller_ops *ops = chip->controller->ops; in nand_setup_interface()
845 * A nand_reset_interface() put both the NAND chip and the NAND in nand_setup_interface()
848 * nand_setup_interface() uses ->set/get_features() which would in nand_setup_interface()
851 if (!chip->best_interface_config) in nand_setup_interface()
854 request = chip->best_interface_config->timings.mode; in nand_setup_interface()
855 if (nand_interface_is_sdr(chip->best_interface_config)) in nand_setup_interface()
861 /* Change the mode on the chip side (if supported by the NAND chip) */ in nand_setup_interface()
872 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config); in nand_setup_interface()
889 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n", in nand_setup_interface()
890 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR", in nand_setup_interface()
891 chip->best_interface_config->timings.mode); in nand_setup_interface()
892 pr_debug("NAND chip would work in %s timing mode %d\n", in nand_setup_interface()
893 tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR", in nand_setup_interface()
899 chip->current_interface_config = chip->best_interface_config; in nand_setup_interface()
917 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
918 * NAND controller and the NAND chip support
919 * @chip: the NAND chip
930 const struct nand_controller_ops *ops = chip->controller->ops; in nand_choose_best_sdr_timings()
931 int best_mode = 0, mode, ret = -EOPNOTSUPP; in nand_choose_best_sdr_timings()
933 iface->type = NAND_SDR_IFACE; in nand_choose_best_sdr_timings()
936 iface->timings.sdr = *spec_timings; in nand_choose_best_sdr_timings()
937 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings); in nand_choose_best_sdr_timings()
940 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_sdr_timings()
943 chip->best_interface_config = iface; in nand_choose_best_sdr_timings()
948 best_mode = iface->timings.mode; in nand_choose_best_sdr_timings()
949 } else if (chip->parameters.onfi) { in nand_choose_best_sdr_timings()
950 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1; in nand_choose_best_sdr_timings()
953 for (mode = best_mode; mode >= 0; mode--) { in nand_choose_best_sdr_timings()
956 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_sdr_timings()
959 chip->best_interface_config = iface; in nand_choose_best_sdr_timings()
968 * nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the
969 * NAND controller and the NAND chip support
970 * @chip: the NAND chip
981 const struct nand_controller_ops *ops = chip->controller->ops; in nand_choose_best_nvddr_timings()
982 int best_mode = 0, mode, ret = -EOPNOTSUPP; in nand_choose_best_nvddr_timings()
984 iface->type = NAND_NVDDR_IFACE; in nand_choose_best_nvddr_timings()
987 iface->timings.nvddr = *spec_timings; in nand_choose_best_nvddr_timings()
988 iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings); in nand_choose_best_nvddr_timings()
991 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_nvddr_timings()
994 chip->best_interface_config = iface; in nand_choose_best_nvddr_timings()
999 best_mode = iface->timings.mode; in nand_choose_best_nvddr_timings()
1000 } else if (chip->parameters.onfi) { in nand_choose_best_nvddr_timings()
1001 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1; in nand_choose_best_nvddr_timings()
1004 for (mode = best_mode; mode >= 0; mode--) { in nand_choose_best_nvddr_timings()
1007 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_nvddr_timings()
1010 chip->best_interface_config = iface; in nand_choose_best_nvddr_timings()
1019 * nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both
1020 * NAND controller and the NAND chip support
1021 * @chip: the NAND chip
1032 /* Try the fastest timings: NV-DDR */ in nand_choose_best_timings()
1042 * nand_choose_interface_config - find the best data interface and timings
1043 * @chip: The NAND chip
1045 * Find the best data interface and NAND timings supported by the chip
1046 * and the driver. Eventually let the NAND manufacturer driver propose his own
1049 * After this function nand_chip->interface_config is initialized with the best
1064 return -ENOMEM; in nand_choose_interface_config()
1066 if (chip->ops.choose_interface_config) in nand_choose_interface_config()
1067 ret = chip->ops.choose_interface_config(chip, iface); in nand_choose_interface_config()
1078 * nand_fill_column_cycles - fill the column cycles of an address
1079 * @chip: The NAND chip
1084 * on the NAND bus width and the page size.
1095 if (offset_in_page > mtd->writesize + mtd->oobsize) in nand_fill_column_cycles()
1096 return -EINVAL; in nand_fill_column_cycles()
1103 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) in nand_fill_column_cycles()
1104 offset_in_page -= mtd->writesize; in nand_fill_column_cycles()
1107 * The offset in page is expressed in bytes, if the NAND bus is 16-bit in nand_fill_column_cycles()
1110 if (chip->options & NAND_BUSWIDTH_16) { in nand_fill_column_cycles()
1112 return -EINVAL; in nand_fill_column_cycles()
1123 if (mtd->writesize <= 512) in nand_fill_column_cycles()
1146 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_sp_exec_read_page_op()
1151 op.ninstrs--; in nand_sp_exec_read_page_op()
1153 if (offset_in_page >= mtd->writesize) in nand_sp_exec_read_page_op()
1156 !(chip->options & NAND_BUSWIDTH_16)) in nand_sp_exec_read_page_op()
1166 if (chip->options & NAND_ROW_ADDR_3) { in nand_sp_exec_read_page_op()
1189 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_lp_exec_read_page_op()
1194 op.ninstrs--; in nand_lp_exec_read_page_op()
1203 if (chip->options & NAND_ROW_ADDR_3) { in nand_lp_exec_read_page_op()
1212 * nand_read_page_op - Do a READ PAGE operation
1213 * @chip: The NAND chip
1230 return -EINVAL; in nand_read_page_op()
1232 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_read_page_op()
1233 return -EINVAL; in nand_read_page_op()
1236 if (mtd->writesize > 512) in nand_read_page_op()
1245 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page); in nand_read_page_op()
1247 chip->legacy.read_buf(chip, buf, len); in nand_read_page_op()
1254 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1255 * @chip: The NAND chip
1272 return -EINVAL; in nand_read_param_page_op()
1285 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_read_param_page_op()
1289 op.ninstrs--; in nand_read_param_page_op()
1294 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1); in nand_read_param_page_op()
1296 p[i] = chip->legacy.read_byte(chip); in nand_read_param_page_op()
1302 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1303 * @chip: The NAND chip
1307 * @force_8bit: force 8-bit bus access
1321 return -EINVAL; in nand_change_read_column_op()
1323 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_change_read_column_op()
1324 return -EINVAL; in nand_change_read_column_op()
1327 if (mtd->writesize <= 512) in nand_change_read_column_op()
1328 return -ENOTSUPP; in nand_change_read_column_op()
1341 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_change_read_column_op()
1350 op.ninstrs--; in nand_change_read_column_op()
1357 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1); in nand_change_read_column_op()
1359 chip->legacy.read_buf(chip, buf, len); in nand_change_read_column_op()
1366 * nand_read_oob_op - Do a READ OOB operation
1367 * @chip: The NAND chip
1384 return -EINVAL; in nand_read_oob_op()
1386 if (offset_in_oob + len > mtd->oobsize) in nand_read_oob_op()
1387 return -EINVAL; in nand_read_oob_op()
1391 mtd->writesize + offset_in_oob, in nand_read_oob_op()
1394 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page); in nand_read_oob_op()
1396 chip->legacy.read_buf(chip, buf, len); in nand_read_oob_op()
1413 * with a large page NAND and adjusted if we're dealing in nand_exec_prog_page_op()
1414 * with a small page NAND and the page offset is > 255. in nand_exec_prog_page_op()
1424 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_exec_prog_page_op()
1432 if (chip->options & NAND_ROW_ADDR_3) in nand_exec_prog_page_op()
1439 op.ninstrs -= 2; in nand_exec_prog_page_op()
1442 op.ninstrs--; in nand_exec_prog_page_op()
1445 if (mtd->writesize <= 512) { in nand_exec_prog_page_op()
1451 if (offset_in_page >= mtd->writesize) in nand_exec_prog_page_op()
1454 !(chip->options & NAND_BUSWIDTH_16)) in nand_exec_prog_page_op()
1459 * NAND. in nand_exec_prog_page_op()
1462 op.ninstrs--; in nand_exec_prog_page_op()
1469 * nand_prog_page_begin_op - starts a PROG PAGE operation
1470 * @chip: The NAND chip
1488 return -EINVAL; in nand_prog_page_begin_op()
1490 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_prog_page_begin_op()
1491 return -EINVAL; in nand_prog_page_begin_op()
1497 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page); in nand_prog_page_begin_op()
1500 chip->legacy.write_buf(chip, buf, len); in nand_prog_page_begin_op()
1507 * nand_prog_page_end_op - ends a PROG PAGE operation
1508 * @chip: The NAND chip
1529 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_prog_page_end_op()
1539 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); in nand_prog_page_end_op()
1540 ret = chip->legacy.waitfunc(chip); in nand_prog_page_end_op()
1548 return -EIO; in nand_prog_page_end_op()
1555 * nand_prog_page_op - Do a full PROG PAGE operation
1556 * @chip: The NAND chip
1576 return -EINVAL; in nand_prog_page_op()
1578 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_prog_page_op()
1579 return -EINVAL; in nand_prog_page_op()
1591 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, in nand_prog_page_op()
1593 chip->legacy.write_buf(chip, buf, len); in nand_prog_page_op()
1594 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); in nand_prog_page_op()
1595 ret = chip->legacy.waitfunc(chip); in nand_prog_page_op()
1603 return -EIO; in nand_prog_page_op()
1610 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1611 * @chip: The NAND chip
1613 * @buf: buffer containing the data to send to the NAND
1615 * @force_8bit: force 8-bit bus access
1630 return -EINVAL; in nand_change_write_column_op()
1632 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_change_write_column_op()
1633 return -EINVAL; in nand_change_write_column_op()
1636 if (mtd->writesize <= 512) in nand_change_write_column_op()
1637 return -ENOTSUPP; in nand_change_write_column_op()
1648 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_change_write_column_op()
1659 op.ninstrs--; in nand_change_write_column_op()
1664 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1); in nand_change_write_column_op()
1666 chip->legacy.write_buf(chip, buf, len); in nand_change_write_column_op()
1673 * nand_readid_op - Do a READID operation
1674 * @chip: The NAND chip
1680 * NAND.
1692 return -EINVAL; in nand_readid_op()
1703 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_readid_op()
1706 /* READ_ID data bytes are received twice in NV-DDR mode */ in nand_readid_op()
1710 return -ENOMEM; in nand_readid_op()
1718 op.ninstrs--; in nand_readid_op()
1731 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1); in nand_readid_op()
1734 id[i] = chip->legacy.read_byte(chip); in nand_readid_op()
1741 * nand_status_op - Do a STATUS operation
1742 * @chip: The NAND chip
1743 * @status: out variable to store the NAND status
1746 * the NAND.
1762 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_status_op()
1765 /* The status data byte will be received twice in NV-DDR mode */ in nand_status_op()
1772 op.ninstrs--; in nand_status_op()
1781 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1); in nand_status_op()
1783 *status = chip->legacy.read_byte(chip); in nand_status_op()
1790 * nand_exit_status_op - Exit a STATUS operation
1791 * @chip: The NAND chip
1806 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_exit_status_op()
1811 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1); in nand_exit_status_op()
1817 * nand_erase_op - Do an erase operation
1818 * @chip: The NAND chip
1821 * This function sends an ERASE command and waits for the NAND to be ready
1830 (chip->phys_erase_shift - chip->page_shift); in nand_erase_op()
1846 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_erase_op()
1848 if (chip->options & NAND_ROW_ADDR_3) in nand_erase_op()
1859 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page); in nand_erase_op()
1860 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1); in nand_erase_op()
1862 ret = chip->legacy.waitfunc(chip); in nand_erase_op()
1870 return -EIO; in nand_erase_op()
1877 * nand_set_features_op - Do a SET FEATURES operation
1878 * @chip: The NAND chip
1882 * This function sends a SET FEATURES command and waits for the NAND to be
1907 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_set_features_op()
1912 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1); in nand_set_features_op()
1914 chip->legacy.write_byte(chip, params[i]); in nand_set_features_op()
1916 ret = chip->legacy.waitfunc(chip); in nand_set_features_op()
1921 return -EIO; in nand_set_features_op()
1927 * nand_get_features_op - Do a GET FEATURES operation
1928 * @chip: The NAND chip
1932 * This function sends a GET FEATURES command and waits for the NAND to be
1956 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_get_features_op()
1959 /* GET_FEATURE data bytes are received twice in NV-DDR mode */ in nand_get_features_op()
1974 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1); in nand_get_features_op()
1976 params[i] = chip->legacy.read_byte(chip); in nand_get_features_op()
1989 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_wait_rdy_op()
1995 if (!chip->legacy.dev_ready) in nand_wait_rdy_op()
1996 udelay(chip->legacy.chip_delay); in nand_wait_rdy_op()
2004 * nand_reset_op - Do a reset operation
2005 * @chip: The NAND chip
2007 * This function sends a RESET command and waits for the NAND to be ready
2024 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_reset_op()
2029 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1); in nand_reset_op()
2036 * nand_read_data_op - Read data from the NAND
2037 * @chip: The NAND chip
2040 * @force_8bit: force 8-bit bus access
2045 * another NAND operation like nand_read_page_op().
2054 return -EINVAL; in nand_read_data_op()
2062 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_read_data_op()
2072 * case NV-DDR timings are being used the data will be received in nand_read_data_op()
2078 return -ENOMEM; in nand_read_data_op()
2111 p[i] = chip->legacy.read_byte(chip); in nand_read_data_op()
2113 chip->legacy.read_buf(chip, buf, len); in nand_read_data_op()
2121 * nand_write_data_op - Write data from the NAND
2122 * @chip: The NAND chip
2125 * @force_8bit: force 8-bit bus access
2128 * another NAND operation like nand_write_page_begin_op().
2137 return -EINVAL; in nand_write_data_op()
2143 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_write_data_op()
2155 chip->legacy.write_byte(chip, p[i]); in nand_write_data_op()
2157 chip->legacy.write_buf(chip, buf, len); in nand_write_data_op()
2165 * struct nand_op_parser_ctx - Context used by the parser
2168 * @subop: Sub-operation to be passed to the NAND controller
2170 * This structure is used by the core to split NAND operations into
2171 * sub-operations that can be handled by the NAND controller.
2180 * nand_op_parser_must_split_instr - Checks if an instruction must be split
2190 * Some NAND controllers are limited and cannot send X address cycles with a
2193 * controller-operation into two or more chunks.
2204 switch (pat->type) { in nand_op_parser_must_split_instr()
2206 if (!pat->ctx.addr.maxcycles) in nand_op_parser_must_split_instr()
2209 if (instr->ctx.addr.naddrs - *start_offset > in nand_op_parser_must_split_instr()
2210 pat->ctx.addr.maxcycles) { in nand_op_parser_must_split_instr()
2211 *start_offset += pat->ctx.addr.maxcycles; in nand_op_parser_must_split_instr()
2218 if (!pat->ctx.data.maxlen) in nand_op_parser_must_split_instr()
2221 if (instr->ctx.data.len - *start_offset > in nand_op_parser_must_split_instr()
2222 pat->ctx.data.maxlen) { in nand_op_parser_must_split_instr()
2223 *start_offset += pat->ctx.data.maxlen; in nand_op_parser_must_split_instr()
2236 * nand_op_parser_match_pat - Checks if a pattern matches the instructions
2241 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2243 * @ctx->subop is updated with the set of instructions to be passed to the
2250 unsigned int instr_offset = ctx->subop.first_instr_start_off; in nand_op_parser_match_pat()
2251 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; in nand_op_parser_match_pat()
2252 const struct nand_op_instr *instr = ctx->subop.instrs; in nand_op_parser_match_pat()
2255 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { in nand_op_parser_match_pat()
2263 if (instr->type != pat->elems[i].type) { in nand_op_parser_match_pat()
2264 if (!pat->elems[i].optional) in nand_op_parser_match_pat()
2278 if (nand_op_parser_must_split_instr(&pat->elems[i], instr, in nand_op_parser_match_pat()
2304 for (; i < pat->nelems; i++) { in nand_op_parser_match_pat()
2305 if (!pat->elems[i].optional) in nand_op_parser_match_pat()
2313 ctx->subop.ninstrs = ninstrs; in nand_op_parser_match_pat()
2314 ctx->subop.last_instr_end_off = instr_offset; in nand_op_parser_match_pat()
2326 pr_debug("executing subop (CS%d):\n", ctx->subop.cs); in nand_op_parser_trace()
2328 for (i = 0; i < ctx->ninstrs; i++) { in nand_op_parser_trace()
2329 instr = &ctx->instrs[i]; in nand_op_parser_trace()
2331 if (instr == &ctx->subop.instrs[0]) in nand_op_parser_trace()
2332 prefix = " ->"; in nand_op_parser_trace()
2336 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) in nand_op_parser_trace()
2350 if (a->subop.ninstrs < b->subop.ninstrs) in nand_op_parser_cmp_ctx()
2351 return -1; in nand_op_parser_cmp_ctx()
2352 else if (a->subop.ninstrs > b->subop.ninstrs) in nand_op_parser_cmp_ctx()
2355 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off) in nand_op_parser_cmp_ctx()
2356 return -1; in nand_op_parser_cmp_ctx()
2357 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off) in nand_op_parser_cmp_ctx()
2364 * nand_op_parser_exec_op - exec_op parser
2365 * @chip: the NAND chip
2367 * @op: the NAND operation to address
2371 * Helper function designed to ease integration of NAND controller drivers that
2374 * multiple sub-operations (if required) and pass them back to the ->exec()
2377 * NAND controller drivers should call this function from their own ->exec_op()
2383 * matching pattern->exec() hook.
2390 .subop.cs = op->cs, in nand_op_parser_exec_op()
2391 .subop.instrs = op->instrs, in nand_op_parser_exec_op()
2392 .instrs = op->instrs, in nand_op_parser_exec_op()
2393 .ninstrs = op->ninstrs, in nand_op_parser_exec_op()
2397 while (ctx.subop.instrs < op->instrs + op->ninstrs) { in nand_op_parser_exec_op()
2400 int ret, best_pattern = -1; in nand_op_parser_exec_op()
2402 for (i = 0; i < parser->npatterns; i++) { in nand_op_parser_exec_op()
2405 pattern = &parser->patterns[i]; in nand_op_parser_exec_op()
2418 pr_debug("->exec_op() parser: pattern not found!\n"); in nand_op_parser_exec_op()
2419 return -ENOTSUPP; in nand_op_parser_exec_op()
2426 pattern = &parser->patterns[best_pattern]; in nand_op_parser_exec_op()
2427 ret = pattern->exec(chip, &ctx.subop); in nand_op_parser_exec_op()
2438 ctx.subop.instrs -= 1; in nand_op_parser_exec_op()
2449 return instr && (instr->type == NAND_OP_DATA_IN_INSTR || in nand_instr_is_data()
2450 instr->type == NAND_OP_DATA_OUT_INSTR); in nand_instr_is_data()
2456 return subop && instr_idx < subop->ninstrs; in nand_subop_instr_is_valid()
2465 return subop->first_instr_start_off; in nand_subop_get_start_off()
2469 * nand_subop_get_addr_start_off - Get the start offset in an address array
2470 * @subop: The entire sub-operation
2471 * @instr_idx: Index of the instruction inside the sub-operation
2474 * ->addr.addrs field of address instructions. This is wrong as address
2483 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) in nand_subop_get_addr_start_off()
2491 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2492 * @subop: The entire sub-operation
2493 * @instr_idx: Index of the instruction inside the sub-operation
2496 * ->addr->naddrs field of a data instruction. This is wrong as instructions
2507 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) in nand_subop_get_num_addr_cyc()
2512 if (instr_idx == subop->ninstrs - 1 && in nand_subop_get_num_addr_cyc()
2513 subop->last_instr_end_off) in nand_subop_get_num_addr_cyc()
2514 end_off = subop->last_instr_end_off; in nand_subop_get_num_addr_cyc()
2516 end_off = subop->instrs[instr_idx].ctx.addr.naddrs; in nand_subop_get_num_addr_cyc()
2518 return end_off - start_off; in nand_subop_get_num_addr_cyc()
2523 * nand_subop_get_data_start_off - Get the start offset in a data array
2524 * @subop: The entire sub-operation
2525 * @instr_idx: Index of the instruction inside the sub-operation
2528 * ->data->buf.{in,out} field of data instructions. This is wrong as data
2537 !nand_instr_is_data(&subop->instrs[instr_idx]))) in nand_subop_get_data_start_off()
2545 * nand_subop_get_data_len - Get the number of bytes to retrieve
2546 * @subop: The entire sub-operation
2547 * @instr_idx: Index of the instruction inside the sub-operation
2550 * ->data->len field of a data instruction. This is wrong as data instructions
2561 !nand_instr_is_data(&subop->instrs[instr_idx]))) in nand_subop_get_data_len()
2566 if (instr_idx == subop->ninstrs - 1 && in nand_subop_get_data_len()
2567 subop->last_instr_end_off) in nand_subop_get_data_len()
2568 end_off = subop->last_instr_end_off; in nand_subop_get_data_len()
2570 end_off = subop->instrs[instr_idx].ctx.data.len; in nand_subop_get_data_len()
2572 return end_off - start_off; in nand_subop_get_data_len()
2577 * nand_reset - Reset and initialize a NAND device
2578 * @chip: The NAND chip
2596 * The CS line has to be released before we can apply the new NAND in nand_reset()
2615 * nand_get_features - wrapper to perform a GET_FEATURE
2616 * @chip: NAND chip info structure
2620 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2627 return -ENOTSUPP; in nand_get_features()
2629 if (chip->legacy.get_features) in nand_get_features()
2630 return chip->legacy.get_features(chip, addr, subfeature_param); in nand_get_features()
2636 * nand_set_features - wrapper to perform a SET_FEATURE
2637 * @chip: NAND chip info structure
2641 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2648 return -ENOTSUPP; in nand_set_features()
2650 if (chip->legacy.set_features) in nand_set_features()
2651 return chip->legacy.set_features(chip, addr, subfeature_param); in nand_set_features()
2657 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
2672 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2682 len--, bitmap++) { in nand_check_erased_buf()
2684 bitflips += BITS_PER_BYTE - weight; in nand_check_erased_buf()
2686 return -EBADMSG; in nand_check_erased_buf()
2690 len -= sizeof(long), bitmap += sizeof(long)) { in nand_check_erased_buf()
2695 bitflips += BITS_PER_LONG - weight; in nand_check_erased_buf()
2697 return -EBADMSG; in nand_check_erased_buf()
2700 for (; len > 0; len--, bitmap++) { in nand_check_erased_buf()
2702 bitflips += BITS_PER_BYTE - weight; in nand_check_erased_buf()
2704 return -EBADMSG; in nand_check_erased_buf()
2711 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2715 * @ecc: ECC buffer
2716 * @ecclen: ECC length
2721 * Check if a data buffer and its associated ECC and OOB data contains only
2728 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2729 * different from the NAND page size. When fixing bitflips, ECC engines will
2730 * report the number of errors per chunk, and the NAND core infrastructure
2736 * the payload data but also their associated ECC data, because a user might
2738 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
2741 * data are protected by the ECC engine.
2743 * extra OOB data to an ECC chunk.
2746 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2750 void *ecc, int ecclen, in nand_check_erased_ecc_chunk() argument
2761 bitflips_threshold -= data_bitflips; in nand_check_erased_ecc_chunk()
2763 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); in nand_check_erased_ecc_chunk()
2767 bitflips_threshold -= ecc_bitflips; in nand_check_erased_ecc_chunk()
2778 memset(ecc, 0xff, ecclen); in nand_check_erased_ecc_chunk()
2788 * nand_read_page_raw_notsupp - dummy read raw page function
2789 * @chip: nand chip info structure
2791 * @oob_required: caller requires OOB data read to chip->oob_poi
2794 * Returns -ENOTSUPP unconditionally.
2799 return -ENOTSUPP; in nand_read_page_raw_notsupp()
2803 * nand_read_page_raw - [INTERN] read raw page data without ecc
2804 * @chip: nand chip info structure
2806 * @oob_required: caller requires OOB data read to chip->oob_poi
2809 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2817 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); in nand_read_page_raw()
2822 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, in nand_read_page_raw()
2833 * nand_monolithic_read_page_raw - Monolithic page read in raw mode
2834 * @chip: NAND chip info structure
2836 * @oob_required: caller requires OOB data read to chip->oob_poi
2841 * eventually OOB) to be loaded in the NAND cache and sent over the
2842 * bus (from the NAND chip to the NAND controller) in a single
2851 unsigned int size = mtd->writesize; in nand_monolithic_read_page_raw()
2856 size += mtd->oobsize; in nand_monolithic_read_page_raw()
2858 if (buf != chip->data_buf) in nand_monolithic_read_page_raw()
2866 if (buf != chip->data_buf) in nand_monolithic_read_page_raw()
2867 memcpy(buf, read_buf, mtd->writesize); in nand_monolithic_read_page_raw()
2874 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2875 * @chip: nand chip info structure
2877 * @oob_required: caller requires OOB data read to chip->oob_poi
2886 int eccsize = chip->ecc.size; in nand_read_page_raw_syndrome()
2887 int eccbytes = chip->ecc.bytes; in nand_read_page_raw_syndrome()
2888 uint8_t *oob = chip->oob_poi; in nand_read_page_raw_syndrome()
2895 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome()
2902 if (chip->ecc.prepad) { in nand_read_page_raw_syndrome()
2903 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_raw_syndrome()
2908 oob += chip->ecc.prepad; in nand_read_page_raw_syndrome()
2917 if (chip->ecc.postpad) { in nand_read_page_raw_syndrome()
2918 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_raw_syndrome()
2923 oob += chip->ecc.postpad; in nand_read_page_raw_syndrome()
2927 size = mtd->oobsize - (oob - chip->oob_poi); in nand_read_page_raw_syndrome()
2938 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
2939 * @chip: nand chip info structure
2941 * @oob_required: caller requires OOB data read to chip->oob_poi
2948 int i, eccsize = chip->ecc.size, ret; in nand_read_page_swecc()
2949 int eccbytes = chip->ecc.bytes; in nand_read_page_swecc()
2950 int eccsteps = chip->ecc.steps; in nand_read_page_swecc()
2952 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_swecc()
2953 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_swecc()
2956 chip->ecc.read_page_raw(chip, buf, 1, page); in nand_read_page_swecc()
2958 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) in nand_read_page_swecc()
2959 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_swecc()
2961 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in nand_read_page_swecc()
2962 chip->ecc.total); in nand_read_page_swecc()
2966 eccsteps = chip->ecc.steps; in nand_read_page_swecc()
2969 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_swecc()
2972 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_swecc()
2974 mtd->ecc_stats.failed++; in nand_read_page_swecc()
2976 mtd->ecc_stats.corrected += stat; in nand_read_page_swecc()
2984 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
2985 * @chip: nand chip info structure
2999 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; in nand_read_subpage()
3004 /* Column address within the page aligned to ECC size (256bytes) */ in nand_read_subpage()
3005 start_step = data_offs / chip->ecc.size; in nand_read_subpage()
3006 end_step = (data_offs + readlen - 1) / chip->ecc.size; in nand_read_subpage()
3007 num_steps = end_step - start_step + 1; in nand_read_subpage()
3008 index = start_step * chip->ecc.bytes; in nand_read_subpage()
3010 /* Data size aligned to ECC ecc.size */ in nand_read_subpage()
3011 datafrag_len = num_steps * chip->ecc.size; in nand_read_subpage()
3012 eccfrag_len = num_steps * chip->ecc.bytes; in nand_read_subpage()
3014 data_col_addr = start_step * chip->ecc.size; in nand_read_subpage()
3021 /* Calculate ECC */ in nand_read_subpage()
3022 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) in nand_read_subpage()
3023 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); in nand_read_subpage()
3027 * ecc.pos. Let's make sure that there are no gaps in ECC positions. in nand_read_subpage()
3037 ret = nand_change_read_column_op(chip, mtd->writesize, in nand_read_subpage()
3038 chip->oob_poi, mtd->oobsize, in nand_read_subpage()
3044 * Send the command to read the particular ECC bytes take care in nand_read_subpage()
3047 aligned_pos = oobregion.offset & ~(busw - 1); in nand_read_subpage()
3049 if (oobregion.offset & (busw - 1)) in nand_read_subpage()
3051 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & in nand_read_subpage()
3052 (busw - 1)) in nand_read_subpage()
3056 mtd->writesize + aligned_pos, in nand_read_subpage()
3057 &chip->oob_poi[aligned_pos], in nand_read_subpage()
3063 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, in nand_read_subpage()
3064 chip->oob_poi, index, eccfrag_len); in nand_read_subpage()
3069 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { in nand_read_subpage()
3072 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], in nand_read_subpage()
3073 &chip->ecc.calc_buf[i]); in nand_read_subpage()
3074 if (stat == -EBADMSG && in nand_read_subpage()
3075 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_subpage()
3077 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_subpage()
3078 &chip->ecc.code_buf[i], in nand_read_subpage()
3079 chip->ecc.bytes, in nand_read_subpage()
3081 chip->ecc.strength); in nand_read_subpage()
3085 mtd->ecc_stats.failed++; in nand_read_subpage()
3087 mtd->ecc_stats.corrected += stat; in nand_read_subpage()
3095 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3096 * @chip: nand chip info structure
3098 * @oob_required: caller requires OOB data read to chip->oob_poi
3101 * Not for syndrome calculating ECC controllers which need a special oob layout.
3107 int i, eccsize = chip->ecc.size, ret; in nand_read_page_hwecc()
3108 int eccbytes = chip->ecc.bytes; in nand_read_page_hwecc()
3109 int eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3111 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_hwecc()
3112 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_hwecc()
3119 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_hwecc()
3120 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_hwecc()
3126 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_hwecc()
3129 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, in nand_read_page_hwecc()
3134 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in nand_read_page_hwecc()
3135 chip->ecc.total); in nand_read_page_hwecc()
3139 eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3142 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_hwecc()
3145 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_hwecc()
3146 if (stat == -EBADMSG && in nand_read_page_hwecc()
3147 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_hwecc()
3152 chip->ecc.strength); in nand_read_page_hwecc()
3156 mtd->ecc_stats.failed++; in nand_read_page_hwecc()
3158 mtd->ecc_stats.corrected += stat; in nand_read_page_hwecc()
3166 * nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC
3168 * @chip: nand chip info structure
3170 * @oob_required: caller requires OOB data read to chip->oob_poi
3173 * Hardware ECC for large page chips, which requires the ECC data to be
3180 int i, eccsize = chip->ecc.size, ret; in nand_read_page_hwecc_oob_first()
3181 int eccbytes = chip->ecc.bytes; in nand_read_page_hwecc_oob_first()
3182 int eccsteps = chip->ecc.steps; in nand_read_page_hwecc_oob_first()
3184 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_hwecc_oob_first()
3188 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in nand_read_page_hwecc_oob_first()
3197 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in nand_read_page_hwecc_oob_first()
3198 chip->ecc.total); in nand_read_page_hwecc_oob_first()
3202 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_hwecc_oob_first()
3205 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_hwecc_oob_first()
3211 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL); in nand_read_page_hwecc_oob_first()
3212 if (stat == -EBADMSG && in nand_read_page_hwecc_oob_first()
3213 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_hwecc_oob_first()
3218 chip->ecc.strength); in nand_read_page_hwecc_oob_first()
3222 mtd->ecc_stats.failed++; in nand_read_page_hwecc_oob_first()
3224 mtd->ecc_stats.corrected += stat; in nand_read_page_hwecc_oob_first()
3233 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3234 * @chip: nand chip info structure
3236 * @oob_required: caller requires OOB data read to chip->oob_poi
3246 int ret, i, eccsize = chip->ecc.size; in nand_read_page_syndrome()
3247 int eccbytes = chip->ecc.bytes; in nand_read_page_syndrome()
3248 int eccsteps = chip->ecc.steps; in nand_read_page_syndrome()
3249 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_page_syndrome()
3251 uint8_t *oob = chip->oob_poi; in nand_read_page_syndrome()
3258 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_syndrome()
3261 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_syndrome()
3267 if (chip->ecc.prepad) { in nand_read_page_syndrome()
3268 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_syndrome()
3273 oob += chip->ecc.prepad; in nand_read_page_syndrome()
3276 chip->ecc.hwctl(chip, NAND_ECC_READSYN); in nand_read_page_syndrome()
3282 stat = chip->ecc.correct(chip, p, oob, NULL); in nand_read_page_syndrome()
3286 if (chip->ecc.postpad) { in nand_read_page_syndrome()
3287 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_syndrome()
3292 oob += chip->ecc.postpad; in nand_read_page_syndrome()
3295 if (stat == -EBADMSG && in nand_read_page_syndrome()
3296 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_syndrome()
3298 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_page_syndrome()
3299 oob - eccpadbytes, in nand_read_page_syndrome()
3302 chip->ecc.strength); in nand_read_page_syndrome()
3306 mtd->ecc_stats.failed++; in nand_read_page_syndrome()
3308 mtd->ecc_stats.corrected += stat; in nand_read_page_syndrome()
3314 i = mtd->oobsize - (oob - chip->oob_poi); in nand_read_page_syndrome()
3325 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
3326 * @chip: NAND chip object
3337 switch (ops->mode) { in nand_transfer_oob()
3341 memcpy(oob, chip->oob_poi + ops->ooboffs, len); in nand_transfer_oob()
3345 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, in nand_transfer_oob()
3346 ops->ooboffs, len); in nand_transfer_oob()
3357 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3358 * @chip: NAND chip object
3362 * when there are too many bitflips in a page (i.e., ECC error). After setting
3369 if (retry_mode >= chip->read_retries) in nand_setup_read_retry()
3370 return -EINVAL; in nand_setup_read_retry()
3372 if (!chip->ops.setup_read_retry) in nand_setup_read_retry()
3373 return -EOPNOTSUPP; in nand_setup_read_retry()
3375 return chip->ops.setup_read_retry(chip, retry_mode); in nand_setup_read_retry()
3382 if (!(chip->options & NAND_NEED_READRDY)) in nand_wait_readrdy()
3390 * nand_do_read_ops - [INTERN] Read data with ECC
3391 * @chip: NAND chip object
3403 uint32_t readlen = ops->len; in nand_do_read_ops()
3404 uint32_t oobreadlen = ops->ooblen; in nand_do_read_ops()
3415 return -EIO; in nand_do_read_ops()
3417 chipnr = (int)(from >> chip->chip_shift); in nand_do_read_ops()
3420 realpage = (int)(from >> chip->page_shift); in nand_do_read_ops()
3421 page = realpage & chip->pagemask; in nand_do_read_ops()
3423 col = (int)(from & (mtd->writesize - 1)); in nand_do_read_ops()
3425 buf = ops->datbuf; in nand_do_read_ops()
3426 oob = ops->oobbuf; in nand_do_read_ops()
3430 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats; in nand_do_read_ops()
3432 bytes = min(mtd->writesize - col, readlen); in nand_do_read_ops()
3433 aligned = (bytes == mtd->writesize); in nand_do_read_ops()
3437 else if (chip->options & NAND_USES_DMA) in nand_do_read_ops()
3440 chip->buf_align); in nand_do_read_ops()
3445 if (realpage != chip->pagecache.page || oob) { in nand_do_read_ops()
3446 bufpoi = use_bounce_buf ? chip->data_buf : buf; in nand_do_read_ops()
3455 * the read methods return max bitflips per ecc step. in nand_do_read_ops()
3457 if (unlikely(ops->mode == MTD_OPS_RAW)) in nand_do_read_ops()
3458 ret = chip->ecc.read_page_raw(chip, bufpoi, in nand_do_read_ops()
3463 ret = chip->ecc.read_subpage(chip, col, bytes, in nand_do_read_ops()
3466 ret = chip->ecc.read_page(chip, bufpoi, in nand_do_read_ops()
3471 chip->pagecache.page = -1; in nand_do_read_ops()
3481 !(mtd->ecc_stats.failed - ecc_stats.failed) && in nand_do_read_ops()
3482 (ops->mode != MTD_OPS_RAW)) { in nand_do_read_ops()
3483 chip->pagecache.page = realpage; in nand_do_read_ops()
3484 chip->pagecache.bitflips = ret; in nand_do_read_ops()
3487 chip->pagecache.page = -1; in nand_do_read_ops()
3498 oobreadlen -= toread; in nand_do_read_ops()
3504 if (mtd->ecc_stats.failed - ecc_stats.failed) { in nand_do_read_ops()
3505 if (retry_mode + 1 < chip->read_retries) { in nand_do_read_ops()
3513 mtd->ecc_stats = ecc_stats; in nand_do_read_ops()
3524 memcpy(buf, chip->data_buf + col, bytes); in nand_do_read_ops()
3527 chip->pagecache.bitflips); in nand_do_read_ops()
3530 readlen -= bytes; in nand_do_read_ops()
3548 page = realpage & chip->pagemask; in nand_do_read_ops()
3558 ops->retlen = ops->len - (size_t) readlen; in nand_do_read_ops()
3560 ops->oobretlen = ops->ooblen - oobreadlen; in nand_do_read_ops()
3566 return -EBADMSG; in nand_do_read_ops()
3572 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3573 * @chip: nand chip info structure
3580 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in nand_read_oob_std()
3585 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3587 * @chip: nand chip info structure
3593 int length = mtd->oobsize; in nand_read_oob_syndrome()
3594 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_oob_syndrome()
3595 int eccsize = chip->ecc.size; in nand_read_oob_syndrome()
3596 uint8_t *bufpoi = chip->oob_poi; in nand_read_oob_syndrome()
3599 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); in nand_read_oob_syndrome()
3603 for (i = 0; i < chip->ecc.steps; i++) { in nand_read_oob_syndrome()
3608 if (mtd->writesize > 512) in nand_read_oob_syndrome()
3627 length -= toread; in nand_read_oob_syndrome()
3639 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3640 * @chip: nand chip info structure
3647 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, in nand_write_oob_std()
3648 mtd->oobsize); in nand_write_oob_std()
3653 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3654 * with syndrome - only for large page flash
3655 * @chip: nand chip info structure
3661 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_write_oob_syndrome()
3662 int eccsize = chip->ecc.size, length = mtd->oobsize; in nand_write_oob_syndrome()
3663 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; in nand_write_oob_syndrome()
3664 const uint8_t *bufpoi = chip->oob_poi; in nand_write_oob_syndrome()
3667 * data-ecc-data-ecc ... ecc-oob in nand_write_oob_syndrome()
3669 * data-pad-ecc-pad-data-pad .... ecc-pad-oob in nand_write_oob_syndrome()
3671 if (!chip->ecc.prepad && !chip->ecc.postpad) { in nand_write_oob_syndrome()
3683 if (mtd->writesize <= 512) { in nand_write_oob_syndrome()
3695 len -= num; in nand_write_oob_syndrome()
3714 length -= len; in nand_write_oob_syndrome()
3726 * nand_do_read_oob - [INTERN] NAND read out-of-band
3727 * @chip: NAND chip object
3731 * NAND read out-of-band data from the spare area.
3740 int readlen = ops->ooblen; in nand_do_read_oob()
3742 uint8_t *buf = ops->oobbuf; in nand_do_read_oob()
3750 return -EIO; in nand_do_read_oob()
3752 stats = mtd->ecc_stats; in nand_do_read_oob()
3756 chipnr = (int)(from >> chip->chip_shift); in nand_do_read_oob()
3760 realpage = (int)(from >> chip->page_shift); in nand_do_read_oob()
3761 page = realpage & chip->pagemask; in nand_do_read_oob()
3764 if (ops->mode == MTD_OPS_RAW) in nand_do_read_oob()
3765 ret = chip->ecc.read_oob_raw(chip, page); in nand_do_read_oob()
3767 ret = chip->ecc.read_oob(chip, page); in nand_do_read_oob()
3779 readlen -= len; in nand_do_read_oob()
3786 page = realpage & chip->pagemask; in nand_do_read_oob()
3796 ops->oobretlen = ops->ooblen - readlen; in nand_do_read_oob()
3801 if (mtd->ecc_stats.failed - stats.failed) in nand_do_read_oob()
3802 return -EBADMSG; in nand_do_read_oob()
3808 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3813 * NAND read data and/or out-of-band data.
3822 ops->retlen = 0; in nand_read_oob()
3824 if (ops->mode != MTD_OPS_PLACE_OOB && in nand_read_oob()
3825 ops->mode != MTD_OPS_AUTO_OOB && in nand_read_oob()
3826 ops->mode != MTD_OPS_RAW) in nand_read_oob()
3827 return -ENOTSUPP; in nand_read_oob()
3831 old_stats = mtd->ecc_stats; in nand_read_oob()
3833 if (!ops->datbuf) in nand_read_oob()
3838 if (ops->stats) { in nand_read_oob()
3839 ops->stats->uncorrectable_errors += in nand_read_oob()
3840 mtd->ecc_stats.failed - old_stats.failed; in nand_read_oob()
3841 ops->stats->corrected_bitflips += in nand_read_oob()
3842 mtd->ecc_stats.corrected - old_stats.corrected; in nand_read_oob()
3850 * nand_write_page_raw_notsupp - dummy raw page write function
3851 * @chip: nand chip info structure
3853 * @oob_required: must write chip->oob_poi to OOB
3856 * Returns -ENOTSUPP unconditionally.
3861 return -ENOTSUPP; in nand_write_page_raw_notsupp()
3865 * nand_write_page_raw - [INTERN] raw page write function
3866 * @chip: nand chip info structure
3868 * @oob_required: must write chip->oob_poi to OOB
3871 * Not for syndrome calculating ECC controllers, which use a special oob layout.
3879 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); in nand_write_page_raw()
3884 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, in nand_write_page_raw()
3895 * nand_monolithic_write_page_raw - Monolithic page write in raw mode
3896 * @chip: NAND chip info structure
3898 * @oob_required: must write chip->oob_poi to OOB
3904 * into the NAND chip arrays in a single operation. This is an
3907 * cycles on the NAND bus, and finally sends the program command to
3908 * synchronyze the NAND chip cache.
3914 unsigned int size = mtd->writesize; in nand_monolithic_write_page_raw()
3918 size += mtd->oobsize; in nand_monolithic_write_page_raw()
3920 if (buf != chip->data_buf) { in nand_monolithic_write_page_raw()
3922 memcpy(write_buf, buf, mtd->writesize); in nand_monolithic_write_page_raw()
3931 * nand_write_page_raw_syndrome - [INTERN] raw page write function
3932 * @chip: nand chip info structure
3934 * @oob_required: must write chip->oob_poi to OOB
3937 * We need a special oob layout and handling even when ECC isn't checked.
3944 int eccsize = chip->ecc.size; in nand_write_page_raw_syndrome()
3945 int eccbytes = chip->ecc.bytes; in nand_write_page_raw_syndrome()
3946 uint8_t *oob = chip->oob_poi; in nand_write_page_raw_syndrome()
3953 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_write_page_raw_syndrome()
3960 if (chip->ecc.prepad) { in nand_write_page_raw_syndrome()
3961 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_raw_syndrome()
3966 oob += chip->ecc.prepad; in nand_write_page_raw_syndrome()
3975 if (chip->ecc.postpad) { in nand_write_page_raw_syndrome()
3976 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_raw_syndrome()
3981 oob += chip->ecc.postpad; in nand_write_page_raw_syndrome()
3985 size = mtd->oobsize - (oob - chip->oob_poi); in nand_write_page_raw_syndrome()
3995 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
3996 * @chip: nand chip info structure
3998 * @oob_required: must write chip->oob_poi to OOB
4005 int i, eccsize = chip->ecc.size, ret; in nand_write_page_swecc()
4006 int eccbytes = chip->ecc.bytes; in nand_write_page_swecc()
4007 int eccsteps = chip->ecc.steps; in nand_write_page_swecc()
4008 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_swecc()
4011 /* Software ECC calculation */ in nand_write_page_swecc()
4012 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) in nand_write_page_swecc()
4013 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_swecc()
4015 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_page_swecc()
4016 chip->ecc.total); in nand_write_page_swecc()
4020 return chip->ecc.write_page_raw(chip, buf, 1, page); in nand_write_page_swecc()
4024 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
4025 * @chip: nand chip info structure
4027 * @oob_required: must write chip->oob_poi to OOB
4034 int i, eccsize = chip->ecc.size, ret; in nand_write_page_hwecc()
4035 int eccbytes = chip->ecc.bytes; in nand_write_page_hwecc()
4036 int eccsteps = chip->ecc.steps; in nand_write_page_hwecc()
4037 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_hwecc()
4044 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_write_page_hwecc()
4045 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_hwecc()
4051 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_hwecc()
4054 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_page_hwecc()
4055 chip->ecc.total); in nand_write_page_hwecc()
4059 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in nand_write_page_hwecc()
4068 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
4069 * @chip: nand chip info structure
4073 * @oob_required: must write chip->oob_poi to OOB
4081 uint8_t *oob_buf = chip->oob_poi; in nand_write_subpage_hwecc()
4082 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4083 int ecc_size = chip->ecc.size; in nand_write_subpage_hwecc()
4084 int ecc_bytes = chip->ecc.bytes; in nand_write_subpage_hwecc()
4085 int ecc_steps = chip->ecc.steps; in nand_write_subpage_hwecc()
4087 uint32_t end_step = (offset + data_len - 1) / ecc_size; in nand_write_subpage_hwecc()
4088 int oob_bytes = mtd->oobsize / ecc_steps; in nand_write_subpage_hwecc()
4097 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_subpage_hwecc()
4104 /* mask ECC of un-touched subpages by padding 0xFF */ in nand_write_subpage_hwecc()
4108 chip->ecc.calculate(chip, buf, ecc_calc); in nand_write_subpage_hwecc()
4110 /* mask OOB of un-touched subpages by padding 0xFF */ in nand_write_subpage_hwecc()
4120 /* copy calculated ECC for whole page to chip->buffer->oob */ in nand_write_subpage_hwecc()
4121 /* this include masked-value(0xFF) for unwritten subpages */ in nand_write_subpage_hwecc()
4122 ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4123 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_subpage_hwecc()
4124 chip->ecc.total); in nand_write_subpage_hwecc()
4128 /* write OOB buffer to NAND device */ in nand_write_subpage_hwecc()
4129 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in nand_write_subpage_hwecc()
4138 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4139 * @chip: nand chip info structure
4141 * @oob_required: must write chip->oob_poi to OOB
4151 int i, eccsize = chip->ecc.size; in nand_write_page_syndrome()
4152 int eccbytes = chip->ecc.bytes; in nand_write_page_syndrome()
4153 int eccsteps = chip->ecc.steps; in nand_write_page_syndrome()
4155 uint8_t *oob = chip->oob_poi; in nand_write_page_syndrome()
4162 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_write_page_syndrome()
4163 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_syndrome()
4169 if (chip->ecc.prepad) { in nand_write_page_syndrome()
4170 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_syndrome()
4175 oob += chip->ecc.prepad; in nand_write_page_syndrome()
4178 chip->ecc.calculate(chip, p, oob); in nand_write_page_syndrome()
4186 if (chip->ecc.postpad) { in nand_write_page_syndrome()
4187 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_syndrome()
4192 oob += chip->ecc.postpad; in nand_write_page_syndrome()
4197 i = mtd->oobsize - (oob - chip->oob_poi); in nand_write_page_syndrome()
4208 * nand_write_page - write one page
4209 * @chip: NAND chip descriptor
4213 * @oob_required: must write chip->oob_poi to OOB
4224 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && in nand_write_page()
4225 chip->ecc.write_subpage) in nand_write_page()
4226 subpage = offset || (data_len < mtd->writesize); in nand_write_page()
4231 status = chip->ecc.write_page_raw(chip, buf, oob_required, in nand_write_page()
4234 status = chip->ecc.write_subpage(chip, offset, data_len, buf, in nand_write_page()
4237 status = chip->ecc.write_page(chip, buf, oob_required, page); in nand_write_page()
4245 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
4248 * nand_do_write_ops - [INTERN] NAND write with ECC
4249 * @chip: NAND chip object
4253 * NAND write with ECC.
4260 uint32_t writelen = ops->len; in nand_do_write_ops()
4262 uint32_t oobwritelen = ops->ooblen; in nand_do_write_ops()
4265 uint8_t *oob = ops->oobbuf; in nand_do_write_ops()
4266 uint8_t *buf = ops->datbuf; in nand_do_write_ops()
4270 ops->retlen = 0; in nand_do_write_ops()
4275 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { in nand_do_write_ops()
4278 return -EINVAL; in nand_do_write_ops()
4283 return -EIO; in nand_do_write_ops()
4285 column = to & (mtd->writesize - 1); in nand_do_write_ops()
4287 chipnr = (int)(to >> chip->chip_shift); in nand_do_write_ops()
4292 ret = -EIO; in nand_do_write_ops()
4296 realpage = (int)(to >> chip->page_shift); in nand_do_write_ops()
4297 page = realpage & chip->pagemask; in nand_do_write_ops()
4300 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) && in nand_do_write_ops()
4301 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len)) in nand_do_write_ops()
4302 chip->pagecache.page = -1; in nand_do_write_ops()
4305 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { in nand_do_write_ops()
4306 ret = -EINVAL; in nand_do_write_ops()
4311 int bytes = mtd->writesize; in nand_do_write_ops()
4314 int part_pagewr = (column || writelen < mtd->writesize); in nand_do_write_ops()
4318 else if (chip->options & NAND_USES_DMA) in nand_do_write_ops()
4321 chip->buf_align); in nand_do_write_ops()
4333 bytes = min_t(int, bytes - column, writelen); in nand_do_write_ops()
4335 memset(wbuf, 0xff, mtd->writesize); in nand_do_write_ops()
4342 oobwritelen -= len; in nand_do_write_ops()
4345 memset(chip->oob_poi, 0xff, mtd->oobsize); in nand_do_write_ops()
4350 (ops->mode == MTD_OPS_RAW)); in nand_do_write_ops()
4354 writelen -= bytes; in nand_do_write_ops()
4362 page = realpage & chip->pagemask; in nand_do_write_ops()
4371 ops->retlen = ops->len - writelen; in nand_do_write_ops()
4373 ops->oobretlen = ops->ooblen; in nand_do_write_ops()
4381 * panic_nand_write - [MTD Interface] NAND write with ECC
4388 * NAND write with ECC. Used when performing writes in interrupt context, this
4395 int chipnr = (int)(to >> chip->chip_shift); in panic_nand_write()
4416 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4427 ops->retlen = 0; in nand_write_oob()
4431 switch (ops->mode) { in nand_write_oob()
4441 if (!ops->datbuf) in nand_write_oob()
4452 * nand_erase - [MTD Interface] erase block(s)
4464 * nand_erase_nand - [INTERN] erase block(s)
4465 * @chip: NAND chip object
4478 __func__, (unsigned long long)instr->addr, in nand_erase_nand()
4479 (unsigned long long)instr->len); in nand_erase_nand()
4481 if (check_offs_len(chip, instr->addr, instr->len)) in nand_erase_nand()
4482 return -EINVAL; in nand_erase_nand()
4485 if (nand_region_is_secured(chip, instr->addr, instr->len)) in nand_erase_nand()
4486 return -EIO; in nand_erase_nand()
4492 page = (int)(instr->addr >> chip->page_shift); in nand_erase_nand()
4493 chipnr = (int)(instr->addr >> chip->chip_shift); in nand_erase_nand()
4496 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); in nand_erase_nand()
4498 /* Select the NAND device */ in nand_erase_nand()
4505 ret = -EIO; in nand_erase_nand()
4510 len = instr->len; in nand_erase_nand()
4513 loff_t ofs = (loff_t)page << chip->page_shift; in nand_erase_nand()
4517 chip->page_shift, allowbbt)) { in nand_erase_nand()
4520 ret = -EIO; in nand_erase_nand()
4528 if (page <= chip->pagecache.page && chip->pagecache.page < in nand_erase_nand()
4530 chip->pagecache.page = -1; in nand_erase_nand()
4532 ret = nand_erase_op(chip, (page & chip->pagemask) >> in nand_erase_nand()
4533 (chip->phys_erase_shift - chip->page_shift)); in nand_erase_nand()
4537 instr->fail_addr = ofs; in nand_erase_nand()
4542 len -= (1ULL << chip->phys_erase_shift); in nand_erase_nand()
4546 if (len && !(page & chip->pagemask)) { in nand_erase_nand()
4565 * nand_sync - [MTD Interface] sync
4583 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
4590 int chipnr = (int)(offs >> chip->chip_shift); in nand_block_isbad()
4593 /* Select the NAND device */ in nand_block_isbad()
4607 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4627 * nand_suspend - [MTD Interface] Suspend the NAND flash
4637 mutex_lock(&chip->lock); in nand_suspend()
4638 if (chip->ops.suspend) in nand_suspend()
4639 ret = chip->ops.suspend(chip); in nand_suspend()
4641 chip->suspended = 1; in nand_suspend()
4642 mutex_unlock(&chip->lock); in nand_suspend()
4648 * nand_resume - [MTD Interface] Resume the NAND flash
4655 mutex_lock(&chip->lock); in nand_resume()
4656 if (chip->suspended) { in nand_resume()
4657 if (chip->ops.resume) in nand_resume()
4658 chip->ops.resume(chip); in nand_resume()
4659 chip->suspended = 0; in nand_resume()
4664 mutex_unlock(&chip->lock); in nand_resume()
4666 wake_up_all(&chip->resume_wq); in nand_resume()
4670 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
4680 * nand_lock - [MTD Interface] Lock the NAND flash
4689 if (!chip->ops.lock_area) in nand_lock()
4690 return -ENOTSUPP; in nand_lock()
4692 return chip->ops.lock_area(chip, ofs, len); in nand_lock()
4696 * nand_unlock - [MTD Interface] Unlock the NAND flash
4705 if (!chip->ops.unlock_area) in nand_unlock()
4706 return -ENOTSUPP; in nand_unlock()
4708 return chip->ops.unlock_area(chip, ofs, len); in nand_unlock()
4715 if (!chip->controller) { in nand_set_defaults()
4716 chip->controller = &chip->legacy.dummy_controller; in nand_set_defaults()
4717 nand_controller_init(chip->controller); in nand_set_defaults()
4722 if (!chip->buf_align) in nand_set_defaults()
4723 chip->buf_align = 1; in nand_set_defaults()
4732 s[len - 1] = 0; in sanitize_string()
4735 for (i = 0; i < len - 1; i++) { in sanitize_string()
4745 * nand_id_has_period - Check if an ID string has a given wraparound period
4752 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
4766 * nand_id_len - Get the length of an ID string returned by CMD_READID
4777 /* Find last non-zero byte */ in nand_id_len()
4778 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) in nand_id_len()
4796 if (last_nonzero < arrlen - 1) in nand_id_len()
4814 * Many new NAND share similar device ID codes, which represent the size of the
4816 * manufacturer-specific "extended ID" decoding patterns.
4823 u8 *id_data = chip->id.data; in nand_decode_ext_id()
4825 memorg = nanddev_get_memorg(&chip->base); in nand_decode_ext_id()
4828 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); in nand_decode_ext_id()
4833 memorg->pagesize = 1024 << (extid & 0x03); in nand_decode_ext_id()
4834 mtd->writesize = memorg->pagesize; in nand_decode_ext_id()
4837 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); in nand_decode_ext_id()
4838 mtd->oobsize = memorg->oobsize; in nand_decode_ext_id()
4841 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) / in nand_decode_ext_id()
4842 memorg->pagesize; in nand_decode_ext_id()
4843 mtd->erasesize = (64 * 1024) << (extid & 0x03); in nand_decode_ext_id()
4847 chip->options |= NAND_BUSWIDTH_16; in nand_decode_ext_id()
4861 memorg = nanddev_get_memorg(&chip->base); in nand_decode_id()
4863 memorg->pages_per_eraseblock = type->erasesize / type->pagesize; in nand_decode_id()
4864 mtd->erasesize = type->erasesize; in nand_decode_id()
4865 memorg->pagesize = type->pagesize; in nand_decode_id()
4866 mtd->writesize = memorg->pagesize; in nand_decode_id()
4867 memorg->oobsize = memorg->pagesize / 32; in nand_decode_id()
4868 mtd->oobsize = memorg->oobsize; in nand_decode_id()
4870 /* All legacy ID NAND are small-page, SLC */ in nand_decode_id()
4871 memorg->bits_per_cell = 1; in nand_decode_id()
4877 * page size, cell-type information).
4884 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) in nand_decode_bbm_options()
4885 chip->badblockpos = NAND_BBM_POS_LARGE; in nand_decode_bbm_options()
4887 chip->badblockpos = NAND_BBM_POS_SMALL; in nand_decode_bbm_options()
4892 return type->id_len; in is_full_id_nand()
4898 struct nand_device *base = &chip->base; in find_full_id_nand()
4902 u8 *id_data = chip->id.data; in find_full_id_nand()
4904 memorg = nanddev_get_memorg(&chip->base); in find_full_id_nand()
4906 if (!strncmp(type->id, id_data, type->id_len)) { in find_full_id_nand()
4907 memorg->pagesize = type->pagesize; in find_full_id_nand()
4908 mtd->writesize = memorg->pagesize; in find_full_id_nand()
4909 memorg->pages_per_eraseblock = type->erasesize / in find_full_id_nand()
4910 type->pagesize; in find_full_id_nand()
4911 mtd->erasesize = type->erasesize; in find_full_id_nand()
4912 memorg->oobsize = type->oobsize; in find_full_id_nand()
4913 mtd->oobsize = memorg->oobsize; in find_full_id_nand()
4915 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); in find_full_id_nand()
4916 memorg->eraseblocks_per_lun = in find_full_id_nand()
4917 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, in find_full_id_nand()
4918 memorg->pagesize * in find_full_id_nand()
4919 memorg->pages_per_eraseblock); in find_full_id_nand()
4920 chip->options |= type->options; in find_full_id_nand()
4921 requirements.strength = NAND_ECC_STRENGTH(type); in find_full_id_nand()
4925 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); in find_full_id_nand()
4926 if (!chip->parameters.model) in find_full_id_nand()
4935 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
4936 * compliant and does not have a full-id or legacy-id entry in the nand_ids
4945 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && in nand_manufacturer_detect()
4946 chip->manufacturer.desc->ops->detect) { in nand_manufacturer_detect()
4949 memorg = nanddev_get_memorg(&chip->base); in nand_manufacturer_detect()
4952 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); in nand_manufacturer_detect()
4953 chip->manufacturer.desc->ops->detect(chip); in nand_manufacturer_detect()
4963 * their ->init() hook.
4967 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || in nand_manufacturer_init()
4968 !chip->manufacturer.desc->ops->init) in nand_manufacturer_init()
4971 return chip->manufacturer.desc->ops->init(chip); in nand_manufacturer_init()
4978 * ->cleanup() hook.
4983 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && in nand_manufacturer_cleanup()
4984 chip->manufacturer.desc->ops->cleanup) in nand_manufacturer_cleanup()
4985 chip->manufacturer.desc->ops->cleanup(chip); in nand_manufacturer_cleanup()
4991 return manufacturer_desc ? manufacturer_desc->name : "Unknown"; in nand_manufacturer_name()
5003 u8 *id_data = chip->id.data; in nand_detect()
5009 * unassigned by the ID-based detection logic. in nand_detect()
5011 memorg = nanddev_get_memorg(&chip->base); in nand_detect()
5012 memorg->planes_per_lun = 1; in nand_detect()
5013 memorg->luns_per_target = 1; in nand_detect()
5017 * after power-up. in nand_detect()
5036 * Try again to make sure, as some systems the bus-hold or other in nand_detect()
5038 * possibly credible NAND flash to appear. If the two results do in nand_detect()
5043 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); in nand_detect()
5050 return -ENODEV; in nand_detect()
5053 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); in nand_detect()
5057 chip->manufacturer.desc = manufacturer_desc; in nand_detect()
5063 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic in nand_detect()
5065 * This is required to make sure initial NAND bus width set by the in nand_detect()
5066 * NAND controller driver is coherent with the real NAND bus width in nand_detect()
5067 * (extracted by auto-detection code). in nand_detect()
5069 busw = chip->options & NAND_BUSWIDTH_16; in nand_detect()
5073 * before starting auto-detection. in nand_detect()
5075 chip->options &= ~NAND_BUSWIDTH_16; in nand_detect()
5077 for (; type->name != NULL; type++) { in nand_detect()
5081 } else if (dev_id == type->dev_id) { in nand_detect()
5086 if (!type->name || !type->pagesize) { in nand_detect()
5102 if (!type->name) in nand_detect()
5103 return -ENODEV; in nand_detect()
5105 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); in nand_detect()
5106 if (!chip->parameters.model) in nand_detect()
5107 return -ENOMEM; in nand_detect()
5109 if (!type->pagesize) in nand_detect()
5115 chip->options |= type->options; in nand_detect()
5117 memorg->eraseblocks_per_lun = in nand_detect()
5118 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, in nand_detect()
5119 memorg->pagesize * in nand_detect()
5120 memorg->pages_per_eraseblock); in nand_detect()
5123 if (!mtd->name) in nand_detect()
5124 mtd->name = chip->parameters.model; in nand_detect()
5126 if (chip->options & NAND_BUSWIDTH_AUTO) { in nand_detect()
5129 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { in nand_detect()
5137 mtd->name); in nand_detect()
5139 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); in nand_detect()
5140 ret = -EINVAL; in nand_detect()
5148 chip->page_shift = ffs(mtd->writesize) - 1; in nand_detect()
5149 /* Convert chipsize to number of pages per chip -1 */ in nand_detect()
5150 targetsize = nanddev_target_size(&chip->base); in nand_detect()
5151 chip->pagemask = (targetsize >> chip->page_shift) - 1; in nand_detect()
5153 chip->bbt_erase_shift = chip->phys_erase_shift = in nand_detect()
5154 ffs(mtd->erasesize) - 1; in nand_detect()
5156 chip->chip_shift = ffs((unsigned)targetsize) - 1; in nand_detect()
5158 chip->chip_shift = ffs((unsigned)(targetsize >> 32)); in nand_detect()
5159 chip->chip_shift += 32 - 1; in nand_detect()
5162 if (chip->chip_shift - chip->page_shift > 16) in nand_detect()
5163 chip->options |= NAND_ROW_ADDR_3; in nand_detect()
5165 chip->badblockbits = 8; in nand_detect()
5172 chip->parameters.model); in nand_detect()
5175 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); in nand_detect()
5179 kfree(chip->parameters.model); in nand_detect()
5202 [NAND_ECC_ON_DIE] = "on-die", in of_get_rawnand_ecc_engine_type_legacy()
5208 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_engine_type_legacy()
5241 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_placement_legacy()
5255 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_algo_legacy()
5269 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; in of_get_nand_ecc_legacy_user_config()
5271 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in of_get_nand_ecc_legacy_user_config()
5272 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5274 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN) in of_get_nand_ecc_legacy_user_config()
5275 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5277 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN) in of_get_nand_ecc_legacy_user_config()
5278 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5287 ret = of_property_read_u32(dn, "nand-bus-width", &val); in of_get_nand_bus_width()
5288 if (ret == -EINVAL) in of_get_nand_bus_width()
5295 chip->options |= NAND_BUSWIDTH_16; in of_get_nand_bus_width()
5297 return -EINVAL; in of_get_nand_bus_width()
5307 /* Only proceed if the "secure-regions" property is present in DT */ in of_get_nand_secure_regions()
5308 prop = of_find_property(dn, "secure-regions", NULL); in of_get_nand_secure_regions()
5312 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64)); in of_get_nand_secure_regions()
5316 chip->nr_secure_regions = nr_elem / 2; in of_get_nand_secure_regions()
5317 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions), in of_get_nand_secure_regions()
5319 if (!chip->secure_regions) in of_get_nand_secure_regions()
5320 return -ENOMEM; in of_get_nand_secure_regions()
5322 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) { in of_get_nand_secure_regions()
5323 of_property_read_u64_index(dn, "secure-regions", j, in of_get_nand_secure_regions()
5324 &chip->secure_regions[i].offset); in of_get_nand_secure_regions()
5325 of_property_read_u64_index(dn, "secure-regions", j + 1, in of_get_nand_secure_regions()
5326 &chip->secure_regions[i].size); in of_get_nand_secure_regions()
5333 * rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller
5347 dev_dbg(dev, "No valid cs-gpios property\n"); in rawnand_dt_parse_gpio_cs()
5353 return -ENOMEM; in rawnand_dt_parse_gpio_cs()
5371 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); in rawnand_dt_init() local
5382 if (of_property_read_bool(dn, "nand-is-boot-medium")) in rawnand_dt_init()
5383 chip->options |= NAND_IS_BOOT_MEDIUM; in rawnand_dt_init()
5385 if (of_property_read_bool(dn, "nand-on-flash-bbt")) in rawnand_dt_init()
5386 chip->bbt_options |= NAND_BBT_USE_FLASH; in rawnand_dt_init()
5388 of_get_nand_ecc_user_config(nand); in rawnand_dt_init()
5392 * If neither the user nor the NAND controller have requested a specific in rawnand_dt_init()
5393 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. in rawnand_dt_init()
5395 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in rawnand_dt_init()
5399 * case default to the NAND controller choice, otherwise fallback to in rawnand_dt_init()
5400 * the raw NAND default one. in rawnand_dt_init()
5402 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5403 chip->ecc.engine_type = nand->ecc.user_conf.engine_type; in rawnand_dt_init()
5404 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5405 chip->ecc.engine_type = nand->ecc.defaults.engine_type; in rawnand_dt_init()
5407 chip->ecc.placement = nand->ecc.user_conf.placement; in rawnand_dt_init()
5408 chip->ecc.algo = nand->ecc.user_conf.algo; in rawnand_dt_init()
5409 chip->ecc.strength = nand->ecc.user_conf.strength; in rawnand_dt_init()
5410 chip->ecc.size = nand->ecc.user_conf.step_size; in rawnand_dt_init()
5416 * nand_scan_ident - Scan for the NAND device
5417 * @chip: NAND chip object
5419 * @table: alternative NAND ID table
5425 * to tweak some ECC-related parameters before nand_scan_tail(). This separation
5427 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5438 memorg = nanddev_get_memorg(&chip->base); in nand_scan_ident()
5441 chip->cur_cs = -1; in nand_scan_ident()
5443 mutex_init(&chip->lock); in nand_scan_ident()
5444 init_waitqueue_head(&chip->resume_wq); in nand_scan_ident()
5447 chip->current_interface_config = nand_get_reset_interface_config(); in nand_scan_ident()
5453 if (!mtd->name && mtd->dev.parent) in nand_scan_ident()
5454 mtd->name = dev_name(mtd->dev.parent); in nand_scan_ident()
5463 memorg->ntargets = maxchips; in nand_scan_ident()
5468 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) in nand_scan_ident()
5469 pr_warn("No NAND device found\n"); in nand_scan_ident()
5474 nand_maf_id = chip->id.data[0]; in nand_scan_ident()
5475 nand_dev_id = chip->id.data[1]; in nand_scan_ident()
5504 memorg->ntargets = i; in nand_scan_ident()
5505 mtd->size = i * nanddev_target_size(&chip->base); in nand_scan_ident()
5512 kfree(chip->parameters.model); in nand_scan_ident_cleanup()
5513 kfree(chip->parameters.onfi); in nand_scan_ident_cleanup()
5519 struct nand_device *base = &chip->base; in rawnand_sw_hamming_init()
5522 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_hamming_init()
5523 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING; in rawnand_sw_hamming_init()
5524 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_hamming_init()
5525 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_hamming_init()
5531 engine_conf = base->ecc.ctx.priv; in rawnand_sw_hamming_init()
5533 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER) in rawnand_sw_hamming_init()
5534 engine_conf->sm_order = true; in rawnand_sw_hamming_init()
5536 chip->ecc.size = base->ecc.ctx.conf.step_size; in rawnand_sw_hamming_init()
5537 chip->ecc.strength = base->ecc.ctx.conf.strength; in rawnand_sw_hamming_init()
5538 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_hamming_init()
5539 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5540 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5550 struct nand_device *base = &chip->base; in rawnand_sw_hamming_calculate()
5561 struct nand_device *base = &chip->base; in rawnand_sw_hamming_correct()
5569 struct nand_device *base = &chip->base; in rawnand_sw_hamming_cleanup()
5577 struct nand_device *base = &chip->base; in rawnand_sw_bch_init()
5581 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_bch_init()
5582 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH; in rawnand_sw_bch_init()
5583 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_bch_init()
5584 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_bch_init()
5590 chip->ecc.size = ecc_conf->step_size; in rawnand_sw_bch_init()
5591 chip->ecc.strength = ecc_conf->strength; in rawnand_sw_bch_init()
5592 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_bch_init()
5593 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5594 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5604 struct nand_device *base = &chip->base; in rawnand_sw_bch_calculate()
5612 struct nand_device *base = &chip->base; in rawnand_sw_bch_correct()
5620 struct nand_device *base = &chip->base; in rawnand_sw_bch_cleanup()
5628 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_on_host_ops() local
5630 switch (ecc->placement) { in nand_set_ecc_on_host_ops()
5634 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5635 ecc->read_page = nand_read_page_hwecc; in nand_set_ecc_on_host_ops()
5636 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5637 ecc->write_page = nand_write_page_hwecc; in nand_set_ecc_on_host_ops()
5638 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5639 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_on_host_ops()
5640 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5641 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_on_host_ops()
5642 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5643 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_on_host_ops()
5644 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5645 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_on_host_ops()
5646 if (!ecc->read_subpage) in nand_set_ecc_on_host_ops()
5647 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_on_host_ops()
5648 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) in nand_set_ecc_on_host_ops()
5649 ecc->write_subpage = nand_write_subpage_hwecc; in nand_set_ecc_on_host_ops()
5653 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && in nand_set_ecc_on_host_ops()
5654 (!ecc->read_page || in nand_set_ecc_on_host_ops()
5655 ecc->read_page == nand_read_page_hwecc || in nand_set_ecc_on_host_ops()
5656 !ecc->write_page || in nand_set_ecc_on_host_ops()
5657 ecc->write_page == nand_write_page_hwecc)) { in nand_set_ecc_on_host_ops()
5658 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); in nand_set_ecc_on_host_ops()
5659 return -EINVAL; in nand_set_ecc_on_host_ops()
5662 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5663 ecc->read_page = nand_read_page_syndrome; in nand_set_ecc_on_host_ops()
5664 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5665 ecc->write_page = nand_write_page_syndrome; in nand_set_ecc_on_host_ops()
5666 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5667 ecc->read_page_raw = nand_read_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5668 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5669 ecc->write_page_raw = nand_write_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5670 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5671 ecc->read_oob = nand_read_oob_syndrome; in nand_set_ecc_on_host_ops()
5672 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5673 ecc->write_oob = nand_write_oob_syndrome; in nand_set_ecc_on_host_ops()
5678 ecc->placement); in nand_set_ecc_on_host_ops()
5679 return -EINVAL; in nand_set_ecc_on_host_ops()
5689 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_soft_ops() local
5692 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) in nand_set_ecc_soft_ops()
5693 return -EINVAL; in nand_set_ecc_soft_ops()
5695 switch (ecc->algo) { in nand_set_ecc_soft_ops()
5697 ecc->calculate = rawnand_sw_hamming_calculate; in nand_set_ecc_soft_ops()
5698 ecc->correct = rawnand_sw_hamming_correct; in nand_set_ecc_soft_ops()
5699 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5700 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5701 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5702 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5703 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5704 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5705 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5706 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5707 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5708 if (!ecc->size) in nand_set_ecc_soft_ops()
5709 ecc->size = 256; in nand_set_ecc_soft_ops()
5710 ecc->bytes = 3; in nand_set_ecc_soft_ops()
5711 ecc->strength = 1; in nand_set_ecc_soft_ops()
5714 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; in nand_set_ecc_soft_ops()
5718 WARN(1, "Hamming ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5726 return -EINVAL; in nand_set_ecc_soft_ops()
5728 ecc->calculate = rawnand_sw_bch_calculate; in nand_set_ecc_soft_ops()
5729 ecc->correct = rawnand_sw_bch_correct; in nand_set_ecc_soft_ops()
5730 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5731 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5732 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5733 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5734 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5735 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5736 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5737 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5738 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5741 * We can only maximize ECC config when the default layout is in nand_set_ecc_soft_ops()
5745 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH && in nand_set_ecc_soft_ops()
5746 mtd->ooblayout != nand_get_large_page_ooblayout()) in nand_set_ecc_soft_ops()
5747 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH; in nand_set_ecc_soft_ops()
5751 WARN(1, "BCH ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5757 WARN(1, "Unsupported ECC algorithm!\n"); in nand_set_ecc_soft_ops()
5758 return -EINVAL; in nand_set_ecc_soft_ops()
5763 * nand_check_ecc_caps - check the sanity of preset ECC settings
5764 * @chip: nand chip info structure
5765 * @caps: ECC caps info structure
5766 * @oobavail: OOB size that the ECC engine can use
5768 * When ECC step size and strength are already set, check if they are supported
5769 * by the controller and the calculated ECC bytes fit within the chip's OOB.
5770 * On success, the calculated ECC bytes is set.
5778 int preset_step = chip->ecc.size; in nand_check_ecc_caps()
5779 int preset_strength = chip->ecc.strength; in nand_check_ecc_caps()
5780 int ecc_bytes, nsteps = mtd->writesize / preset_step; in nand_check_ecc_caps()
5783 for (i = 0; i < caps->nstepinfos; i++) { in nand_check_ecc_caps()
5784 stepinfo = &caps->stepinfos[i]; in nand_check_ecc_caps()
5786 if (stepinfo->stepsize != preset_step) in nand_check_ecc_caps()
5789 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_check_ecc_caps()
5790 if (stepinfo->strengths[j] != preset_strength) in nand_check_ecc_caps()
5793 ecc_bytes = caps->calc_ecc_bytes(preset_step, in nand_check_ecc_caps()
5799 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", in nand_check_ecc_caps()
5801 return -ENOSPC; in nand_check_ecc_caps()
5804 chip->ecc.bytes = ecc_bytes; in nand_check_ecc_caps()
5810 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", in nand_check_ecc_caps()
5813 return -ENOTSUPP; in nand_check_ecc_caps()
5817 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
5818 * @chip: nand chip info structure
5819 * @caps: ECC engine caps info structure
5820 * @oobavail: OOB size that the ECC engine can use
5822 * If a chip's ECC requirement is provided, try to meet it with the least
5823 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
5824 * On success, the chosen ECC settings are set.
5831 nanddev_get_ecc_requirements(&chip->base); in nand_match_ecc_req()
5834 int req_step = requirements->step_size; in nand_match_ecc_req()
5835 int req_strength = requirements->strength; in nand_match_ecc_req()
5836 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; in nand_match_ecc_req() local
5841 /* No information provided by the NAND chip */ in nand_match_ecc_req()
5843 return -ENOTSUPP; in nand_match_ecc_req()
5846 req_corr = mtd->writesize / req_step * req_strength; in nand_match_ecc_req()
5848 for (i = 0; i < caps->nstepinfos; i++) { in nand_match_ecc_req()
5849 stepinfo = &caps->stepinfos[i]; in nand_match_ecc_req()
5850 step_size = stepinfo->stepsize; in nand_match_ecc_req()
5852 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_match_ecc_req()
5853 strength = stepinfo->strengths[j]; in nand_match_ecc_req()
5856 * If both step size and strength are smaller than the in nand_match_ecc_req()
5860 if (step_size < req_step && strength < req_strength) in nand_match_ecc_req()
5863 if (mtd->writesize % step_size) in nand_match_ecc_req()
5866 nsteps = mtd->writesize / step_size; in nand_match_ecc_req()
5868 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); in nand_match_ecc_req()
5874 strength * nsteps < req_corr) in nand_match_ecc_req()
5879 * with the least number of ECC bytes. in nand_match_ecc_req()
5884 best_strength = strength; in nand_match_ecc_req()
5891 return -ENOTSUPP; in nand_match_ecc_req()
5893 chip->ecc.size = best_step; in nand_match_ecc_req()
5894 chip->ecc.strength = best_strength; in nand_match_ecc_req()
5895 chip->ecc.bytes = best_ecc_bytes; in nand_match_ecc_req()
5901 * nand_maximize_ecc - choose the max ECC strength available
5902 * @chip: nand chip info structure
5903 * @caps: ECC engine caps info structure
5904 * @oobavail: OOB size that the ECC engine can use
5906 * Choose the max ECC strength that is supported on the controller, and can fit
5907 * within the chip's OOB. On success, the chosen ECC settings are set.
5915 int step_size, strength, nsteps, ecc_bytes, corr; in nand_maximize_ecc() local
5921 for (i = 0; i < caps->nstepinfos; i++) { in nand_maximize_ecc()
5922 stepinfo = &caps->stepinfos[i]; in nand_maximize_ecc()
5923 step_size = stepinfo->stepsize; in nand_maximize_ecc()
5925 /* If chip->ecc.size is already set, respect it */ in nand_maximize_ecc()
5926 if (chip->ecc.size && step_size != chip->ecc.size) in nand_maximize_ecc()
5929 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_maximize_ecc()
5930 strength = stepinfo->strengths[j]; in nand_maximize_ecc()
5932 if (mtd->writesize % step_size) in nand_maximize_ecc()
5935 nsteps = mtd->writesize / step_size; in nand_maximize_ecc()
5937 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); in nand_maximize_ecc()
5944 corr = strength * nsteps; in nand_maximize_ecc()
5954 best_strength = strength; in nand_maximize_ecc()
5961 return -ENOTSUPP; in nand_maximize_ecc()
5963 chip->ecc.size = best_step; in nand_maximize_ecc()
5964 chip->ecc.strength = best_strength; in nand_maximize_ecc()
5965 chip->ecc.bytes = best_ecc_bytes; in nand_maximize_ecc()
5971 * nand_ecc_choose_conf - Set the ECC strength and ECC step size
5972 * @chip: nand chip info structure
5973 * @caps: ECC engine caps info structure
5974 * @oobavail: OOB size that the ECC engine can use
5976 * Choose the ECC configuration according to following logic.
5978 * 1. If both ECC step size and ECC strength are already set (usually by DT)
5980 * 2. If the user provided the nand-ecc-maximize property, then select maximum
5981 * ECC strength.
5982 * 3. Otherwise, try to match the ECC step size and ECC strength closest
5984 * requirement then fallback to the maximum ECC step size and ECC strength.
5986 * On success, the chosen ECC settings are set.
5994 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) in nand_ecc_choose_conf()
5995 return -EINVAL; in nand_ecc_choose_conf()
5997 if (chip->ecc.size && chip->ecc.strength) in nand_ecc_choose_conf()
6000 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in nand_ecc_choose_conf()
6010 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) in rawnand_erase() argument
6012 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_erase()
6014 unsigned int eb = nanddev_pos_to_row(nand, pos); in rawnand_erase()
6017 eb >>= nand->rowconv.eraseblock_addr_shift; in rawnand_erase()
6019 nand_select_target(chip, pos->target); in rawnand_erase()
6026 static int rawnand_markbad(struct nand_device *nand, in rawnand_markbad() argument
6029 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_markbad()
6032 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); in rawnand_markbad()
6035 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos) in rawnand_isbad() argument
6037 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_isbad()
6041 nand_select_target(chip, pos->target); in rawnand_isbad()
6042 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); in rawnand_isbad()
6055 * nand_scan_tail - Scan for the NAND device
6056 * @chip: NAND chip object
6065 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_scan_tail() local
6068 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ in nand_scan_tail()
6069 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && in nand_scan_tail()
6070 !(chip->bbt_options & NAND_BBT_USE_FLASH))) { in nand_scan_tail()
6071 return -EINVAL; in nand_scan_tail()
6074 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6075 if (!chip->data_buf) in nand_scan_tail()
6076 return -ENOMEM; in nand_scan_tail()
6079 * FIXME: some NAND manufacturer drivers expect the first die to be in nand_scan_tail()
6080 * selected when manufacturer->init() is called. They should be fixed in nand_scan_tail()
6081 * to explictly select the relevant die when interacting with the NAND in nand_scan_tail()
6091 chip->oob_poi = chip->data_buf + mtd->writesize; in nand_scan_tail()
6096 if (!mtd->ooblayout && in nand_scan_tail()
6097 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6098 ecc->algo == NAND_ECC_ALGO_BCH) && in nand_scan_tail()
6099 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6100 ecc->algo == NAND_ECC_ALGO_HAMMING)) { in nand_scan_tail()
6101 switch (mtd->oobsize) { in nand_scan_tail()
6115 * ->oobsize, but we must keep the old large/small in nand_scan_tail()
6116 * page with ECC layout when ->oobsize <= 128 for in nand_scan_tail()
6119 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { in nand_scan_tail()
6126 mtd->oobsize); in nand_scan_tail()
6127 ret = -EINVAL; in nand_scan_tail()
6133 * Check ECC mode, default to software if 3byte/512byte hardware ECC is in nand_scan_tail()
6134 * selected and we have 256 byte pagesize fallback to software ECC in nand_scan_tail()
6137 switch (ecc->engine_type) { in nand_scan_tail()
6143 if (mtd->writesize >= ecc->size) { in nand_scan_tail()
6144 if (!ecc->strength) { in nand_scan_tail()
6145 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); in nand_scan_tail()
6146 ret = -EINVAL; in nand_scan_tail()
6151 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", in nand_scan_tail()
6152 ecc->size, mtd->writesize); in nand_scan_tail()
6153 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in nand_scan_tail()
6154 ecc->algo = NAND_ECC_ALGO_HAMMING; in nand_scan_tail()
6164 if (!ecc->read_page || !ecc->write_page) { in nand_scan_tail()
6165 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); in nand_scan_tail()
6166 ret = -EINVAL; in nand_scan_tail()
6169 if (!ecc->read_oob) in nand_scan_tail()
6170 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6171 if (!ecc->write_oob) in nand_scan_tail()
6172 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6177 ecc->read_page = nand_read_page_raw; in nand_scan_tail()
6178 ecc->write_page = nand_write_page_raw; in nand_scan_tail()
6179 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6180 ecc->read_page_raw = nand_read_page_raw; in nand_scan_tail()
6181 ecc->write_page_raw = nand_write_page_raw; in nand_scan_tail()
6182 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6183 ecc->size = mtd->writesize; in nand_scan_tail()
6184 ecc->bytes = 0; in nand_scan_tail()
6185 ecc->strength = 0; in nand_scan_tail()
6189 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); in nand_scan_tail()
6190 ret = -EINVAL; in nand_scan_tail()
6194 if (ecc->correct || ecc->calculate) { in nand_scan_tail()
6195 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6196 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6197 if (!ecc->calc_buf || !ecc->code_buf) { in nand_scan_tail()
6198 ret = -ENOMEM; in nand_scan_tail()
6204 if (!ecc->read_oob_raw) in nand_scan_tail()
6205 ecc->read_oob_raw = ecc->read_oob; in nand_scan_tail()
6206 if (!ecc->write_oob_raw) in nand_scan_tail()
6207 ecc->write_oob_raw = ecc->write_oob; in nand_scan_tail()
6209 /* propagate ecc info to mtd_info */ in nand_scan_tail()
6210 mtd->ecc_strength = ecc->strength; in nand_scan_tail()
6211 mtd->ecc_step_size = ecc->size; in nand_scan_tail()
6214 * Set the number of read / write steps for one page depending on ECC in nand_scan_tail()
6217 if (!ecc->steps) in nand_scan_tail()
6218 ecc->steps = mtd->writesize / ecc->size; in nand_scan_tail()
6219 if (ecc->steps * ecc->size != mtd->writesize) { in nand_scan_tail()
6220 WARN(1, "Invalid ECC parameters\n"); in nand_scan_tail()
6221 ret = -EINVAL; in nand_scan_tail()
6225 if (!ecc->total) { in nand_scan_tail()
6226 ecc->total = ecc->steps * ecc->bytes; in nand_scan_tail()
6227 chip->base.ecc.ctx.total = ecc->total; in nand_scan_tail()
6230 if (ecc->total > mtd->oobsize) { in nand_scan_tail()
6231 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); in nand_scan_tail()
6232 ret = -EINVAL; in nand_scan_tail()
6244 mtd->oobavail = ret; in nand_scan_tail()
6246 /* ECC sanity check: warn if it's too weak */ in nand_scan_tail()
6247 if (!nand_ecc_is_strong_enough(&chip->base)) in nand_scan_tail()
6248 …pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one requir… in nand_scan_tail()
6249 mtd->name, chip->ecc.strength, chip->ecc.size, in nand_scan_tail()
6250 nanddev_get_ecc_requirements(&chip->base)->strength, in nand_scan_tail()
6251 nanddev_get_ecc_requirements(&chip->base)->step_size); in nand_scan_tail()
6253 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ in nand_scan_tail()
6254 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { in nand_scan_tail()
6255 switch (ecc->steps) { in nand_scan_tail()
6257 mtd->subpage_sft = 1; in nand_scan_tail()
6262 mtd->subpage_sft = 2; in nand_scan_tail()
6266 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; in nand_scan_tail()
6269 chip->pagecache.page = -1; in nand_scan_tail()
6271 /* Large page NAND with SOFT_ECC should support subpage reads */ in nand_scan_tail()
6272 switch (ecc->engine_type) { in nand_scan_tail()
6274 if (chip->page_shift > 9) in nand_scan_tail()
6275 chip->options |= NAND_SUBPAGE_READ; in nand_scan_tail()
6282 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); in nand_scan_tail()
6287 if (chip->options & NAND_ROM) in nand_scan_tail()
6288 mtd->flags = MTD_CAP_ROM; in nand_scan_tail()
6291 mtd->_erase = nand_erase; in nand_scan_tail()
6292 mtd->_point = NULL; in nand_scan_tail()
6293 mtd->_unpoint = NULL; in nand_scan_tail()
6294 mtd->_panic_write = panic_nand_write; in nand_scan_tail()
6295 mtd->_read_oob = nand_read_oob; in nand_scan_tail()
6296 mtd->_write_oob = nand_write_oob; in nand_scan_tail()
6297 mtd->_sync = nand_sync; in nand_scan_tail()
6298 mtd->_lock = nand_lock; in nand_scan_tail()
6299 mtd->_unlock = nand_unlock; in nand_scan_tail()
6300 mtd->_suspend = nand_suspend; in nand_scan_tail()
6301 mtd->_resume = nand_resume; in nand_scan_tail()
6302 mtd->_reboot = nand_shutdown; in nand_scan_tail()
6303 mtd->_block_isreserved = nand_block_isreserved; in nand_scan_tail()
6304 mtd->_block_isbad = nand_block_isbad; in nand_scan_tail()
6305 mtd->_block_markbad = nand_block_markbad; in nand_scan_tail()
6306 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; in nand_scan_tail()
6313 if (!mtd->bitflip_threshold) in nand_scan_tail()
6314 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); in nand_scan_tail()
6322 for (i = 0; i < nanddev_ntargets(&chip->base); i++) { in nand_scan_tail()
6329 * Look for secure regions in the NAND chip. These regions are supposed in nand_scan_tail()
6339 if (chip->options & NAND_SKIP_BBTSCAN) in nand_scan_tail()
6350 kfree(chip->secure_regions); in nand_scan_tail()
6353 kfree(chip->best_interface_config); in nand_scan_tail()
6356 nanddev_cleanup(&chip->base); in nand_scan_tail()
6362 kfree(chip->data_buf); in nand_scan_tail()
6363 kfree(ecc->code_buf); in nand_scan_tail()
6364 kfree(ecc->calc_buf); in nand_scan_tail()
6371 if (chip->controller->ops && chip->controller->ops->attach_chip) in nand_attach()
6372 return chip->controller->ops->attach_chip(chip); in nand_attach()
6379 if (chip->controller->ops && chip->controller->ops->detach_chip) in nand_detach()
6380 chip->controller->ops->detach_chip(chip); in nand_detach()
6384 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6385 * @chip: NAND chip object
6399 return -EINVAL; in nand_scan_with_ids()
6425 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
6426 * @chip: NAND chip object
6430 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) { in nand_cleanup()
6431 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in nand_cleanup()
6433 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in nand_cleanup()
6437 nanddev_cleanup(&chip->base); in nand_cleanup()
6440 kfree(chip->secure_regions); in nand_cleanup()
6443 kfree(chip->bbt); in nand_cleanup()
6444 kfree(chip->data_buf); in nand_cleanup()
6445 kfree(chip->ecc.code_buf); in nand_cleanup()
6446 kfree(chip->ecc.calc_buf); in nand_cleanup()
6449 if (chip->badblock_pattern && chip->badblock_pattern->options in nand_cleanup()
6451 kfree(chip->badblock_pattern); in nand_cleanup()
6454 kfree(chip->best_interface_config); in nand_cleanup()
6471 MODULE_DESCRIPTION("Generic NAND flash driver code");