Lines Matching full:ctrl
316 struct brcmnand_controller *ctrl; member
599 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) in brcmnand_non_mmio_ops() argument
608 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) in nand_readreg() argument
610 if (brcmnand_non_mmio_ops(ctrl)) in nand_readreg()
611 return brcmnand_soc_read(ctrl->soc, offs); in nand_readreg()
612 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
615 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, in nand_writereg() argument
618 if (brcmnand_non_mmio_ops(ctrl)) in nand_writereg()
619 brcmnand_soc_write(ctrl->soc, val, offs); in nand_writereg()
621 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
624 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) in brcmnand_revision_init() argument
634 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
637 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
638 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
639 ctrl->nand_version); in brcmnand_revision_init()
644 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
645 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
646 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
647 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
648 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
649 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
650 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
651 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
652 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
653 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
654 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
655 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
658 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
659 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
661 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
664 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
665 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
667 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
670 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
671 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
672 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
676 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
678 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
679 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
681 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
682 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
683 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
684 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
686 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
688 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
689 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
691 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
693 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
694 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
695 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
696 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
697 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
698 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
700 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
702 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
703 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
704 ctrl->max_page_size = 2048; in brcmnand_revision_init()
706 ctrl->max_page_size = 4096; in brcmnand_revision_init()
707 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
712 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
713 ctrl->max_oob = 128; in brcmnand_revision_init()
714 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
715 ctrl->max_oob = 64; in brcmnand_revision_init()
716 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
717 ctrl->max_oob = 32; in brcmnand_revision_init()
719 ctrl->max_oob = 16; in brcmnand_revision_init()
722 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
723 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
729 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
730 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
732 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
733 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
735 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
736 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
737 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
738 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
743 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) in brcmnand_flash_dma_revision_init() argument
746 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
747 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
748 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
749 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
751 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
754 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, in brcmnand_read_reg() argument
757 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
760 return nand_readreg(ctrl, offs); in brcmnand_read_reg()
765 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, in brcmnand_write_reg() argument
768 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
771 nand_writereg(ctrl, offs, val); in brcmnand_write_reg()
774 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, in brcmnand_rmw_reg() argument
778 u32 tmp = brcmnand_read_reg(ctrl, reg); in brcmnand_rmw_reg()
782 brcmnand_write_reg(ctrl, reg, tmp); in brcmnand_rmw_reg()
785 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) in brcmnand_read_fc() argument
787 if (brcmnand_non_mmio_ops(ctrl)) in brcmnand_read_fc()
788 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_read_fc()
789 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
792 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, in brcmnand_write_fc() argument
795 if (brcmnand_non_mmio_ops(ctrl)) in brcmnand_write_fc()
796 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_write_fc()
798 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
801 static inline void edu_writel(struct brcmnand_controller *ctrl, in edu_writel() argument
804 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
806 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
809 static inline u32 edu_readl(struct brcmnand_controller *ctrl, in edu_readl() argument
812 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
814 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
817 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) in brcmnand_clear_ecc_addr() argument
821 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); in brcmnand_clear_ecc_addr()
822 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); in brcmnand_clear_ecc_addr()
823 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
824 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
827 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_uncorrecc_addr() argument
831 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); in brcmnand_get_uncorrecc_addr()
832 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_uncorrecc_addr()
839 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_correcc_addr() argument
843 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); in brcmnand_get_correcc_addr()
844 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_correcc_addr()
855 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr() local
857 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, in brcmnand_set_cmd_addr()
859 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); in brcmnand_set_cmd_addr()
860 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_set_cmd_addr()
862 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_set_cmd_addr()
865 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, in brcmnand_cs_offset() argument
868 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
869 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
872 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
873 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
875 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
878 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
880 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
883 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) in brcmnand_count_corrected() argument
885 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
887 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); in brcmnand_count_corrected()
892 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh() local
897 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
900 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
902 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
904 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
909 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
913 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
918 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
921 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) in brcmnand_cmd_shift() argument
926 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) in brcmnand_cmd_shift()
929 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
958 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) in brcmnand_spare_area_mask() argument
960 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
962 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
964 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
973 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) in brcmnand_ecc_level_mask() argument
975 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
980 if (ctrl->nand_version >= 0x0702) in brcmnand_ecc_level_mask()
988 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled() local
989 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
990 u32 acc_control = nand_readreg(ctrl, offs); in brcmnand_set_ecc_enabled()
999 acc_control &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_ecc_enabled()
1002 nand_writereg(ctrl, offs, acc_control); in brcmnand_set_ecc_enabled()
1005 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) in brcmnand_sector_1k_shift() argument
1007 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
1009 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
1011 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
1019 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k() local
1020 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_get_sector_size_1k()
1021 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1027 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; in brcmnand_get_sector_size_1k()
1032 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k() local
1033 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_set_sector_size_1k()
1034 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1041 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_sector_size_1k()
1044 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_sector_size_1k()
1056 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, in bcmnand_ctrl_poll_status() argument
1068 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); in bcmnand_ctrl_poll_status()
1075 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1081 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) in brcmnand_set_wp() argument
1085 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); in brcmnand_set_wp()
1092 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) in has_flash_dma() argument
1094 return ctrl->flash_dma_base; in has_flash_dma()
1097 static inline bool has_edu(struct brcmnand_controller *ctrl) in has_edu() argument
1099 return ctrl->edu_base; in has_edu()
1102 static inline bool use_dma(struct brcmnand_controller *ctrl) in use_dma() argument
1104 return has_flash_dma(ctrl) || has_edu(ctrl); in use_dma()
1107 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) in disable_ctrl_irqs() argument
1109 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1112 if (has_flash_dma(ctrl)) { in disable_ctrl_irqs()
1113 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1114 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1117 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1118 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1127 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, in flash_dma_writel() argument
1130 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1132 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1135 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, in flash_dma_readl() argument
1138 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1140 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1155 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, in is_hamming_ecc() argument
1158 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1319 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1351 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp() local
1353 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1358 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1363 * make sure ctrl/flash ready before and after in brcmnand_wp()
1366 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | in brcmnand_wp()
1373 brcmnand_set_wp(ctrl, wp); in brcmnand_wp()
1376 ret = bcmnand_ctrl_poll_status(ctrl, in brcmnand_wp()
1392 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) in oob_reg_read() argument
1396 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1397 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1399 if (offs >= ctrl->max_oob) in oob_reg_read()
1407 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1410 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, in oob_reg_write() argument
1415 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1416 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1418 if (offs >= ctrl->max_oob) in oob_reg_write()
1426 nand_writereg(ctrl, reg_offs, data); in oob_reg_write()
1431 * @ctrl: NAND controller
1437 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, in read_oob_from_regs() argument
1445 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1446 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1449 oob[j] = oob_reg_read(ctrl, j); in read_oob_from_regs()
1460 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, in write_oob_to_regs() argument
1468 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1469 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1472 oob_reg_write(ctrl, j, in write_oob_to_regs()
1480 static void brcmnand_edu_init(struct brcmnand_controller *ctrl) in brcmnand_edu_init() argument
1483 edu_writel(ctrl, EDU_ERR_STATUS, 0); in brcmnand_edu_init()
1484 edu_readl(ctrl, EDU_ERR_STATUS); in brcmnand_edu_init()
1485 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1486 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1487 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1488 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1489 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_init()
1495 struct brcmnand_controller *ctrl = data; in brcmnand_edu_irq() local
1497 if (ctrl->edu_count) { in brcmnand_edu_irq()
1498 ctrl->edu_count--; in brcmnand_edu_irq()
1499 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) in brcmnand_edu_irq()
1501 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_irq()
1502 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_irq()
1505 if (ctrl->edu_count) { in brcmnand_edu_irq()
1506 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1507 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1509 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1510 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_irq()
1511 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1512 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_irq()
1514 if (ctrl->oob) { in brcmnand_edu_irq()
1515 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1516 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1517 ctrl->edu_count + 1, in brcmnand_edu_irq()
1518 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1519 ctrl->sector_size_1k); in brcmnand_edu_irq()
1521 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_irq()
1522 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1523 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_irq()
1524 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1525 ctrl->edu_count, in brcmnand_edu_irq()
1526 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1527 ctrl->sector_size_1k); in brcmnand_edu_irq()
1532 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1533 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_irq()
1538 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1545 struct brcmnand_controller *ctrl = data; in brcmnand_ctlrdy_irq() local
1548 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1552 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1553 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1561 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1568 struct brcmnand_controller *ctrl = data; in brcmnand_irq() local
1570 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1578 struct brcmnand_controller *ctrl = data; in brcmnand_dma_irq() local
1580 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1587 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd() local
1591 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_send_cmd()
1593 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1595 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1596 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1598 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); in brcmnand_send_cmd()
1602 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, in brcmnand_send_cmd()
1603 cmd << brcmnand_cmd_shift(ctrl)); in brcmnand_send_cmd()
1611 unsigned int ctrl) in brcmnand_cmd_ctrl() argument
1619 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion() local
1624 if (mtd->oops_panic_write || ctrl->irq < 0) { in brcmstb_nand_wait_for_completion()
1626 disable_ctrl_irqs(ctrl); in brcmstb_nand_wait_for_completion()
1627 sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, in brcmstb_nand_wait_for_completion()
1634 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1644 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc() local
1647 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1648 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1652 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) in brcmnand_waitfunc()
1653 >> brcmnand_cmd_shift(ctrl); in brcmnand_waitfunc()
1655 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1657 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1658 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); in brcmnand_waitfunc()
1660 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1661 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_waitfunc()
1680 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op() local
1705 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1707 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); in brcmnand_low_level_op()
1708 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); in brcmnand_low_level_op()
1719 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc() local
1730 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1787 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1790 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1801 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); in brcmnand_cmdfunc()
1803 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1819 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte() local
1826 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> in brcmnand_read_byte()
1829 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> in brcmnand_read_byte()
1834 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1838 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_read_byte()
1853 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1862 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; in brcmnand_read_byte()
1866 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1904 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans() local
1913 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1916 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1917 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1918 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1922 ctrl->edu_pending = true; in brcmnand_edu_trans()
1923 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1924 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1925 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1926 ctrl->edu_count = trans; in brcmnand_edu_trans()
1927 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1928 ctrl->oob = oob; in brcmnand_edu_trans()
1930 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1931 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_trans()
1932 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1933 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_trans()
1934 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); in brcmnand_edu_trans()
1935 edu_readl(ctrl, EDU_LENGTH); in brcmnand_edu_trans()
1937 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1938 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_trans()
1939 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1940 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_trans()
1941 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1943 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1944 ctrl->sector_size_1k); in brcmnand_edu_trans()
1949 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1950 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_trans()
1952 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1953 dev_err(ctrl->dev, in brcmnand_edu_trans()
1955 edu_readl(ctrl, EDU_STATUS), in brcmnand_edu_trans()
1956 edu_readl(ctrl, EDU_ERR_STATUS)); in brcmnand_edu_trans()
1959 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
1962 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
1963 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
1965 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1966 ctrl->sector_size_1k); in brcmnand_edu_trans()
1970 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_edu_trans()
1973 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
1979 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) in brcmnand_edu_trans()
1980 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
1981 edu_readl(ctrl, EDU_STATUS)); in brcmnand_edu_trans()
1983 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { in brcmnand_edu_trans()
1984 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
1989 ctrl->edu_pending = false; in brcmnand_edu_trans()
1990 brcmnand_edu_init(ctrl); in brcmnand_edu_trans()
1991 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ in brcmnand_edu_trans()
1992 edu_readl(ctrl, EDU_STOP); in brcmnand_edu_trans()
2001 err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_edu_trans()
2003 err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_edu_trans()
2051 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run() local
2054 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); in brcmnand_dma_run()
2055 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); in brcmnand_dma_run()
2056 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
2057 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, in brcmnand_dma_run()
2059 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); in brcmnand_dma_run()
2063 ctrl->dma_pending = true; in brcmnand_dma_run()
2065 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ in brcmnand_dma_run()
2067 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
2068 dev_err(ctrl->dev, in brcmnand_dma_run()
2070 flash_dma_readl(ctrl, FLASH_DMA_STATUS), in brcmnand_dma_run()
2071 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); in brcmnand_dma_run()
2073 ctrl->dma_pending = false; in brcmnand_dma_run()
2074 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ in brcmnand_dma_run()
2080 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans() local
2084 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2085 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2086 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2090 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2093 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2095 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2097 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2099 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2113 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio() local
2116 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read_by_pio()
2125 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2128 *buf = brcmnand_read_fc(ctrl, j); in brcmnand_read_by_pio()
2130 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2134 oob += read_oob_from_regs(ctrl, i, oob, in brcmnand_read_by_pio()
2139 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_read_by_pio()
2146 *err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_read_by_pio()
2212 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read() local
2218 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2221 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read()
2223 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2225 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2236 if (has_edu(ctrl) && err_addr) in brcmnand_read()
2256 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2257 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2268 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2276 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2284 unsigned int corrected = brcmnand_count_corrected(ctrl); in brcmnand_read()
2291 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2357 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write() local
2361 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2364 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2370 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2371 oob_reg_write(ctrl, i, 0xffffffff); in brcmnand_write()
2375 disable_ctrl_irqs(ctrl); in brcmnand_write()
2377 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) { in brcmnand_write()
2378 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2391 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2394 brcmnand_write_fc(ctrl, j, *buf); in brcmnand_write()
2396 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2399 brcmnand_write_fc(ctrl, j, 0xffffffff); in brcmnand_write()
2403 oob += write_oob_to_regs(ctrl, i, oob, in brcmnand_write()
2413 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2480 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg() local
2482 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2483 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2485 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2490 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2493 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2494 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2499 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2507 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2508 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2509 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2514 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2517 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2518 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2523 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2531 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2532 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2533 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2538 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2550 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2552 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2554 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2557 nand_writereg(ctrl, cfg_ext_offs, tmp); in brcmnand_set_cfg()
2560 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_cfg()
2561 tmp &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_cfg()
2562 tmp &= ~brcmnand_spare_area_mask(ctrl); in brcmnand_set_cfg()
2563 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2567 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_cfg()
2589 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2615 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev() local
2633 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2634 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2649 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2665 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2676 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2690 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2691 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2695 dev_err(ctrl->dev, in brcmnand_setup_dev()
2704 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2722 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2725 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2726 tmp = nand_readreg(ctrl, offs); in brcmnand_setup_dev()
2731 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2734 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2737 nand_writereg(ctrl, offs, tmp); in brcmnand_setup_dev()
2770 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2785 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs() local
2786 struct device *dev = ctrl->dev; in brcmnand_init_cs()
2821 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2828 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2829 nand_writereg(ctrl, cfg_offs, in brcmnand_init_cs()
2830 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); in brcmnand_init_cs()
2846 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config() local
2847 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2848 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2850 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2852 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2853 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2856 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2858 nand_writereg(ctrl, cfg_ext_offs, in brcmnand_save_restore_cs_config()
2860 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2861 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2862 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2864 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2867 nand_readreg(ctrl, cfg_ext_offs); in brcmnand_save_restore_cs_config()
2868 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2869 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2870 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2876 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_suspend() local
2879 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2882 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2883 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2884 ctrl->corr_stat_threshold = in brcmnand_suspend()
2885 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); in brcmnand_suspend()
2887 if (has_flash_dma(ctrl)) in brcmnand_suspend()
2888 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2889 else if (has_edu(ctrl)) in brcmnand_suspend()
2890 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2897 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_resume() local
2900 if (has_flash_dma(ctrl)) { in brcmnand_resume()
2901 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2902 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_resume()
2905 if (has_edu(ctrl)) { in brcmnand_resume()
2906 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2907 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2908 edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2909 brcmnand_edu_init(ctrl); in brcmnand_resume()
2912 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2913 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2914 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, in brcmnand_resume()
2915 ctrl->corr_stat_threshold); in brcmnand_resume()
2916 if (ctrl->soc) { in brcmnand_resume()
2918 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2919 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2922 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2962 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup() local
2968 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
2969 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
2970 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
2972 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
2974 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | in brcmnand_edu_setup()
2976 edu_readl(ctrl, EDU_CONFIG); in brcmnand_edu_setup()
2979 brcmnand_edu_init(ctrl); in brcmnand_edu_setup()
2981 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
2982 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
2986 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
2988 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
2990 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
2991 ctrl->edu_irq, ret); in brcmnand_edu_setup()
2996 ctrl->edu_irq); in brcmnand_edu_setup()
3008 struct brcmnand_controller *ctrl; in brcmnand_probe() local
3016 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in brcmnand_probe()
3017 if (!ctrl) in brcmnand_probe()
3020 dev_set_drvdata(dev, ctrl); in brcmnand_probe()
3021 ctrl->dev = dev; in brcmnand_probe()
3022 ctrl->soc = soc; in brcmnand_probe()
3027 if (brcmnand_soc_has_ops(ctrl->soc)) in brcmnand_probe()
3030 init_completion(&ctrl->done); in brcmnand_probe()
3031 init_completion(&ctrl->dma_done); in brcmnand_probe()
3032 init_completion(&ctrl->edu_done); in brcmnand_probe()
3033 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3034 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3035 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3039 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3040 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) in brcmnand_probe()
3041 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3044 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3045 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3046 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3050 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3054 ctrl->clk = NULL; in brcmnand_probe()
3058 ret = brcmnand_revision_init(ctrl); in brcmnand_probe()
3068 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3069 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3070 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3074 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3075 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3081 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3082 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3083 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3088 brcmnand_flash_dma_revision_init(ctrl); in brcmnand_probe()
3091 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3101 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); in brcmnand_probe()
3102 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_probe()
3105 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3106 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3107 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3108 if (!ctrl->dma_desc) { in brcmnand_probe()
3113 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3114 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3120 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3122 ctrl); in brcmnand_probe()
3125 ctrl->dma_irq, ret); in brcmnand_probe()
3131 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3137 if (has_edu(ctrl)) in brcmnand_probe()
3139 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3143 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, in brcmnand_probe()
3146 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); in brcmnand_probe()
3148 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3151 brcmnand_set_wp(ctrl, false); in brcmnand_probe()
3157 ctrl->irq = platform_get_irq_optional(pdev, 0); in brcmnand_probe()
3158 if (ctrl->irq > 0) { in brcmnand_probe()
3164 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3165 DRV_NAME, ctrl); in brcmnand_probe()
3168 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3169 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3172 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3173 DRV_NAME, ctrl); in brcmnand_probe()
3177 ctrl->irq, ret); in brcmnand_probe()
3192 host->ctrl = ctrl; in brcmnand_probe()
3209 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3213 if (!list_empty(&ctrl->host_list)) in brcmnand_probe()
3228 host->ctrl = ctrl; in brcmnand_probe()
3237 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3240 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3248 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3256 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove() local
3261 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3268 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()