Lines Matching +full:brcmnand +full:- +full:v7

1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
12 #include <linux/platform_data/brcmnand.h>
17 #include <linux/dma-mapping.h>
33 #include "brcmnand.h"
49 #define DRV_NAME "brcmnand"
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
277 /* for low-power standby/resume only */
297 /* use for low-power standby/resume only */
328 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
342 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
344 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
348 /* BRCMNAND v2.1-v2.2 */
378 /* BRCMNAND v3.3-v4.0 */
408 /* BRCMNAND v5.0 */
438 /* BRCMNAND v6.0 - v7.1 */
468 /* BRCMNAND v7.1 */
498 /* BRCMNAND v7.2 */
536 /* Per chip-select offsets for v7.1 */
545 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
554 /* Per chip-select offset for <= v5.0 on CS0 only */
564 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
566 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
579 /* Only for pre-v7.1 (with no CFG_EXT register) */
583 /* Only for v7.1+ (with CFG_EXT register) */
611 return brcmnand_soc_read(ctrl->soc, offs); in nand_readreg()
612 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
619 brcmnand_soc_write(ctrl->soc, val, offs); in nand_writereg()
621 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
634 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
637 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
638 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
639 ctrl->nand_version); in brcmnand_revision_init()
640 return -ENODEV; in brcmnand_revision_init()
644 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
645 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
646 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
647 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
648 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
649 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
650 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
651 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
652 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
653 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
654 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
655 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
657 /* Chip-select stride */ in brcmnand_revision_init()
658 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
659 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
661 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
663 /* Per chip-select registers */ in brcmnand_revision_init()
664 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
665 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
667 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
669 /* v3.3-5.0 have a different CS0 offset layout */ in brcmnand_revision_init()
670 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
671 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
672 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
676 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
677 /* >= v7.1 use nice power-of-2 values! */ in brcmnand_revision_init()
678 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
679 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
681 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
682 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
683 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
684 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
686 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
688 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
689 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
691 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
693 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
694 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
695 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
696 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
697 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
698 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
700 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
702 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
703 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
704 ctrl->max_page_size = 2048; in brcmnand_revision_init()
706 ctrl->max_page_size = 4096; in brcmnand_revision_init()
707 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
712 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
713 ctrl->max_oob = 128; in brcmnand_revision_init()
714 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
715 ctrl->max_oob = 64; in brcmnand_revision_init()
716 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
717 ctrl->max_oob = 32; in brcmnand_revision_init()
719 ctrl->max_oob = 16; in brcmnand_revision_init()
722 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
723 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
729 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
730 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
732 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
733 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
735 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
736 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
737 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
738 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
746 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
747 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
748 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
749 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
751 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
757 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
768 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
788 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_read_fc()
789 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
796 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_write_fc()
798 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
804 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
806 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
812 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
814 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
855 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr()
858 (host->cs << 16) | ((addr >> 32) & 0xffff)); in brcmnand_set_cmd_addr()
868 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
869 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
872 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
873 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
875 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
878 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
880 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
885 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
892 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh()
895 int cs = host->cs; in brcmnand_wr_corr_thresh()
897 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
900 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
902 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
904 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
909 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
913 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
918 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
923 /* Kludge for the BCMA-based NAND controller which does not actually in brcmnand_cmd_shift()
926 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) in brcmnand_cmd_shift()
929 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
960 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
962 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
964 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
975 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
979 /* v7.2 includes additional ECC levels */ in brcmnand_ecc_level_mask()
980 if (ctrl->nand_version >= 0x0702) in brcmnand_ecc_level_mask()
988 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled()
989 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
995 acc_control |= host->hwcfg.ecc_level in brcmnand_set_ecc_enabled()
1007 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
1009 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
1011 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
1014 return -1; in brcmnand_sector_1k_shift()
1019 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k()
1021 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1032 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k()
1034 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1075 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1078 return -ETIMEDOUT; in bcmnand_ctrl_poll_status()
1094 return ctrl->flash_dma_base; in has_flash_dma()
1099 return ctrl->edu_base; in has_edu()
1109 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1113 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1114 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1117 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1118 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1130 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1132 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1138 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1140 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1143 /* Low-level operation types: command, address, write, or read */
1158 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1159 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && in is_hamming_ecc()
1160 cfg->ecc_level == 15; in is_hamming_ecc()
1162 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && in is_hamming_ecc()
1163 cfg->ecc_level == 15) || in is_hamming_ecc()
1164 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); in is_hamming_ecc()
1168 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1170 * Returns -ERRCODE on failure.
1177 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_ecc()
1178 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_ecc()
1179 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_ecc()
1182 return -ERANGE; in brcmnand_hamming_ooblayout_ecc()
1184 oobregion->offset = (section * sas) + 6; in brcmnand_hamming_ooblayout_ecc()
1185 oobregion->length = 3; in brcmnand_hamming_ooblayout_ecc()
1195 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_free()
1196 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_free()
1197 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_free()
1201 return -ERANGE; in brcmnand_hamming_ooblayout_free()
1208 oobregion->offset = ((section - 1) * sas) + 9; in brcmnand_hamming_ooblayout_free()
1210 if (cfg->page_size > 512) { in brcmnand_hamming_ooblayout_free()
1212 oobregion->offset = 2; in brcmnand_hamming_ooblayout_free()
1215 oobregion->offset = 0; in brcmnand_hamming_ooblayout_free()
1216 next--; in brcmnand_hamming_ooblayout_free()
1220 oobregion->length = next - oobregion->offset; in brcmnand_hamming_ooblayout_free()
1235 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_ecc()
1236 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_ecc()
1237 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_ecc()
1240 return -ERANGE; in brcmnand_bch_ooblayout_ecc()
1242 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1243 oobregion->length = chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1253 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_lp()
1254 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_lp()
1255 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_free_lp()
1258 return -ERANGE; in brcmnand_bch_ooblayout_free_lp()
1260 if (sas <= chip->ecc.bytes) in brcmnand_bch_ooblayout_free_lp()
1263 oobregion->offset = section * sas; in brcmnand_bch_ooblayout_free_lp()
1264 oobregion->length = sas - chip->ecc.bytes; in brcmnand_bch_ooblayout_free_lp()
1267 oobregion->offset++; in brcmnand_bch_ooblayout_free_lp()
1268 oobregion->length--; in brcmnand_bch_ooblayout_free_lp()
1279 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_sp()
1280 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_sp()
1282 if (section > 1 || sas - chip->ecc.bytes < 6 || in brcmnand_bch_ooblayout_free_sp()
1283 (section && sas - chip->ecc.bytes == 6)) in brcmnand_bch_ooblayout_free_sp()
1284 return -ERANGE; in brcmnand_bch_ooblayout_free_sp()
1287 oobregion->offset = 0; in brcmnand_bch_ooblayout_free_sp()
1288 oobregion->length = 5; in brcmnand_bch_ooblayout_free_sp()
1290 oobregion->offset = 6; in brcmnand_bch_ooblayout_free_sp()
1291 oobregion->length = sas - chip->ecc.bytes - 6; in brcmnand_bch_ooblayout_free_sp()
1309 struct brcmnand_cfg *p = &host->hwcfg; in brcmstb_choose_ecc_layout()
1310 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmstb_choose_ecc_layout()
1311 struct nand_ecc_ctrl *ecc = &host->chip.ecc; in brcmstb_choose_ecc_layout()
1312 unsigned int ecc_level = p->ecc_level; in brcmstb_choose_ecc_layout()
1313 int sas = p->spare_area_size << p->sector_size_1k; in brcmstb_choose_ecc_layout()
1314 int sectors = p->page_size / (512 << p->sector_size_1k); in brcmstb_choose_ecc_layout()
1316 if (p->sector_size_1k) in brcmstb_choose_ecc_layout()
1319 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1320 ecc->bytes = 3 * sectors; in brcmstb_choose_ecc_layout()
1331 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); in brcmstb_choose_ecc_layout()
1332 if (p->page_size == 512) in brcmstb_choose_ecc_layout()
1337 if (ecc->bytes >= sas) { in brcmstb_choose_ecc_layout()
1338 dev_err(&host->pdev->dev, in brcmstb_choose_ecc_layout()
1340 ecc->bytes, sas); in brcmstb_choose_ecc_layout()
1341 return -EINVAL; in brcmstb_choose_ecc_layout()
1351 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp()
1353 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1354 static int old_wp = -1; in brcmnand_wp()
1358 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1385 dev_err_ratelimited(&host->pdev->dev, in brcmnand_wp()
1396 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1397 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1399 if (offs >= ctrl->max_oob) in oob_reg_read()
1403 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_read()
1407 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1415 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1416 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1418 if (offs >= ctrl->max_oob) in oob_reg_write()
1422 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_write()
1430 * read_oob_from_regs - read data from OOB registers
1432 * @i: sub-page sector index
1445 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1446 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1454 * write_oob_to_regs - write data to OOB registers
1455 * @i: sub-page sector index
1468 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1469 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1497 if (ctrl->edu_count) { in brcmnand_edu_irq()
1498 ctrl->edu_count--; in brcmnand_edu_irq()
1505 if (ctrl->edu_count) { in brcmnand_edu_irq()
1506 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1507 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1509 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1511 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1514 if (ctrl->oob) { in brcmnand_edu_irq()
1515 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1516 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1517 ctrl->edu_count + 1, in brcmnand_edu_irq()
1518 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1519 ctrl->sector_size_1k); in brcmnand_edu_irq()
1522 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1524 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1525 ctrl->edu_count, in brcmnand_edu_irq()
1526 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1527 ctrl->sector_size_1k); in brcmnand_edu_irq()
1532 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1538 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1548 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1552 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1553 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1561 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1565 /* Handle SoC-specific interrupt hardware */
1570 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1580 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1587 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd()
1593 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1595 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1596 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1619 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion()
1624 if (mtd->oops_panic_write || ctrl->irq < 0) { in brcmstb_nand_wait_for_completion()
1634 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1644 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc()
1647 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1648 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1655 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1657 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1660 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1679 struct nand_chip *chip = &host->chip; in brcmnand_low_level_op()
1680 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op()
1705 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1719 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc()
1720 u64 addr = (u64)page_addr << chip->page_shift; in brcmnand_cmdfunc()
1726 /* Avoid propagating a negative, don't-care address */ in brcmnand_cmdfunc()
1730 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1733 host->last_cmd = command; in brcmnand_cmdfunc()
1734 host->last_byte = 0; in brcmnand_cmdfunc()
1735 host->last_addr = addr; in brcmnand_cmdfunc()
1764 addr &= ~((u64)(FC_BYTES - 1)); in brcmnand_cmdfunc()
1770 host->hwcfg.sector_size_1k = in brcmnand_cmdfunc()
1786 /* Copy flash cache word-wise */ in brcmnand_cmdfunc()
1787 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1790 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1803 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1806 if (host->hwcfg.sector_size_1k) in brcmnand_cmdfunc()
1808 host->hwcfg.sector_size_1k); in brcmnand_cmdfunc()
1811 /* Re-enable protection is necessary only after erase */ in brcmnand_cmdfunc()
1819 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte()
1823 switch (host->last_cmd) { in brcmnand_read_byte()
1825 if (host->last_byte < 4) in brcmnand_read_byte()
1827 (24 - (host->last_byte << 3)); in brcmnand_read_byte()
1828 else if (host->last_byte < 8) in brcmnand_read_byte()
1830 (56 - (host->last_byte << 3)); in brcmnand_read_byte()
1834 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1846 addr = host->last_addr + host->last_byte; in brcmnand_read_byte()
1847 offs = addr & (FC_BYTES - 1); in brcmnand_read_byte()
1850 if (host->last_byte > 0 && offs == 0) in brcmnand_read_byte()
1853 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1856 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { in brcmnand_read_byte()
1859 bool last = host->last_byte == in brcmnand_read_byte()
1860 ONFI_SUBFEATURE_PARAM_LEN - 1; in brcmnand_read_byte()
1866 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1867 host->last_byte++; in brcmnand_read_byte()
1886 switch (host->last_cmd) { in brcmnand_write_buf()
1904 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans()
1905 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_edu_trans()
1913 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1916 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1917 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1918 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1919 return -ENOMEM; in brcmnand_edu_trans()
1922 ctrl->edu_pending = true; in brcmnand_edu_trans()
1923 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1924 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1925 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1926 ctrl->edu_count = trans; in brcmnand_edu_trans()
1927 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1928 ctrl->oob = oob; in brcmnand_edu_trans()
1930 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1932 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1937 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1939 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1941 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1943 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1944 ctrl->sector_size_1k); in brcmnand_edu_trans()
1949 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1952 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1953 dev_err(ctrl->dev, in brcmnand_edu_trans()
1959 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
1962 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
1963 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
1965 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1966 ctrl->sector_size_1k); in brcmnand_edu_trans()
1973 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
1975 ret = -EIO; in brcmnand_edu_trans()
1980 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
1984 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
1986 ret = -EIO; in brcmnand_edu_trans()
1989 ctrl->edu_pending = false; in brcmnand_edu_trans()
2005 ret = -EUCLEAN; in brcmnand_edu_trans()
2007 ret = -EBADMSG; in brcmnand_edu_trans()
2016 * - Is this descriptor the beginning or end of a linked list?
2017 * - What is the (DMA) address of the next descriptor in the linked list?
2027 desc->next_desc = lower_32_bits(next_desc); in brcmnand_fill_dma_desc()
2028 desc->next_desc_ext = upper_32_bits(next_desc); in brcmnand_fill_dma_desc()
2029 desc->cmd_irq = (dma_cmd << 24) | in brcmnand_fill_dma_desc()
2033 desc->cmd_irq |= 0x01 << 12; in brcmnand_fill_dma_desc()
2035 desc->dram_addr = lower_32_bits(buf); in brcmnand_fill_dma_desc()
2036 desc->dram_addr_ext = upper_32_bits(buf); in brcmnand_fill_dma_desc()
2037 desc->tfr_len = len; in brcmnand_fill_dma_desc()
2038 desc->total_len = len; in brcmnand_fill_dma_desc()
2039 desc->flash_addr = lower_32_bits(addr); in brcmnand_fill_dma_desc()
2040 desc->flash_addr_ext = upper_32_bits(addr); in brcmnand_fill_dma_desc()
2041 desc->cs = host->cs; in brcmnand_fill_dma_desc()
2042 desc->status_valid = 0x01; in brcmnand_fill_dma_desc()
2051 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run()
2056 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
2063 ctrl->dma_pending = true; in brcmnand_dma_run()
2067 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
2068 dev_err(ctrl->dev, in brcmnand_dma_run()
2073 ctrl->dma_pending = false; in brcmnand_dma_run()
2080 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans()
2084 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2085 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2086 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2087 return -ENOMEM; in brcmnand_dma_trans()
2090 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2093 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2095 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2097 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2098 return -EBADMSG; in brcmnand_dma_trans()
2099 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2100 return -EUCLEAN; in brcmnand_dma_trans()
2113 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio()
2125 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2130 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2135 mtd->oobsize / trans, in brcmnand_read_by_pio()
2136 host->hwcfg.sector_size_1k); in brcmnand_read_by_pio()
2138 if (ret != -EBADMSG) { in brcmnand_read_by_pio()
2142 ret = -EBADMSG; in brcmnand_read_by_pio()
2149 ret = -EUCLEAN; in brcmnand_read_by_pio()
2164 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2167 * bitflips-per-ECC-sector to the caller.
2176 int page = addr >> chip->page_shift; in brcmstb_nand_verify_erased_page()
2185 ret = chip->ecc.read_page_raw(chip, buf, true, page); in brcmstb_nand_verify_erased_page()
2189 for (i = 0; i < chip->ecc.steps; i++) { in brcmstb_nand_verify_erased_page()
2190 ecc_chunk = buf + chip->ecc.size * i; in brcmstb_nand_verify_erased_page()
2193 ecc_bytes = chip->oob_poi + ecc.offset; in brcmstb_nand_verify_erased_page()
2195 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, in brcmstb_nand_verify_erased_page()
2198 chip->ecc.strength); in brcmstb_nand_verify_erased_page()
2212 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read()
2218 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2223 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2225 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2233 return -EIO; in brcmnand_read()
2241 memset(oob, 0x99, mtd->oobsize); in brcmnand_read()
2256 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2257 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2268 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2276 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2278 mtd->ecc_stats.failed++; in brcmnand_read()
2291 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2293 mtd->ecc_stats.corrected += corrected; in brcmnand_read()
2294 /* Always exceed the software-imposed threshold */ in brcmnand_read()
2295 return max(mtd->bitflip_threshold, corrected); in brcmnand_read()
2306 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page()
2310 return brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page()
2311 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page()
2319 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page_raw()
2325 ret = brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page_raw()
2326 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page_raw()
2335 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob()
2336 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob()
2337 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob()
2346 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob_raw()
2347 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob_raw()
2348 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob_raw()
2357 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write()
2358 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; in brcmnand_write()
2361 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2364 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2370 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2373 if (mtd->oops_panic_write) in brcmnand_write()
2378 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2381 ret = -EIO; in brcmnand_write()
2391 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2396 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2404 mtd->oobsize / trans, in brcmnand_write()
2405 host->hwcfg.sector_size_1k); in brcmnand_write()
2413 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2415 ret = -EIO; in brcmnand_write()
2429 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page()
2432 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page()
2442 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page_raw()
2446 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page_raw()
2455 (u64)page << chip->page_shift, NULL, in brcmnand_write_oob()
2456 chip->oob_poi); in brcmnand_write_oob()
2466 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, in brcmnand_write_oob_raw()
2467 (u8 *)chip->oob_poi); in brcmnand_write_oob_raw()
2474 * Per-CS setup (1 NAND device)
2480 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg()
2481 struct nand_chip *chip = &host->chip; in brcmnand_set_cfg()
2482 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2483 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2485 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2490 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2493 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2494 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2499 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2500 cfg->block_size); in brcmnand_set_cfg()
2501 return -EINVAL; in brcmnand_set_cfg()
2504 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); in brcmnand_set_cfg()
2507 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2508 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2509 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2510 cfg->block_size); in brcmnand_set_cfg()
2514 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2517 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2518 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2523 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2524 cfg->page_size); in brcmnand_set_cfg()
2525 return -EINVAL; in brcmnand_set_cfg()
2528 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); in brcmnand_set_cfg()
2531 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2532 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2533 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2534 return -EINVAL; in brcmnand_set_cfg()
2537 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { in brcmnand_set_cfg()
2538 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2539 (unsigned long long)cfg->device_size); in brcmnand_set_cfg()
2540 return -EINVAL; in brcmnand_set_cfg()
2542 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); in brcmnand_set_cfg()
2544 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2545 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2546 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2547 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | in brcmnand_set_cfg()
2550 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2563 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2564 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; in brcmnand_set_cfg()
2565 tmp |= cfg->spare_area_size; in brcmnand_set_cfg()
2569 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); in brcmnand_set_cfg()
2571 /* threshold = ceil(BCH-level * 0.75) */ in brcmnand_set_cfg()
2572 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); in brcmnand_set_cfg()
2581 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", in brcmnand_print_cfg()
2582 (unsigned long long)cfg->device_size >> 20, in brcmnand_print_cfg()
2583 cfg->block_size >> 10, in brcmnand_print_cfg()
2584 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, in brcmnand_print_cfg()
2585 cfg->page_size >= 1024 ? "KiB" : "B", in brcmnand_print_cfg()
2586 cfg->spare_area_size, cfg->device_width); in brcmnand_print_cfg()
2589 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2591 else if (cfg->sector_size_1k) in brcmnand_print_cfg()
2592 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); in brcmnand_print_cfg()
2594 sprintf(buf, ", BCH-%u", cfg->ecc_level); in brcmnand_print_cfg()
2599 * roundup(log2(size / page-size) / 8)
2601 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2606 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; in get_blk_adr_bytes()
2611 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmnand_setup_dev()
2612 struct nand_chip *chip = &host->chip; in brcmnand_setup_dev()
2614 nanddev_get_ecc_requirements(&chip->base); in brcmnand_setup_dev()
2615 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev()
2616 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_setup_dev()
2624 "brcm,nand-oob-sector-size", in brcmnand_setup_dev()
2628 cfg->spare_area_size = mtd->oobsize / in brcmnand_setup_dev()
2629 (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2631 cfg->spare_area_size = oob_sector; in brcmnand_setup_dev()
2633 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2634 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2639 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2641 cfg->device_size = mtd->size; in brcmnand_setup_dev()
2642 cfg->block_size = mtd->erasesize; in brcmnand_setup_dev()
2643 cfg->page_size = mtd->writesize; in brcmnand_setup_dev()
2644 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; in brcmnand_setup_dev()
2645 cfg->col_adr_bytes = 2; in brcmnand_setup_dev()
2646 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); in brcmnand_setup_dev()
2648 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { in brcmnand_setup_dev()
2649 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2650 chip->ecc.engine_type); in brcmnand_setup_dev()
2651 return -EINVAL; in brcmnand_setup_dev()
2654 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in brcmnand_setup_dev()
2655 if (chip->ecc.strength == 1 && chip->ecc.size == 512) in brcmnand_setup_dev()
2656 /* Default to Hamming for 1-bit ECC, if unspecified */ in brcmnand_setup_dev()
2657 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in brcmnand_setup_dev()
2660 chip->ecc.algo = NAND_ECC_ALGO_BCH; in brcmnand_setup_dev()
2663 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && in brcmnand_setup_dev()
2664 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { in brcmnand_setup_dev()
2665 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2666 chip->ecc.strength, chip->ecc.size); in brcmnand_setup_dev()
2667 return -EINVAL; in brcmnand_setup_dev()
2670 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && in brcmnand_setup_dev()
2671 (!chip->ecc.size || !chip->ecc.strength)) { in brcmnand_setup_dev()
2672 if (requirements->step_size && requirements->strength) { in brcmnand_setup_dev()
2674 chip->ecc.size = requirements->step_size; in brcmnand_setup_dev()
2675 chip->ecc.strength = requirements->strength; in brcmnand_setup_dev()
2676 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2677 chip->ecc.size, chip->ecc.strength); in brcmnand_setup_dev()
2681 switch (chip->ecc.size) { in brcmnand_setup_dev()
2683 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in brcmnand_setup_dev()
2684 cfg->ecc_level = 15; in brcmnand_setup_dev()
2686 cfg->ecc_level = chip->ecc.strength; in brcmnand_setup_dev()
2687 cfg->sector_size_1k = 0; in brcmnand_setup_dev()
2690 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2691 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2692 return -EINVAL; in brcmnand_setup_dev()
2694 if (chip->ecc.strength & 0x1) { in brcmnand_setup_dev()
2695 dev_err(ctrl->dev, in brcmnand_setup_dev()
2697 return -EINVAL; in brcmnand_setup_dev()
2700 cfg->ecc_level = chip->ecc.strength >> 1; in brcmnand_setup_dev()
2701 cfg->sector_size_1k = 1; in brcmnand_setup_dev()
2704 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2705 chip->ecc.size); in brcmnand_setup_dev()
2706 return -EINVAL; in brcmnand_setup_dev()
2709 cfg->ful_adr_bytes = cfg->blk_adr_bytes; in brcmnand_setup_dev()
2710 if (mtd->writesize > 512) in brcmnand_setup_dev()
2711 cfg->ful_adr_bytes += cfg->col_adr_bytes; in brcmnand_setup_dev()
2713 cfg->ful_adr_bytes += 1; in brcmnand_setup_dev()
2722 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2725 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2731 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2734 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2748 chip->options |= NAND_NO_SUBPAGE_WRITE; in brcmnand_attach_chip()
2754 chip->options |= NAND_USES_DMA; in brcmnand_attach_chip()
2756 if (chip->bbt_options & NAND_BBT_USE_FLASH) in brcmnand_attach_chip()
2757 chip->bbt_options |= NAND_BBT_NO_OOB; in brcmnand_attach_chip()
2760 return -ENXIO; in brcmnand_attach_chip()
2762 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; in brcmnand_attach_chip()
2765 mtd->bitflip_threshold = 1; in brcmnand_attach_chip()
2770 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2771 chip->ecc.write_oob = brcmnand_write_oob_raw; in brcmnand_attach_chip()
2772 chip->ecc.read_oob = brcmnand_read_oob_raw; in brcmnand_attach_chip()
2785 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs()
2786 struct device *dev = ctrl->dev; in brcmnand_init_cs()
2792 mtd = nand_to_mtd(&host->chip); in brcmnand_init_cs()
2793 chip = &host->chip; in brcmnand_init_cs()
2796 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", in brcmnand_init_cs()
2797 host->cs); in brcmnand_init_cs()
2798 if (!mtd->name) in brcmnand_init_cs()
2799 return -ENOMEM; in brcmnand_init_cs()
2801 mtd->owner = THIS_MODULE; in brcmnand_init_cs()
2802 mtd->dev.parent = dev; in brcmnand_init_cs()
2804 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; in brcmnand_init_cs()
2805 chip->legacy.cmdfunc = brcmnand_cmdfunc; in brcmnand_init_cs()
2806 chip->legacy.waitfunc = brcmnand_waitfunc; in brcmnand_init_cs()
2807 chip->legacy.read_byte = brcmnand_read_byte; in brcmnand_init_cs()
2808 chip->legacy.read_buf = brcmnand_read_buf; in brcmnand_init_cs()
2809 chip->legacy.write_buf = brcmnand_write_buf; in brcmnand_init_cs()
2811 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in brcmnand_init_cs()
2812 chip->ecc.read_page = brcmnand_read_page; in brcmnand_init_cs()
2813 chip->ecc.write_page = brcmnand_write_page; in brcmnand_init_cs()
2814 chip->ecc.read_page_raw = brcmnand_read_page_raw; in brcmnand_init_cs()
2815 chip->ecc.write_page_raw = brcmnand_write_page_raw; in brcmnand_init_cs()
2816 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; in brcmnand_init_cs()
2817 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; in brcmnand_init_cs()
2818 chip->ecc.read_oob = brcmnand_read_oob; in brcmnand_init_cs()
2819 chip->ecc.write_oob = brcmnand_write_oob; in brcmnand_init_cs()
2821 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2828 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2846 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config()
2847 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2848 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2850 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2852 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2853 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2856 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2859 host->hwcfg.config_ext); in brcmnand_save_restore_cs_config()
2860 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2861 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2862 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2864 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2866 host->hwcfg.config_ext = in brcmnand_save_restore_cs_config()
2868 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2869 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2870 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2879 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2882 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2883 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2884 ctrl->corr_stat_threshold = in brcmnand_suspend()
2888 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2890 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2901 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2906 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2907 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2912 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2913 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2915 ctrl->corr_stat_threshold); in brcmnand_resume()
2916 if (ctrl->soc) { in brcmnand_resume()
2917 /* Clear/re-enable interrupt */ in brcmnand_resume()
2918 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2919 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2922 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2923 struct nand_chip *chip = &host->chip; in brcmnand_resume()
2927 /* Reset the chip, required by some chips after power-up */ in brcmnand_resume()
2941 { .compatible = "brcm,brcmnand-v2.1" },
2942 { .compatible = "brcm,brcmnand-v2.2" },
2943 { .compatible = "brcm,brcmnand-v4.0" },
2944 { .compatible = "brcm,brcmnand-v5.0" },
2945 { .compatible = "brcm,brcmnand-v6.0" },
2946 { .compatible = "brcm,brcmnand-v6.1" },
2947 { .compatible = "brcm,brcmnand-v6.2" },
2948 { .compatible = "brcm,brcmnand-v7.0" },
2949 { .compatible = "brcm,brcmnand-v7.1" },
2950 { .compatible = "brcm,brcmnand-v7.2" },
2951 { .compatible = "brcm,brcmnand-v7.3" },
2961 struct device *dev = &pdev->dev; in brcmnand_edu_setup()
2962 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup()
2966 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); in brcmnand_edu_setup()
2968 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
2969 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
2970 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
2972 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
2981 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
2982 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
2986 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
2988 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
2990 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
2991 ctrl->edu_irq, ret); in brcmnand_edu_setup()
2996 ctrl->edu_irq); in brcmnand_edu_setup()
3005 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); in brcmnand_probe()
3006 struct device *dev = &pdev->dev; in brcmnand_probe()
3007 struct device_node *dn = dev->of_node, *child; in brcmnand_probe()
3014 return -ENODEV; in brcmnand_probe()
3018 return -ENOMEM; in brcmnand_probe()
3021 ctrl->dev = dev; in brcmnand_probe()
3022 ctrl->soc = soc; in brcmnand_probe()
3025 * that a non-memory mapped IO access path must be used in brcmnand_probe()
3027 if (brcmnand_soc_has_ops(ctrl->soc)) in brcmnand_probe()
3030 init_completion(&ctrl->done); in brcmnand_probe()
3031 init_completion(&ctrl->dma_done); in brcmnand_probe()
3032 init_completion(&ctrl->edu_done); in brcmnand_probe()
3033 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3034 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3035 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3039 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3040 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) in brcmnand_probe()
3041 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3044 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3045 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3046 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3050 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3051 if (ret == -EPROBE_DEFER) in brcmnand_probe()
3054 ctrl->clk = NULL; in brcmnand_probe()
3066 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); in brcmnand_probe()
3068 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3069 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3070 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3074 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3075 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3079 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); in brcmnand_probe()
3081 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3082 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3083 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3090 ret = -EIO; in brcmnand_probe()
3091 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3092 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3095 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3100 /* linked-list and stop on error */ in brcmnand_probe()
3105 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3106 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3107 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3108 if (!ctrl->dma_desc) { in brcmnand_probe()
3109 ret = -ENOMEM; in brcmnand_probe()
3113 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3114 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3116 ret = -ENODEV; in brcmnand_probe()
3120 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3125 ctrl->dma_irq, ret); in brcmnand_probe()
3131 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3139 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3148 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3157 ctrl->irq = platform_get_irq_optional(pdev, 0); in brcmnand_probe()
3158 if (ctrl->irq > 0) { in brcmnand_probe()
3164 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3168 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3169 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3172 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3177 ctrl->irq, ret); in brcmnand_probe()
3188 ret = -ENOMEM; in brcmnand_probe()
3191 host->pdev = pdev; in brcmnand_probe()
3192 host->ctrl = ctrl; in brcmnand_probe()
3194 ret = of_property_read_u32(child, "reg", &host->cs); in brcmnand_probe()
3196 dev_err(dev, "can't get chip-select\n"); in brcmnand_probe()
3201 nand_set_flash_node(&host->chip, child); in brcmnand_probe()
3206 continue; /* Try all chip-selects */ in brcmnand_probe()
3209 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3213 if (!list_empty(&ctrl->host_list)) in brcmnand_probe()
3217 ret = -ENODEV; in brcmnand_probe()
3224 ret = -ENOMEM; in brcmnand_probe()
3227 host->pdev = pdev; in brcmnand_probe()
3228 host->ctrl = ctrl; in brcmnand_probe()
3229 host->cs = pd->chip_select; in brcmnand_probe()
3230 host->chip.ecc.size = pd->ecc_stepsize; in brcmnand_probe()
3231 host->chip.ecc.strength = pd->ecc_strength; in brcmnand_probe()
3233 ret = brcmnand_init_cs(host, pd->part_probe_types); in brcmnand_probe()
3237 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3239 /* No chip-selects could initialize properly */ in brcmnand_probe()
3240 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3241 ret = -ENODEV; in brcmnand_probe()
3248 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3256 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove()
3261 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3262 chip = &host->chip; in brcmnand_remove()
3268 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()
3270 dev_set_drvdata(&pdev->dev, NULL); in brcmnand_remove()
3280 MODULE_ALIAS("platform:brcmnand");