Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
151 * @node: Used to store NAND chips into a list
152 * @chip: NAND chip information structure
153 * @rb: Ready-busy line
157 * @timings: NV-DDR specific timings to use
158 * @ecc_conf: Hardware ECC configuration value
159 * @strength: Register value of the ECC strength
162 * @ecc_bits: Exact number of ECC bits per syndrome
163 * @ecc_total: Total number of ECC bytes
167 * @cs_idx: Array of chip-select for this device, values are indexes
180 u32 strength; member
193 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
199 * @chips: List of all NAND chips attached to the controller
224 static struct anand *to_anand(struct nand_chip *nand) in to_anand() argument
226 return container_of(nand, struct anand, chip); in to_anand()
239 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val, in anfc_wait_for_event()
243 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event); in anfc_wait_for_event()
244 return -ETIMEDOUT; in anfc_wait_for_event()
247 writel_relaxed(event, nfc->base + INTR_STS_REG); in anfc_wait_for_event()
260 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val, in anfc_wait_for_rb()
261 val & BIT(anand->rb), in anfc_wait_for_rb()
264 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n", in anfc_wait_for_rb()
265 readl_relaxed(nfc->base + READY_STS_REG)); in anfc_wait_for_rb()
266 return -ETIMEDOUT; in anfc_wait_for_rb()
274 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG); in anfc_trigger_op()
275 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG); in anfc_trigger_op()
276 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG); in anfc_trigger_op()
277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG); in anfc_trigger_op()
278 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG); in anfc_trigger_op()
293 return -ENOTSUPP; in anfc_pkt_len_config()
306 return nfc_cs >= 0 && nfc->cs_array[nfc_cs]; in anfc_is_gpio_cs()
311 return anand->cs_idx[num]; in anfc_relative_to_absolute_cs()
317 if (nfc->cur_cs == nfc_cs_idx) in anfc_assert_cs()
321 if (anfc_is_gpio_cs(nfc, nfc->cur_cs)) in anfc_assert_cs()
322 gpiod_set_value_cansleep(nfc->cs_array[nfc->cur_cs], 1); in anfc_assert_cs()
326 nfc->native_cs = nfc->spare_cs; in anfc_assert_cs()
327 gpiod_set_value_cansleep(nfc->cs_array[nfc_cs_idx], 0); in anfc_assert_cs()
329 nfc->native_cs = nfc_cs_idx; in anfc_assert_cs()
332 nfc->cur_cs = nfc_cs_idx; in anfc_assert_cs()
338 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_select_target()
344 /* Update the controller timings and the potential ECC configuration */ in anfc_select_target()
345 writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG); in anfc_select_target()
346 writel_relaxed(anand->timings, nfc->base + TIMING_REG); in anfc_select_target()
349 if (nfc->cur_clk != anand->clk) { in anfc_select_target()
350 clk_disable_unprepare(nfc->bus_clk); in anfc_select_target()
351 ret = clk_set_rate(nfc->bus_clk, anand->clk); in anfc_select_target()
353 dev_err(nfc->dev, "Failed to change clock rate\n"); in anfc_select_target()
357 ret = clk_prepare_enable(nfc->bus_clk); in anfc_select_target()
359 dev_err(nfc->dev, in anfc_select_target()
360 "Failed to re-enable the bus clock\n"); in anfc_select_target()
364 nfc->cur_clk = anand->clk; in anfc_select_target()
371 * When using the embedded hardware ECC engine, the controller is in charge of
372 * feeding the engine with, first, the ECC residue present in the data array.
375 * but targeting the column of the first ECC bytes in the OOB area instead of
377 * 2/ After having read the relevant number of ECC bytes, the controller uses
378 * the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command
381 * will feed the ECC engine with this buffer again.
382 * 4/ The ECC engine derives the ECC bytes for the given data and compare them
388 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
395 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_read_page_hw_ecc()
398 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_read_page_hw_ecc()
404 PKT_SIZE(chip->ecc.size) | in anfc_read_page_hw_ecc()
405 PKT_STEPS(chip->ecc.steps), in anfc_read_page_hw_ecc()
407 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_read_page_hw_ecc()
408 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_read_page_hw_ecc()
411 ADDR2_STRENGTH(anand->strength) | in anfc_read_page_hw_ecc()
412 ADDR2_CS(nfc->native_cs), in anfc_read_page_hw_ecc()
416 CMD_PAGE_SIZE(anand->page_sz) | in anfc_read_page_hw_ecc()
418 CMD_NADDRS(anand->caddr_cycles + in anfc_read_page_hw_ecc()
419 anand->raddr_cycles), in anfc_read_page_hw_ecc()
423 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
424 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_read_page_hw_ecc()
425 dev_err(nfc->dev, "Buffer mapping error"); in anfc_read_page_hw_ecc()
426 return -EIO; in anfc_read_page_hw_ecc()
429 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_read_page_hw_ecc()
430 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_read_page_hw_ecc()
435 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
437 dev_err(nfc->dev, "Error reading page %d\n", page); in anfc_read_page_hw_ecc()
442 ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi, in anfc_read_page_hw_ecc()
443 mtd->oobsize, 0); in anfc_read_page_hw_ecc()
452 for (step = 0; step < chip->ecc.steps; step++) { in anfc_read_page_hw_ecc()
453 u8 *raw_buf = &buf[step * chip->ecc.size]; in anfc_read_page_hw_ecc()
458 memset(anand->hw_ecc, 0, chip->ecc.bytes); in anfc_read_page_hw_ecc()
459 nand_extract_bits(anand->hw_ecc, 0, in anfc_read_page_hw_ecc()
460 &chip->oob_poi[mtd->oobsize - anand->ecc_total], in anfc_read_page_hw_ecc()
461 anand->ecc_bits * step, anand->ecc_bits); in anfc_read_page_hw_ecc()
463 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
464 anand->hw_ecc, NULL, NULL, anand->errloc); in anfc_read_page_hw_ecc()
470 if (anand->errloc[i] < (chip->ecc.size * 8)) { in anfc_read_page_hw_ecc()
471 bit = BIT(anand->errloc[i] & 7); in anfc_read_page_hw_ecc()
472 byte = anand->errloc[i] >> 3; in anfc_read_page_hw_ecc()
477 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
483 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
485 chip->ecc.strength); in anfc_read_page_hw_ecc()
487 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
489 memset(raw_buf, 0xFF, chip->ecc.size); in anfc_read_page_hw_ecc()
491 mtd->ecc_stats.failed++; in anfc_read_page_hw_ecc()
503 ret = anfc_select_target(chip, chip->cur_cs); in anfc_sel_read_page_hw_ecc()
514 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_write_page_hw_ecc()
516 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_write_page_hw_ecc()
521 PKT_SIZE(chip->ecc.size) | in anfc_write_page_hw_ecc()
522 PKT_STEPS(chip->ecc.steps), in anfc_write_page_hw_ecc()
524 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_write_page_hw_ecc()
525 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_write_page_hw_ecc()
528 ADDR2_STRENGTH(anand->strength) | in anfc_write_page_hw_ecc()
529 ADDR2_CS(nfc->native_cs), in anfc_write_page_hw_ecc()
533 CMD_PAGE_SIZE(anand->page_sz) | in anfc_write_page_hw_ecc()
535 CMD_NADDRS(anand->caddr_cycles + in anfc_write_page_hw_ecc()
536 anand->raddr_cycles) | in anfc_write_page_hw_ecc()
541 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG); in anfc_write_page_hw_ecc()
543 ECC_SP_ADDRS(anand->caddr_cycles), in anfc_write_page_hw_ecc()
544 nfc->base + ECC_SP_REG); in anfc_write_page_hw_ecc()
546 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
547 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_write_page_hw_ecc()
548 dev_err(nfc->dev, "Buffer mapping error"); in anfc_write_page_hw_ecc()
549 return -EIO; in anfc_write_page_hw_ecc()
552 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_write_page_hw_ecc()
553 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_write_page_hw_ecc()
557 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
559 dev_err(nfc->dev, "Error writing page %d\n", page); in anfc_write_page_hw_ecc()
575 ret = anfc_select_target(chip, chip->cur_cs); in anfc_sel_write_page_hw_ecc()
582 /* NAND framework ->exec_op() hooks and related helpers */
587 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_parse_instructions()
595 nfc_op->addr2_reg = ADDR2_CS(nfc->native_cs); in anfc_parse_instructions()
596 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz); in anfc_parse_instructions()
598 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in anfc_parse_instructions()
603 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
605 switch (instr->type) { in anfc_parse_instructions()
608 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode); in anfc_parse_instructions()
610 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode); in anfc_parse_instructions()
618 addrs = &instr->ctx.addr.addrs[offset]; in anfc_parse_instructions()
619 nfc_op->cmd_reg |= CMD_NADDRS(naddrs); in anfc_parse_instructions()
623 nfc_op->addr1_reg |= (u32)addrs[i] << i * 8; in anfc_parse_instructions()
625 nfc_op->addr2_reg |= addrs[i]; in anfc_parse_instructions()
630 nfc_op->read = true; in anfc_parse_instructions()
634 buf = instr->ctx.data.buf.in; in anfc_parse_instructions()
635 nfc_op->buf = &buf[offset]; in anfc_parse_instructions()
636 nfc_op->len = nand_subop_get_data_len(subop, op_id); in anfc_parse_instructions()
637 ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps, in anfc_parse_instructions()
656 nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) | in anfc_parse_instructions()
657 PKT_STEPS(nfc_op->steps); in anfc_parse_instructions()
660 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in anfc_parse_instructions()
670 unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps; in anfc_rw_pio_op()
671 unsigned int last_len = nfc_op->len % 4; in anfc_rw_pio_op()
673 u8 *buf = nfc_op->buf; in anfc_rw_pio_op()
676 for (i = 0; i < nfc_op->steps; i++) { in anfc_rw_pio_op()
677 dir = nfc_op->read ? READ_READY : WRITE_READY; in anfc_rw_pio_op()
680 dev_err(nfc->dev, "PIO %s ready signal not received\n", in anfc_rw_pio_op()
681 nfc_op->read ? "Read" : "Write"); in anfc_rw_pio_op()
686 if (nfc_op->read) in anfc_rw_pio_op()
687 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
690 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
697 offset = nfc_op->len - last_len; in anfc_rw_pio_op()
699 if (nfc_op->read) { in anfc_rw_pio_op()
700 remainder = readl_relaxed(nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
704 writel_relaxed(remainder, nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
715 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_data_type_exec()
749 * NV-DDR mode the same command simply fails. However, it was also in anfc_data_read_type_exec()
752 * and NV-DDR). So, for simplicity, let's program the controller with in anfc_data_read_type_exec()
756 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_RNDOUT && in anfc_data_read_type_exec()
757 subop->instrs[2].ctx.cmd.opcode == NAND_CMD_RNDOUTSTART) in anfc_data_read_type_exec()
779 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_zerolen_type_exec()
803 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_status_type_exec()
808 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) in anfc_status_type_exec()
809 return -ENOTSUPP; in anfc_status_type_exec()
815 tmp = readl_relaxed(nfc->base + FLASH_STS_REG); in anfc_status_type_exec()
816 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); in anfc_status_type_exec()
836 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_wait_type_exec()
898 * The controller abstracts all the NAND operations and do not support in anfc_check_op()
904 for (op_id = 0; op_id < op->ninstrs; op_id++) { in anfc_check_op()
905 instr = &op->instrs[op_id]; in anfc_check_op()
907 switch (instr->type) { in anfc_check_op()
909 if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC) in anfc_check_op()
910 return -ENOTSUPP; in anfc_check_op()
915 if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE) in anfc_check_op()
916 return -ENOTSUPP; in anfc_check_op()
918 if (anfc_pkt_len_config(instr->ctx.data.len, NULL, NULL)) in anfc_check_op()
919 return -ENOTSUPP; in anfc_check_op()
935 * fixed patterns instead of open-coding this check here. in anfc_check_op()
937 if (op->ninstrs == 2 && in anfc_check_op()
938 op->instrs[0].type == NAND_OP_CMD_INSTR && in anfc_check_op()
939 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && in anfc_check_op()
940 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in anfc_check_op()
941 return -ENOTSUPP; in anfc_check_op()
955 ret = anfc_select_target(chip, op->cs); in anfc_exec_op()
966 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_setup_interface()
967 struct device_node *np = nfc->dev->of_node; in anfc_setup_interface()
979 * a multiple of 4. In practice, most data accesses are 4-byte in anfc_setup_interface()
982 * the device *and* we are using the NV-DDR interface(!). In in anfc_setup_interface()
987 * selecting software ECC support and must be avoided. in anfc_setup_interface()
989 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) in anfc_setup_interface()
990 return -ENOTSUPP; in anfc_setup_interface()
1001 anand->data_iface = DIFACE_SDR | in anfc_setup_interface()
1002 DIFACE_SDR_MODE(conf->timings.mode); in anfc_setup_interface()
1003 anand->timings = 0; in anfc_setup_interface()
1005 anand->data_iface = DIFACE_NVDDR | in anfc_setup_interface()
1006 DIFACE_DDR_MODE(conf->timings.mode); in anfc_setup_interface()
1008 if (conf->timings.nvddr.tCCS_min <= 100000) in anfc_setup_interface()
1010 else if (conf->timings.nvddr.tCCS_min <= 200000) in anfc_setup_interface()
1012 else if (conf->timings.nvddr.tCCS_min <= 300000) in anfc_setup_interface()
1018 if (conf->timings.nvddr.tCAD_min < 45000) in anfc_setup_interface()
1021 switch (conf->timings.mode) { in anfc_setup_interface()
1041 anand->timings = tccs_min | fast_tcad | in anfc_setup_interface()
1047 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; in anfc_setup_interface()
1050 anand->clk = div_u64((u64)NSEC_PER_SEC * 1000, in anfc_setup_interface()
1051 conf->timings.nvddr.tCK_min); in anfc_setup_interface()
1055 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work in anfc_setup_interface()
1058 * 80MHz when using SDR modes 2-5 with this SoC. in anfc_setup_interface()
1060 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") && in anfc_setup_interface()
1061 nand_interface_is_sdr(conf) && conf->timings.mode >= 2) in anfc_setup_interface()
1062 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK; in anfc_setup_interface()
1067 static int anfc_calc_hw_ecc_bytes(int step_size, int strength) in anfc_calc_hw_ecc_bytes() argument
1079 return -EINVAL; in anfc_calc_hw_ecc_bytes()
1082 ecc_bits = bch_gf_mag * strength; in anfc_calc_hw_ecc_bytes()
1115 struct nand_ecc_ctrl *ecc = &chip->ecc; in anfc_init_hw_ecc_controller() local
1119 switch (mtd->writesize) { in anfc_init_hw_ecc_controller()
1127 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize); in anfc_init_hw_ecc_controller()
1128 return -EINVAL; in anfc_init_hw_ecc_controller()
1131 ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize); in anfc_init_hw_ecc_controller()
1135 switch (ecc->strength) { in anfc_init_hw_ecc_controller()
1137 anand->strength = 0x1; in anfc_init_hw_ecc_controller()
1140 anand->strength = 0x2; in anfc_init_hw_ecc_controller()
1143 anand->strength = 0x3; in anfc_init_hw_ecc_controller()
1146 anand->strength = 0x4; in anfc_init_hw_ecc_controller()
1149 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
1150 return -EINVAL; in anfc_init_hw_ecc_controller()
1153 switch (ecc->size) { in anfc_init_hw_ecc_controller()
1163 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
1164 return -EINVAL; in anfc_init_hw_ecc_controller()
1169 ecc->steps = mtd->writesize / ecc->size; in anfc_init_hw_ecc_controller()
1170 ecc->algo = NAND_ECC_ALGO_BCH; in anfc_init_hw_ecc_controller()
1171 anand->ecc_bits = bch_gf_mag * ecc->strength; in anfc_init_hw_ecc_controller()
1172 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8); in anfc_init_hw_ecc_controller()
1173 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8); in anfc_init_hw_ecc_controller()
1174 ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total; in anfc_init_hw_ecc_controller()
1175 anand->ecc_conf = ECC_CONF_COL(ecc_offset) | in anfc_init_hw_ecc_controller()
1176 ECC_CONF_LEN(anand->ecc_total) | in anfc_init_hw_ecc_controller()
1179 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength, in anfc_init_hw_ecc_controller()
1180 sizeof(*anand->errloc), GFP_KERNEL); in anfc_init_hw_ecc_controller()
1181 if (!anand->errloc) in anfc_init_hw_ecc_controller()
1182 return -ENOMEM; in anfc_init_hw_ecc_controller()
1184 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL); in anfc_init_hw_ecc_controller()
1185 if (!anand->hw_ecc) in anfc_init_hw_ecc_controller()
1186 return -ENOMEM; in anfc_init_hw_ecc_controller()
1189 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); in anfc_init_hw_ecc_controller()
1190 if (!anand->bch) in anfc_init_hw_ecc_controller()
1191 return -EINVAL; in anfc_init_hw_ecc_controller()
1193 ecc->read_page = anfc_sel_read_page_hw_ecc; in anfc_init_hw_ecc_controller()
1194 ecc->write_page = anfc_sel_write_page_hw_ecc; in anfc_init_hw_ecc_controller()
1202 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_attach_chip()
1206 if (mtd->writesize <= SZ_512) in anfc_attach_chip()
1207 anand->caddr_cycles = 1; in anfc_attach_chip()
1209 anand->caddr_cycles = 2; in anfc_attach_chip()
1211 if (chip->options & NAND_ROW_ADDR_3) in anfc_attach_chip()
1212 anand->raddr_cycles = 3; in anfc_attach_chip()
1214 anand->raddr_cycles = 2; in anfc_attach_chip()
1216 switch (mtd->writesize) { in anfc_attach_chip()
1218 anand->page_sz = 0; in anfc_attach_chip()
1221 anand->page_sz = 5; in anfc_attach_chip()
1224 anand->page_sz = 1; in anfc_attach_chip()
1227 anand->page_sz = 2; in anfc_attach_chip()
1230 anand->page_sz = 3; in anfc_attach_chip()
1233 anand->page_sz = 4; in anfc_attach_chip()
1236 return -EINVAL; in anfc_attach_chip()
1239 /* These hooks are valid for all ECC providers */ in anfc_attach_chip()
1240 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; in anfc_attach_chip()
1241 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; in anfc_attach_chip()
1243 switch (chip->ecc.engine_type) { in anfc_attach_chip()
1252 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", in anfc_attach_chip()
1253 chip->ecc.engine_type); in anfc_attach_chip()
1254 return -EINVAL; in anfc_attach_chip()
1264 if (anand->bch) in anfc_detach_chip()
1265 bch_free(anand->bch); in anfc_detach_chip()
1282 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL); in anfc_chip_init()
1284 return -ENOMEM; in anfc_chip_init()
1286 /* Chip-select init */ in anfc_chip_init()
1287 anand->ncs_idx = of_property_count_elems_of_size(np, "reg", sizeof(u32)); in anfc_chip_init()
1288 if (anand->ncs_idx <= 0 || anand->ncs_idx > nfc->ncs) { in anfc_chip_init()
1289 dev_err(nfc->dev, "Invalid reg property\n"); in anfc_chip_init()
1290 return -EINVAL; in anfc_chip_init()
1293 anand->cs_idx = devm_kcalloc(nfc->dev, anand->ncs_idx, in anfc_chip_init()
1294 sizeof(*anand->cs_idx), GFP_KERNEL); in anfc_chip_init()
1295 if (!anand->cs_idx) in anfc_chip_init()
1296 return -ENOMEM; in anfc_chip_init()
1298 for (i = 0; i < anand->ncs_idx; i++) { in anfc_chip_init()
1300 &anand->cs_idx[i]); in anfc_chip_init()
1302 dev_err(nfc->dev, "invalid CS property: %d\n", ret); in anfc_chip_init()
1307 /* Ready-busy init */ in anfc_chip_init()
1308 ret = of_property_read_u32(np, "nand-rb", &rb); in anfc_chip_init()
1313 dev_err(nfc->dev, "Wrong RB %d\n", rb); in anfc_chip_init()
1314 return -EINVAL; in anfc_chip_init()
1317 anand->rb = rb; in anfc_chip_init()
1319 chip = &anand->chip; in anfc_chip_init()
1321 mtd->dev.parent = nfc->dev; in anfc_chip_init()
1322 chip->controller = &nfc->controller; in anfc_chip_init()
1323 chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | in anfc_chip_init()
1327 if (!mtd->name) { in anfc_chip_init()
1328 dev_err(nfc->dev, "NAND label property is mandatory\n"); in anfc_chip_init()
1329 return -EINVAL; in anfc_chip_init()
1332 ret = nand_scan(chip, anand->ncs_idx); in anfc_chip_init()
1334 dev_err(nfc->dev, "Scan operation failed\n"); in anfc_chip_init()
1344 list_add_tail(&anand->node, &nfc->chips); in anfc_chip_init()
1355 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) { in anfc_chips_cleanup()
1356 chip = &anand->chip; in anfc_chips_cleanup()
1360 list_del(&anand->node); in anfc_chips_cleanup()
1366 struct device_node *np = nfc->dev->of_node, *nand_np; in anfc_chips_init()
1371 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n", in anfc_chips_init()
1373 return -EINVAL; in anfc_chips_init()
1391 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG); in anfc_reset()
1394 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG); in anfc_reset()
1396 nfc->cur_cs = -1; in anfc_reset()
1403 /* Check the gpio-cs property */ in anfc_parse_cs()
1404 ret = rawnand_dt_parse_gpio_cs(nfc->dev, &nfc->cs_array, &nfc->ncs); in anfc_parse_cs()
1411 * the other is selected when a non-native CS must be asserted (not in anfc_parse_cs()
1412 * wired physically or configured as GPIO instead of NAND CS). In this in anfc_parse_cs()
1413 * case, the "not" chosen CS is assigned to nfc->spare_cs and selected in anfc_parse_cs()
1416 if (nfc->cs_array && nfc->ncs > 2) { in anfc_parse_cs()
1417 if (!nfc->cs_array[0] && !nfc->cs_array[1]) { in anfc_parse_cs()
1418 dev_err(nfc->dev, in anfc_parse_cs()
1420 return -EINVAL; in anfc_parse_cs()
1423 if (nfc->cs_array[0]) in anfc_parse_cs()
1424 nfc->spare_cs = 0; in anfc_parse_cs()
1426 nfc->spare_cs = 1; in anfc_parse_cs()
1429 if (!nfc->cs_array) { in anfc_parse_cs()
1430 nfc->cs_array = anfc_default_cs_array; in anfc_parse_cs()
1431 nfc->ncs = ANFC_MAX_CS; in anfc_parse_cs()
1443 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); in anfc_probe()
1445 return -ENOMEM; in anfc_probe()
1447 nfc->dev = &pdev->dev; in anfc_probe()
1448 nand_controller_init(&nfc->controller); in anfc_probe()
1449 nfc->controller.ops = &anfc_ops; in anfc_probe()
1450 INIT_LIST_HEAD(&nfc->chips); in anfc_probe()
1452 nfc->base = devm_platform_ioremap_resource(pdev, 0); in anfc_probe()
1453 if (IS_ERR(nfc->base)) in anfc_probe()
1454 return PTR_ERR(nfc->base); in anfc_probe()
1458 nfc->controller_clk = devm_clk_get(&pdev->dev, "controller"); in anfc_probe()
1459 if (IS_ERR(nfc->controller_clk)) in anfc_probe()
1460 return PTR_ERR(nfc->controller_clk); in anfc_probe()
1462 nfc->bus_clk = devm_clk_get(&pdev->dev, "bus"); in anfc_probe()
1463 if (IS_ERR(nfc->bus_clk)) in anfc_probe()
1464 return PTR_ERR(nfc->bus_clk); in anfc_probe()
1466 ret = clk_prepare_enable(nfc->controller_clk); in anfc_probe()
1470 ret = clk_prepare_enable(nfc->bus_clk); in anfc_probe()
1474 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in anfc_probe()
1491 clk_disable_unprepare(nfc->bus_clk); in anfc_probe()
1494 clk_disable_unprepare(nfc->controller_clk); in anfc_probe()
1505 clk_disable_unprepare(nfc->bus_clk); in anfc_remove()
1506 clk_disable_unprepare(nfc->controller_clk); in anfc_remove()
1513 .compatible = "xlnx,zynqmp-nand-controller",
1516 .compatible = "arasan,nfc-v3p10",
1524 .name = "arasan-nand-controller",
1536 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");