Lines Matching +full:bus +full:- +full:specific

1 # SPDX-License-Identifier: GPL-2.0-only
13 	  support any device that is CFI-compliant, you need to enable this
18 	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 	  This option enables JEDEC-style probing of flash chips which are not
24 	  CFI-targeted flash drivers for any chips which are identified which
26 	  covers most AMD/Fujitsu-compatible chips and also non-CFI
36 	  If you need to specify a specific endianness for access to flash
38 	  support for only specific arrangements of flash chips, say 'Y'. This
53 	  are expected to be wired to the CPU in 'host-endian' form.
54 	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
71 	bool "Specific CFI Flash geometry selection"
85 	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
88 	  If you wish to support CFI devices on a physical bus which is
92 	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
95 	  If you wish to support CFI devices on a physical bus which is
99 	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
102 	  If you wish to support CFI devices on a physical bus which is
106 	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
109 	  If you wish to support CFI devices on a physical bus which is
113 	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
116 	  If you wish to support CFI devices on a physical bus which is
120 	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
124 	  If you wish to support CFI devices on a physical bus which is
128 	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
131 	  If your flash chips are not interleaved - i.e. you only have one
132 	  flash chip addressed by each bus cycle, then say 'Y'.
135 	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
138 	  If your flash chips are interleaved in pairs - i.e. you have two
139 	  flash chips addressed by each bus cycle, then say 'Y'.
142 	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
145 	  If your flash chips are interleaved in fours - i.e. you have four
146 	  flash chips addressed by each bus cycle, then say 'Y'.
149 	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
152 	  If your flash chips are interleaved in eights - i.e. you have eight
153 	  flash chips addressed by each bus cycle, then say 'Y'.
156 	bool "Protection Registers aka one-time programmable (OTP) bits"
162 	  A subset of them are pre-programmed at the factory with a
163 	  unique set of values. The rest is user-programmable.
165 	  The user-programmable Protection Registers contain one-time
186 	  sets which a CFI-compliant chip may claim to implement. This code
196 	  sets which a CFI-compliant chip may claim to implement. This code
206 	  sets which a CFI-compliant chip may claim to implement. This code
213 	tristate "Support for RAM chips in bus mapping"
216 	  a bus mapping driver.
219 	tristate "Support for ROM chips in bus mapping"
222 	  a bus mapping driver.
225 	tristate "Support for absent chips in bus mapping"
232 	  with this driver will return -ENODEV upon access.