Lines Matching +full:host +full:- +full:controller
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
5 * Header file for Host Controller registers and I/O accessors.
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
20 #include <linux/mmc/host.h>
23 * Controller registers
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
235 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
244 /* 4C-4F reserved for more max current */
251 /* 55-57 reserved */
256 /* 60-FB reserved */
264 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
284 * End of controller registers.
291 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
294 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
296 /* ADMA2 32-bit DMA descriptor size */
299 /* ADMA2 32-bit descriptor */
308 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
312 * alignment for the descriptor table even in 32-bit DMA mode. Memory
318 * ADMA2 64-bit DMA descriptor size
319 * According to SD Host Controller spec v4.10, there are two kinds of
320 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
321 * Descriptor, if Host Version 4 Enable is set in the Host Control 2
322 * register, 128-bit Descriptor will be selected.
324 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) argument
327 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
359 #define sdhci_err_stats_inc(host, err_name) \ argument
360 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
374 /* Controller doesn't honor resets unless we touch the clock register */
376 /* Controller has bad caps bits, but really supports DMA */
378 /* Controller doesn't like to be reset when there is no card inserted. */
380 /* Controller doesn't like clearing the power reg before a change */
382 /* Controller has an unusable DMA engine */
384 /* Controller has an unusable ADMA engine */
386 /* Controller can only DMA from 32-bit aligned addresses */
388 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
390 /* Controller can only ADMA chunks that are a multiple of 32 bits */
392 /* Controller needs to be reset after each request to stay stable */
394 /* Controller needs voltage and power writes to happen separately */
396 /* Controller provides an incorrect timeout value for transfers */
398 /* Controller has an issue with buffer bits for small transfers */
400 /* Controller does not provide transfer-complete interrupt when not busy */
402 /* Controller has unreliable card detection */
404 /* Controller reports inverted write-protect state */
406 /* Controller has unusable command queue engine */
408 /* Controller does not like fast PIO transfers */
410 /* Controller does not have a LED */
412 /* Controller has to be forced to use block size of 2048 bytes */
414 /* Controller cannot do multi-block transfers */
416 /* Controller can only handle 1-bit data transfers */
418 /* Controller needs 10ms delay between applying power and clock */
420 /* Controller uses SDCLK instead of TMCLK for data timeouts */
422 /* Controller reports wrong base clock capability */
424 /* Controller cannot support End Attribute in NOP ADMA descriptor */
426 /* Controller is missing device caps. Use caps provided by host */
428 /* Controller uses Auto CMD12 command to stop the transfer */
430 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
432 /* Controller treats ADMA descriptors with length 0000h incorrectly */
434 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
441 /* The system physically doesn't support 1.8v, even if the host does */
445 /* Controller has a non-standard host control register */
447 /* Controller does not support HS200 */
449 /* Controller does not support DDR50 */
453 /* Controller does not support 64-bit DMA */
457 /* Capability register bit-63 indicates HS400 support */
463 /* Controller broken with using ACMD23 */
465 /* Broken Clock divider zero in controller */
467 /* Controller has CRC in 136 bit Command Response */
475 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
476 * for other purposes. Consequently we support 16-bit block count by default.
477 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
493 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
503 int flags; /* Host attributes */
504 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
505 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
512 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
514 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
515 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
516 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
527 u8 drv_type; /* Current UHS-I driver type */
528 bool reinit_uhs; /* Force UHS-related re-initialization */
530 bool runtime_suspended; /* Host is runtime suspended */
535 bool v4_mode; /* Host Version 4 Enable */
536 bool use_external_dma; /* Host selects to use external DMA */
562 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
599 unsigned int tuning_count; /* Timer count for re-tuning */
600 unsigned int tuning_mode; /* Re-tuning mode supported by host */
601 unsigned int tuning_err; /* Error code for re-tuning */
609 /* Host SDMA buffer boundary. */
612 /* Host ADMA table count */
622 u32 (*read_l)(struct sdhci_host *host, int reg);
623 u16 (*read_w)(struct sdhci_host *host, int reg);
624 u8 (*read_b)(struct sdhci_host *host, int reg);
625 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
626 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
627 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
630 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
631 void (*set_power)(struct sdhci_host *host, unsigned char mode,
634 u32 (*irq)(struct sdhci_host *host, u32 intmask);
636 int (*set_dma_mask)(struct sdhci_host *host);
637 int (*enable_dma)(struct sdhci_host *host);
638 unsigned int (*get_max_clock)(struct sdhci_host *host);
639 unsigned int (*get_min_clock)(struct sdhci_host *host);
641 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
642 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
643 void (*set_timeout)(struct sdhci_host *host,
645 void (*set_bus_width)(struct sdhci_host *host, int width);
646 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
648 unsigned int (*get_ro)(struct sdhci_host *host);
649 void (*reset)(struct sdhci_host *host, u8 mask);
650 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
651 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
652 void (*hw_reset)(struct sdhci_host *host);
653 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
654 void (*card_event)(struct sdhci_host *host);
655 void (*voltage_switch)(struct sdhci_host *host);
656 void (*adma_write_desc)(struct sdhci_host *host, void **desc,
658 void (*copy_to_bounce_buffer)(struct sdhci_host *host,
661 void (*request_done)(struct sdhci_host *host,
663 void (*dump_vendor_regs)(struct sdhci_host *host);
668 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() argument
670 if (unlikely(host->ops->write_l)) in sdhci_writel()
671 host->ops->write_l(host, val, reg); in sdhci_writel()
673 writel(val, host->ioaddr + reg); in sdhci_writel()
676 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() argument
678 if (unlikely(host->ops->write_w)) in sdhci_writew()
679 host->ops->write_w(host, val, reg); in sdhci_writew()
681 writew(val, host->ioaddr + reg); in sdhci_writew()
684 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb() argument
686 if (unlikely(host->ops->write_b)) in sdhci_writeb()
687 host->ops->write_b(host, val, reg); in sdhci_writeb()
689 writeb(val, host->ioaddr + reg); in sdhci_writeb()
692 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() argument
694 if (unlikely(host->ops->read_l)) in sdhci_readl()
695 return host->ops->read_l(host, reg); in sdhci_readl()
697 return readl(host->ioaddr + reg); in sdhci_readl()
700 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() argument
702 if (unlikely(host->ops->read_w)) in sdhci_readw()
703 return host->ops->read_w(host, reg); in sdhci_readw()
705 return readw(host->ioaddr + reg); in sdhci_readw()
708 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb() argument
710 if (unlikely(host->ops->read_b)) in sdhci_readb()
711 return host->ops->read_b(host, reg); in sdhci_readb()
713 return readb(host->ioaddr + reg); in sdhci_readb()
718 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() argument
720 writel(val, host->ioaddr + reg); in sdhci_writel()
723 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() argument
725 writew(val, host->ioaddr + reg); in sdhci_writew()
728 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb() argument
730 writeb(val, host->ioaddr + reg); in sdhci_writeb()
733 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() argument
735 return readl(host->ioaddr + reg); in sdhci_readl()
738 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() argument
740 return readw(host->ioaddr + reg); in sdhci_readw()
743 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb() argument
745 return readb(host->ioaddr + reg); in sdhci_readb()
751 void sdhci_free_host(struct sdhci_host *host);
753 static inline void *sdhci_priv(struct sdhci_host *host) in sdhci_priv() argument
755 return host->private; in sdhci_priv()
758 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
760 int sdhci_setup_host(struct sdhci_host *host);
761 void sdhci_cleanup_host(struct sdhci_host *host);
762 int __sdhci_add_host(struct sdhci_host *host);
763 int sdhci_add_host(struct sdhci_host *host);
764 void sdhci_remove_host(struct sdhci_host *host, int dead);
766 static inline void sdhci_read_caps(struct sdhci_host *host) in sdhci_read_caps() argument
768 __sdhci_read_caps(host, NULL, NULL, NULL); in sdhci_read_caps()
771 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
773 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
774 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
775 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
777 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
780 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
785 void sdhci_set_bus_width(struct sdhci_host *host, int width);
786 void sdhci_reset(struct sdhci_host *host, u8 mask);
787 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
793 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
797 int sdhci_suspend_host(struct sdhci_host *host);
798 int sdhci_resume_host(struct sdhci_host *host);
799 int sdhci_runtime_suspend_host(struct sdhci_host *host);
800 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
805 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
808 void sdhci_dumpregs(struct sdhci_host *host);
809 void sdhci_enable_v4_mode(struct sdhci_host *host);
811 void sdhci_start_tuning(struct sdhci_host *host);
812 void sdhci_end_tuning(struct sdhci_host *host);
813 void sdhci_reset_tuning(struct sdhci_host *host);
814 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
815 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
816 void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
817 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
818 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);