Lines Matching defs:sdhci_host
368 struct sdhci_host { struct
370 const char *hw_name; /* Hardware bus name */
372 unsigned int quirks; /* Deviations from spec. */
437 unsigned int quirks2; /* More deviations from spec. */
482 int irq; /* Device IRQ */
483 void __iomem *ioaddr; /* Mapped address */
484 phys_addr_t mapbase; /* physical address base */
485 char *bounce_buffer; /* For packing SDMA reads/writes */
486 dma_addr_t bounce_addr;
487 unsigned int bounce_buffer_size;
489 const struct sdhci_ops *ops; /* Low level hw interface */
492 struct mmc_host *mmc; /* MMC structure */
493 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
494 u64 dma_mask; /* custom DMA mask */
497 struct led_classdev led; /* LED control */
498 char led_name[32];
501 spinlock_t lock; /* Mutex */
503 int flags; /* Host attributes */
518 unsigned int version; /* SDHCI spec. version */
520 unsigned int max_clk; /* Max possible freq (MHz) */
521 unsigned int timeout_clk; /* Timeout freq (KHz) */
522 u8 max_timeout_count; /* Vendor specific max timeout count */
523 unsigned int clk_mul; /* Clock Muliplier value */
525 unsigned int clock; /* Current clock (MHz) */
526 u8 pwr; /* Current voltage */
527 u8 drv_type; /* Current UHS-I driver type */
528 bool reinit_uhs; /* Force UHS-related re-initialization */
530 bool runtime_suspended; /* Host is runtime suspended */
531 bool bus_on; /* Bus power prevents runtime suspend */
532 bool preset_enabled; /* Preset is enabled */
533 bool pending_reset; /* Cmd/data reset is pending */
534 bool irq_wake_enabled; /* IRQ wakeup is enabled */
535 bool v4_mode; /* Host Version 4 Enable */
536 bool use_external_dma; /* Host selects to use external DMA */
537 bool always_defer_done; /* Always defer to complete requests */
539 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
540 struct mmc_command *cmd; /* Current command */
541 struct mmc_command *data_cmd; /* Current data command */
542 struct mmc_command *deferred_cmd; /* Deferred command */
543 struct mmc_data *data; /* Current data request */
544 unsigned int data_early:1; /* Data finished before cmd */
546 struct sg_mapping_iter sg_miter; /* SG state for PIO */
547 unsigned int blocks; /* remaining PIO blocks */
549 int sg_count; /* Mapped sg entries */
550 int max_adma; /* Max. length in ADMA descriptor */
552 void *adma_table; /* ADMA descriptor table */
553 void *align_buffer; /* Bounce buffer */
555 size_t adma_table_sz; /* ADMA descriptor table size */
556 size_t align_buffer_sz; /* Bounce buffer size */
558 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
559 dma_addr_t align_addr; /* Mapped bounce buffer */
561 unsigned int desc_sz; /* ADMA current descriptor size */
562 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
564 struct workqueue_struct *complete_wq; /* Request completion wq */
565 struct work_struct complete_work; /* Request completion work */
567 struct timer_list timer; /* Timer for timeouts */
568 struct timer_list data_timer; /* Timer for data timeouts */
571 struct dma_chan *rx_chan;
572 struct dma_chan *tx_chan;
575 u32 caps; /* CAPABILITY_0 */
576 u32 caps1; /* CAPABILITY_1 */
577 bool read_caps; /* Capability flags have been read */
579 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
580 unsigned int ocr_avail_sdio; /* OCR bit masks */
581 unsigned int ocr_avail_sd;
582 unsigned int ocr_avail_mmc;
583 u32 ocr_mask; /* available voltages */
585 unsigned timing; /* Current timing */
587 u32 thread_isr;
590 u32 ier;
592 bool cqe_on; /* CQE is operating */
593 u32 cqe_ier; /* CQE interrupt mask */
594 u32 cqe_err_ier; /* CQE error interrupt mask */
596 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
597 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
622 u32 (*read_l)(struct sdhci_host *host, int reg); argument