160 	struct clk *tmclk;  member
1689 	 * timeout clock and SW can choose TMCLK or SDCLK for hardware  in sdhci_tegra_probe()
1694 	 * 12Mhz TMCLK which is advertised in host capability register.  in sdhci_tegra_probe()
1695 	 * With TMCLK of 12Mhz provides maximum data timeout period that can  in sdhci_tegra_probe()
1698 	 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's  in sdhci_tegra_probe()
1699 	 * supporting separate TMCLK.  in sdhci_tegra_probe()
1703 		clk = devm_clk_get(&pdev->dev, "tmclk");  in sdhci_tegra_probe()
1709 			dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);  in sdhci_tegra_probe()
1717 				"failed to enable tmclk: %d\n", rc);  in sdhci_tegra_probe()
1721 		tegra_host->tmclk = clk;  in sdhci_tegra_probe()
1775 	clk_disable_unprepare(tegra_host->tmclk);  in sdhci_tegra_probe()
1796 	clk_disable_unprepare(tegra_host->tmclk);  in sdhci_tegra_remove()