Lines Matching +full:sdmmc +full:- +full:3 +full:v3
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
25 #include <linux/mmc/slot-gpio.h>
31 #include "sdhci-cqhci.h"
32 #include "sdhci-pltfm.h"
42 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
101 #define NVQUIRK_ENABLE_SDR50 BIT(3)
110 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
111 * 3V3/1V8 pad selection happens through pinctrl state selection depending
120 * SDMMC hardware data timeout.
126 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
187 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
189 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
195 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
208 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
211 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
212 host->ioaddr + SDHCI_TRANSFER_MODE); in tegra_sdhci_writew()
216 writew(val, host->ioaddr + reg); in tegra_sdhci_writew()
223 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel()
232 writel(val, host->ioaddr + reg); in tegra_sdhci_writel()
234 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
237 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
242 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
282 writew(val, host->ioaddr + reg); in tegra210_sdhci_writew()
294 * Write-enable shall be assumed if GPIO is missing in a board's in tegra_sdhci_get_ro()
295 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on in tegra_sdhci_get_ro()
298 return mmc_gpio_get_ro(host->mmc); in tegra_sdhci_get_ro()
315 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
318 if (IS_ERR(host->mmc->supply.vqmmc)) in tegra_sdhci_is_pad_and_regulator_valid()
321 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
324 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
328 return tegra_host->pad_control_available; in tegra_sdhci_is_pad_and_regulator_valid()
338 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap()
348 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
356 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
368 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset()
376 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_reset()
390 /* Erratum: Enable SDHCI spec v3.00 support */ in tegra_sdhci_reset()
391 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) in tegra_sdhci_reset()
394 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
396 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in tegra_sdhci_reset()
398 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) in tegra_sdhci_reset()
400 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
404 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
409 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { in tegra_sdhci_reset()
415 tegra_host->pad_calib_required = true; in tegra_sdhci_reset()
418 tegra_host->ddr_signaling = false; in tegra_sdhci_reset()
459 &tegra_host->autocal_offsets; in tegra_sdhci_set_padctrl()
468 if (tegra_host->pinctrl_state_1v8_drv) { in tegra_sdhci_set_padctrl()
470 tegra_host->pinctrl_state_1v8_drv; in tegra_sdhci_set_padctrl()
472 drvup = offsets->pull_up_1v8_timeout; in tegra_sdhci_set_padctrl()
473 drvdn = offsets->pull_down_1v8_timeout; in tegra_sdhci_set_padctrl()
476 if (tegra_host->pinctrl_state_3v3_drv) { in tegra_sdhci_set_padctrl()
478 tegra_host->pinctrl_state_3v3_drv; in tegra_sdhci_set_padctrl()
480 drvup = offsets->pull_up_3v3_timeout; in tegra_sdhci_set_padctrl()
481 drvdn = offsets->pull_down_3v3_timeout; in tegra_sdhci_set_padctrl()
486 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
489 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
502 if (!tegra_host->pad_control_available) in tegra_sdhci_set_padctrl()
506 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
507 tegra_host->pinctrl_state_1v8); in tegra_sdhci_set_padctrl()
509 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
512 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
513 tegra_host->pinctrl_state_3v3); in tegra_sdhci_set_padctrl()
515 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
528 tegra_host->autocal_offsets; in tegra_sdhci_pad_autocalib()
529 struct mmc_ios *ios = &host->mmc->ios; in tegra_sdhci_pad_autocalib()
535 switch (ios->timing) { in tegra_sdhci_pad_autocalib()
543 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in tegra_sdhci_pad_autocalib()
549 /* Set initial offset before auto-calibration */ in tegra_sdhci_pad_autocalib()
562 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, in tegra_sdhci_pad_autocalib()
571 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); in tegra_sdhci_pad_autocalib()
578 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); in tegra_sdhci_pad_autocalib()
580 dev_err(mmc_dev(host->mmc), in tegra_sdhci_pad_autocalib()
590 &tegra_host->autocal_offsets; in tegra_sdhci_parse_pad_autocal_dt()
593 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
594 "nvidia,pad-autocal-pull-up-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
595 &autocal->pull_up_3v3); in tegra_sdhci_parse_pad_autocal_dt()
597 autocal->pull_up_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
599 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
600 "nvidia,pad-autocal-pull-down-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
601 &autocal->pull_down_3v3); in tegra_sdhci_parse_pad_autocal_dt()
603 autocal->pull_down_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
605 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
606 "nvidia,pad-autocal-pull-up-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
607 &autocal->pull_up_1v8); in tegra_sdhci_parse_pad_autocal_dt()
609 autocal->pull_up_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
611 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
612 "nvidia,pad-autocal-pull-down-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
613 &autocal->pull_down_1v8); in tegra_sdhci_parse_pad_autocal_dt()
615 autocal->pull_down_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
617 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
618 "nvidia,pad-autocal-pull-up-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
619 &autocal->pull_up_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
621 autocal->pull_up_sdr104 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
623 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
624 "nvidia,pad-autocal-pull-down-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
625 &autocal->pull_down_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
627 autocal->pull_down_sdr104 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
629 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
630 "nvidia,pad-autocal-pull-up-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
631 &autocal->pull_up_hs400); in tegra_sdhci_parse_pad_autocal_dt()
633 autocal->pull_up_hs400 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
635 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
636 "nvidia,pad-autocal-pull-down-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
637 &autocal->pull_down_hs400); in tegra_sdhci_parse_pad_autocal_dt()
639 autocal->pull_down_hs400 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
642 * Different fail-safe drive strength values based on the signaling in tegra_sdhci_parse_pad_autocal_dt()
643 * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. in tegra_sdhci_parse_pad_autocal_dt()
647 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_parse_pad_autocal_dt()
650 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
651 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
652 &autocal->pull_up_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
654 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
655 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
656 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
657 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
658 autocal->pull_up_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
661 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
662 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
663 &autocal->pull_down_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
665 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
666 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
667 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
668 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
669 autocal->pull_down_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
672 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
673 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
674 &autocal->pull_up_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
676 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
677 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
678 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
679 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
680 autocal->pull_up_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
683 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
684 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
685 &autocal->pull_down_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
687 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
688 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
689 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
690 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
691 autocal->pull_down_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
700 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); in tegra_sdhci_request()
705 tegra_host->last_calib = ktime_get(); in tegra_sdhci_request()
717 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", in tegra_sdhci_parse_tap_and_trim()
718 &tegra_host->default_tap); in tegra_sdhci_parse_tap_and_trim()
720 tegra_host->default_tap = 0; in tegra_sdhci_parse_tap_and_trim()
722 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", in tegra_sdhci_parse_tap_and_trim()
723 &tegra_host->default_trim); in tegra_sdhci_parse_tap_and_trim()
725 tegra_host->default_trim = 0; in tegra_sdhci_parse_tap_and_trim()
727 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", in tegra_sdhci_parse_tap_and_trim()
728 &tegra_host->dqs_trim); in tegra_sdhci_parse_tap_and_trim()
730 tegra_host->dqs_trim = 0x11; in tegra_sdhci_parse_tap_and_trim()
738 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) in tegra_sdhci_parse_dt()
739 tegra_host->enable_hwcq = true; in tegra_sdhci_parse_dt()
741 tegra_host->enable_hwcq = false; in tegra_sdhci_parse_dt()
751 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_clock()
762 * sdhci_calc_clk(). The divider is calculated from host->max_clk and in tegra_sdhci_set_clock()
765 * By setting the host->max_clk to clock * 2 the divider calculation in tegra_sdhci_set_clock()
770 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; in tegra_sdhci_set_clock()
777 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
778 if (tegra_host->ddr_signaling) in tegra_sdhci_set_clock()
779 host->max_clk = host_clk; in tegra_sdhci_set_clock()
781 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
785 if (tegra_host->pad_calib_required) { in tegra_sdhci_set_clock()
787 tegra_host->pad_calib_required = false; in tegra_sdhci_set_clock()
799 if (ios->enhanced_strobe) { in tegra_sdhci_hs400_enhanced_strobe()
821 return clk_round_rate(pltfm_host->clk, UINT_MAX); in tegra_sdhci_get_max_clock()
844 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, in tegra_sdhci_hs400_dll_cal()
848 dev_err(mmc_dev(host->mmc), in tegra_sdhci_hs400_dll_cal()
869 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; in tegra_sdhci_tap_correction()
872 * Read auto-tuned results and extract good valid passing window by in tegra_sdhci_tap_correction()
873 * filtering out un-wanted bubble/partial/merged windows. in tegra_sdhci_tap_correction()
902 end_pass_tap = tap - 1; in tegra_sdhci_tap_correction()
906 window = end_pass_tap - start_pass_tap; in tegra_sdhci_tap_correction()
914 tegra_host->tuned_tap_delay = tap; in tegra_sdhci_tap_correction()
927 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; in tegra_sdhci_tap_correction()
928 if (edge1 - 1 > fixed_tap) in tegra_sdhci_tap_correction()
929 tegra_host->tuned_tap_delay = edge1 - fixed_tap; in tegra_sdhci_tap_correction()
931 tegra_host->tuned_tap_delay = edge1 + fixed_tap; in tegra_sdhci_tap_correction()
939 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_post_tuning()
948 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> in tegra_sdhci_post_tuning()
950 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { in tegra_sdhci_post_tuning()
951 min_tap_dly = soc_data->min_tap_delay; in tegra_sdhci_post_tuning()
952 max_tap_dly = soc_data->max_tap_delay; in tegra_sdhci_post_tuning()
953 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; in tegra_sdhci_post_tuning()
974 window_width = end_tap - start_tap; in tegra_sdhci_post_tuning()
975 num_iter = host->tuning_loop_count; in tegra_sdhci_post_tuning()
981 if (start_tap == 0 || (end_tap == (num_iter - 1)) || in tegra_sdhci_post_tuning()
982 (end_tap == num_iter - 2) || window_width >= thdupper) { in tegra_sdhci_post_tuning()
984 mmc_hostname(host->mmc)); in tegra_sdhci_post_tuning()
990 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_post_tuning()
999 if (!err && !host->tuning_err) in tegra_sdhci_execute_hw_tuning()
1016 tegra_host->ddr_signaling = false; in tegra_sdhci_set_uhs_signaling()
1032 tegra_host->ddr_signaling = true; in tegra_sdhci_set_uhs_signaling()
1050 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; in tegra_sdhci_set_uhs_signaling()
1056 if (tegra_host->tuned_tap_delay && !set_default_tap) in tegra_sdhci_set_uhs_signaling()
1057 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_set_uhs_signaling()
1059 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_set_uhs_signaling()
1062 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); in tegra_sdhci_set_uhs_signaling()
1080 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in tegra_sdhci_execute_tuning()
1089 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in tegra_sdhci_execute_tuning()
1090 max--; in tegra_sdhci_execute_tuning()
1097 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); in tegra_sdhci_execute_tuning()
1099 return mmc_send_tuning(host->mmc, opcode, NULL); in tegra_sdhci_execute_tuning()
1110 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in sdhci_tegra_start_signal_voltage_switch()
1111 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1115 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_tegra_start_signal_voltage_switch()
1119 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1122 if (tegra_host->pad_calib_required) in sdhci_tegra_start_signal_voltage_switch()
1131 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); in tegra_sdhci_init_pinctrl_info()
1132 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { in tegra_sdhci_init_pinctrl_info()
1134 PTR_ERR(tegra_host->pinctrl_sdmmc)); in tegra_sdhci_init_pinctrl_info()
1135 return -1; in tegra_sdhci_init_pinctrl_info()
1138 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1139 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); in tegra_sdhci_init_pinctrl_info()
1140 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { in tegra_sdhci_init_pinctrl_info()
1141 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1142 tegra_host->pinctrl_state_1v8_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1145 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1146 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); in tegra_sdhci_init_pinctrl_info()
1147 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { in tegra_sdhci_init_pinctrl_info()
1148 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1149 tegra_host->pinctrl_state_3v3_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1152 tegra_host->pinctrl_state_3v3 = in tegra_sdhci_init_pinctrl_info()
1153 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); in tegra_sdhci_init_pinctrl_info()
1154 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { in tegra_sdhci_init_pinctrl_info()
1156 PTR_ERR(tegra_host->pinctrl_state_3v3)); in tegra_sdhci_init_pinctrl_info()
1157 return -1; in tegra_sdhci_init_pinctrl_info()
1160 tegra_host->pinctrl_state_1v8 = in tegra_sdhci_init_pinctrl_info()
1161 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); in tegra_sdhci_init_pinctrl_info()
1162 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { in tegra_sdhci_init_pinctrl_info()
1164 PTR_ERR(tegra_host->pinctrl_state_1v8)); in tegra_sdhci_init_pinctrl_info()
1165 return -1; in tegra_sdhci_init_pinctrl_info()
1168 tegra_host->pad_control_available = true; in tegra_sdhci_init_pinctrl_info()
1177 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_voltage_switch()
1179 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in tegra_sdhci_voltage_switch()
1180 tegra_host->pad_calib_required = true; in tegra_sdhci_voltage_switch()
1185 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel()
1194 * to be re-configured. in tegra_cqhci_writel()
1203 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1216 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1218 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1227 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in sdhci_tegra_update_dcmd_desc()
1229 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && in sdhci_tegra_update_dcmd_desc()
1230 mrq->cmd->flags & MMC_RSP_R1B) in sdhci_tegra_update_dcmd_desc()
1236 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_enable()
1241 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size in sdhci_tegra_cqe_enable()
1246 if (!cq_host->activated) { in sdhci_tegra_cqe_enable()
1282 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_tegra_cqhci_irq()
1306 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) in tegra_sdhci_set_timeout()
1317 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_pre_enable()
1327 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_post_disable()
1351 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; in tegra_sdhci_set_dma_mask()
1352 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_dma_mask()
1354 if (soc->dma_mask) in tegra_sdhci_set_dma_mask()
1355 return dma_set_mask_and_coherent(dev, soc->dma_mask); in tegra_sdhci_set_dma_mask()
1401 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1561 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1562 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1563 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1564 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1565 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1566 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1567 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1580 if (!tegra_host->enable_hwcq) in sdhci_tegra_add_host()
1589 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_tegra_add_host()
1591 cq_host = devm_kzalloc(mmc_dev(host->mmc), in sdhci_tegra_add_host()
1594 ret = -ENOMEM; in sdhci_tegra_add_host()
1598 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; in sdhci_tegra_add_host()
1599 cq_host->ops = &sdhci_tegra_cqhci_ops; in sdhci_tegra_add_host()
1601 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_tegra_add_host()
1603 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_tegra_add_host()
1605 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_tegra_add_host()
1629 soc_data = of_device_get_match_data(&pdev->dev); in sdhci_tegra_probe()
1631 return -EINVAL; in sdhci_tegra_probe()
1633 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); in sdhci_tegra_probe()
1639 tegra_host->ddr_signaling = false; in sdhci_tegra_probe()
1640 tegra_host->pad_calib_required = false; in sdhci_tegra_probe()
1641 tegra_host->pad_control_available = false; in sdhci_tegra_probe()
1642 tegra_host->soc_data = soc_data; in sdhci_tegra_probe()
1644 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) in sdhci_tegra_probe()
1645 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; in sdhci_tegra_probe()
1647 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { in sdhci_tegra_probe()
1648 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); in sdhci_tegra_probe()
1650 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_tegra_probe()
1655 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in sdhci_tegra_probe()
1656 host->mmc_host_ops.request = tegra_sdhci_request; in sdhci_tegra_probe()
1658 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_tegra_probe()
1661 if (!host->ops->platform_execute_tuning) in sdhci_tegra_probe()
1662 host->mmc_host_ops.execute_tuning = in sdhci_tegra_probe()
1665 rc = mmc_of_parse(host->mmc); in sdhci_tegra_probe()
1669 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in sdhci_tegra_probe()
1670 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_tegra_probe()
1673 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_tegra_probe()
1676 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_tegra_probe()
1680 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", in sdhci_tegra_probe()
1682 if (IS_ERR(tegra_host->power_gpio)) { in sdhci_tegra_probe()
1683 rc = PTR_ERR(tegra_host->power_gpio); in sdhci_tegra_probe()
1693 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses in sdhci_tegra_probe()
1702 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { in sdhci_tegra_probe()
1703 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1706 if (rc == -EPROBE_DEFER) in sdhci_tegra_probe()
1709 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1716 dev_err(&pdev->dev, in sdhci_tegra_probe()
1721 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1724 clk = devm_clk_get(mmc_dev(host->mmc), NULL); in sdhci_tegra_probe()
1726 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_tegra_probe()
1730 pltfm_host->clk = clk; in sdhci_tegra_probe()
1732 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, in sdhci_tegra_probe()
1734 if (IS_ERR(tegra_host->rst)) { in sdhci_tegra_probe()
1735 rc = PTR_ERR(tegra_host->rst); in sdhci_tegra_probe()
1736 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); in sdhci_tegra_probe()
1740 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); in sdhci_tegra_probe()
1744 pm_runtime_enable(&pdev->dev); in sdhci_tegra_probe()
1745 rc = pm_runtime_resume_and_get(&pdev->dev); in sdhci_tegra_probe()
1749 rc = reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1755 rc = reset_control_deassert(tegra_host->rst); in sdhci_tegra_probe()
1768 reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1770 pm_runtime_put_sync_suspend(&pdev->dev); in sdhci_tegra_probe()
1772 pm_runtime_disable(&pdev->dev); in sdhci_tegra_probe()
1775 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1790 reset_control_assert(tegra_host->rst); in sdhci_tegra_remove()
1793 pm_runtime_put_sync_suspend(&pdev->dev); in sdhci_tegra_remove()
1794 pm_runtime_force_suspend(&pdev->dev); in sdhci_tegra_remove()
1796 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()
1807 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_runtime_suspend()
1817 return clk_prepare_enable(pltfm_host->clk); in sdhci_tegra_runtime_resume()
1826 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_suspend()
1827 ret = cqhci_suspend(host->mmc); in sdhci_tegra_suspend()
1834 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1841 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1845 return mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_tegra_suspend()
1853 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_tegra_resume()
1865 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_resume()
1866 ret = cqhci_resume(host->mmc); in sdhci_tegra_resume()
1889 .name = "sdhci-tegra",