164 	u32 scratch_32;  in o2_pci_set_baseclk()  local
167 			      O2_SD_PLL_SETTING, &scratch_32);  in o2_pci_set_baseclk()
169 	scratch_32 &= 0x0000FFFF;  in o2_pci_set_baseclk()
170 	scratch_32 |= value;  in o2_pci_set_baseclk()
173 			       O2_SD_PLL_SETTING, scratch_32);  in o2_pci_set_baseclk()
243 	u32 scratch_32 = 0;  in sdhci_o2_dll_recovery()  local
258 		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
259 		scratch_32 |= O2_PLL_SOFT_RESET;  in sdhci_o2_dll_recovery()
260 		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
264 					    &scratch_32);  in sdhci_o2_dll_recovery()
266 		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_o2_dll_recovery()
267 		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);  in sdhci_o2_dll_recovery()
416 	u32 scratch_32;  in o2_pci_led_enable()  local
420 				    O2_SD_FUNC_REG0, &scratch_32);  in o2_pci_led_enable()
424 	scratch_32 &= ~O2_SD_FREG0_LEDOFF;  in o2_pci_led_enable()
426 			       O2_SD_FUNC_REG0, scratch_32);  in o2_pci_led_enable()
429 				    O2_SD_TEST_REG, &scratch_32);  in o2_pci_led_enable()
433 	scratch_32 |= O2_SD_LED_ENABLE;  in o2_pci_led_enable()
435 			       O2_SD_TEST_REG, scratch_32);  in o2_pci_led_enable()
440 	u32 scratch_32;  in sdhci_pci_o2_fujin2_pci_init()  local
443 	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
446 	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));  in sdhci_pci_o2_fujin2_pci_init()
447 	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
450 	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
453 	scratch_32 &= ~((1 << 19) | (1 << 11));  in sdhci_pci_o2_fujin2_pci_init()
454 	scratch_32 |= (1 << 10);  in sdhci_pci_o2_fujin2_pci_init()
455 	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
458 	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
461 	scratch_32 |= (1 << 4);  in sdhci_pci_o2_fujin2_pci_init()
462 	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
468 	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
471 	scratch_32 &= ~(3 << 12);  in sdhci_pci_o2_fujin2_pci_init()
472 	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
475 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
478 	scratch_32 &= ~(0x01FE);  in sdhci_pci_o2_fujin2_pci_init()
479 	scratch_32 |= 0x00CC;  in sdhci_pci_o2_fujin2_pci_init()
480 	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
483 				    O2_SD_TUNING_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
486 	scratch_32 &= ~(0x000000FF);  in sdhci_pci_o2_fujin2_pci_init()
487 	scratch_32 |= 0x00000066;  in sdhci_pci_o2_fujin2_pci_init()
488 	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
492 				    O2_SD_UHS2_L1_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
495 	scratch_32 &= ~(0x000000FC);  in sdhci_pci_o2_fujin2_pci_init()
496 	scratch_32 |= 0x00000084;  in sdhci_pci_o2_fujin2_pci_init()
497 	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
500 	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
503 	scratch_32 &= ~((1 << 21) | (1 << 30));  in sdhci_pci_o2_fujin2_pci_init()
505 	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
508 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
511 	scratch_32 &= ~(0xf0000000);  in sdhci_pci_o2_fujin2_pci_init()
512 	scratch_32 |= 0x30000000;  in sdhci_pci_o2_fujin2_pci_init()
513 	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
516 				    O2_SD_MISC_CTRL4, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
519 	scratch_32 &= ~(0x000f0000);  in sdhci_pci_o2_fujin2_pci_init()
520 	scratch_32 |= 0x00080000;  in sdhci_pci_o2_fujin2_pci_init()
521 	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
564 	u32 scratch_32;  in sdhci_pci_o2_set_clock()  local
581 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
583 		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)  in sdhci_pci_o2_set_clock()
586 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
588 		if ((scratch_32 & 0xFFFF0000) != 0x25100000)  in sdhci_pci_o2_set_clock()
592 	pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);  in sdhci_pci_o2_set_clock()
593 	scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);  in sdhci_pci_o2_set_clock()
594 	pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);  in sdhci_pci_o2_set_clock()
686 	u32 scratch_32;  in sdhci_pci_o2_probe()  local
758 						    &scratch_32);  in sdhci_pci_o2_probe()
761 			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);  in sdhci_pci_o2_probe()
764 			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {  in sdhci_pci_o2_probe()
765 				scratch_32 = 0x25100000;  in sdhci_pci_o2_probe()
767 				o2_pci_set_baseclk(chip, scratch_32);  in sdhci_pci_o2_probe()
770 							    &scratch_32);  in sdhci_pci_o2_probe()
775 				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_pci_o2_probe()
778 						       scratch_32);  in sdhci_pci_o2_probe()
793 					    O2_SD_CLK_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
797 		scratch_32 &= ~(0xFF00);  in sdhci_pci_o2_probe()
798 		scratch_32 |= 0x07E0C800;  in sdhci_pci_o2_probe()
800 				       O2_SD_CLK_SETTING, scratch_32);  in sdhci_pci_o2_probe()
803 					    O2_SD_CLKREQ, &scratch_32);  in sdhci_pci_o2_probe()
806 		scratch_32 |= 0x3;  in sdhci_pci_o2_probe()
807 		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);  in sdhci_pci_o2_probe()
810 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
814 		scratch_32 &= ~(0x1F3F070E);  in sdhci_pci_o2_probe()
815 		scratch_32 |= 0x18270106;  in sdhci_pci_o2_probe()
817 				       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
821 					    O2_SD_CAP_REG2, &scratch_32);  in sdhci_pci_o2_probe()
824 		scratch_32 &= ~(0xE0);  in sdhci_pci_o2_probe()
826 				       O2_SD_CAP_REG2, scratch_32);  in sdhci_pci_o2_probe()
851 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
855 		if ((scratch_32 & 0xff000000) == 0x01000000) {  in sdhci_pci_o2_probe()
856 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
857 			scratch_32 |= 0x1F340000;  in sdhci_pci_o2_probe()
860 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
862 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
863 			scratch_32 |= 0x25100000;  in sdhci_pci_o2_probe()
866 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
870 						    &scratch_32);  in sdhci_pci_o2_probe()
873 			scratch_32 |= (1 << 22);  in sdhci_pci_o2_probe()
875 					       O2_SD_FUNC_REG4, scratch_32);  in sdhci_pci_o2_probe()
882 		pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);  in sdhci_pci_o2_probe()
883 		scratch_32 &= 0xFFE7FFFF;  in sdhci_pci_o2_probe()
884 		scratch_32 |= 0x00180000;  in sdhci_pci_o2_probe()
885 		pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);  in sdhci_pci_o2_probe()