401 	u32 ssc;  in gl9750_set_ssc()  local
405 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
408 	ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;  in gl9750_set_ssc()
411 	ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);  in gl9750_set_ssc()
412 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
421 	/* set pll to 205MHz and ssc */  in gl9750_set_ssc_pll_205mhz()
430 	/* set pll to 100MHz and ssc */  in gl9750_set_ssc_pll_100mhz()
439 	/* set pll to 50MHz and ssc */  in gl9750_set_ssc_pll_50mhz()
581 	u32 ssc;  in gl9755_set_ssc()  local
585 	pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);  in gl9755_set_ssc()
588 	ssc &= ~PCI_GLI_9755_PLLSSC_PPM;  in gl9755_set_ssc()
591 	ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);  in gl9755_set_ssc()
592 	pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);  in gl9755_set_ssc()
601 	/* set pll to 205MHz and ssc */  in gl9755_set_ssc_pll_205mhz()
610 	/* set pll to 100MHz and ssc */  in gl9755_set_ssc_pll_100mhz()
619 	/* set pll to 50MHz and ssc */  in gl9755_set_ssc_pll_50mhz()