138 #define msm_host_readl(msm_host, host, offset) \  argument
139 	msm_host->var_ops->msm_readl_relaxed(host, offset)
141 #define msm_host_writel(msm_host, val, host, offset) \  argument
142 	msm_host->var_ops->msm_writel_relaxed(val, host, offset)
294 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_priv_msm_offset()  local
296 	return msm_host->offset;  in sdhci_priv_msm_offset()
307 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_mci_variant_readl_relaxed()  local
309 	return readl_relaxed(msm_host->core_mem + offset);  in sdhci_msm_mci_variant_readl_relaxed()
322 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_mci_variant_writel_relaxed()  local
324 	writel_relaxed(val, msm_host->core_mem + offset);  in sdhci_msm_mci_variant_writel_relaxed()
354 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in msm_set_clock_rate_for_bus_mode()  local
356 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in msm_set_clock_rate_for_bus_mode()
383 	msm_host->clk_rate = desired_rate;  in msm_set_clock_rate_for_bus_mode()
624 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in msm_init_cm_dll()  local
629 					msm_host->offset;  in msm_init_cm_dll()
631 	if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))  in msm_init_cm_dll()
632 		xo_clk = clk_get_rate(msm_host->xo_clk);  in msm_init_cm_dll()
645 	if (msm_host->dll_config)  in msm_init_cm_dll()
646 		writel_relaxed(msm_host->dll_config,  in msm_init_cm_dll()
649 	if (msm_host->use_14lpp_dll_reset) {  in msm_init_cm_dll()
675 	if (!msm_host->dll_config)  in msm_init_cm_dll()
678 	if (msm_host->use_14lpp_dll_reset &&  in msm_init_cm_dll()
679 	    !IS_ERR_OR_NULL(msm_host->xo_clk)) {  in msm_init_cm_dll()
715 	if (msm_host->use_14lpp_dll_reset) {  in msm_init_cm_dll()
716 		if (!msm_host->dll_config)  in msm_init_cm_dll()
729 	if (msm_host->uses_tassadar_dll) {  in msm_init_cm_dll()
738 		if (msm_host->clk_rate < 150000000)  in msm_init_cm_dll()
778 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in msm_hc_select_default()  local
781 					msm_host->offset;  in msm_hc_select_default()
783 	if (!msm_host->use_cdclp533) {  in msm_hc_select_default()
818 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in msm_hc_select_hs400()  local
823 					msm_host->offset;  in msm_hc_select_hs400()
835 	if ((msm_host->tuning_done || ios.enhanced_strobe) &&  in msm_hc_select_hs400()
836 	    !msm_host->calibration_done) {  in msm_hc_select_hs400()
844 	if (!msm_host->clk_rate && !msm_host->use_cdclp533) {  in msm_hc_select_hs400()
900 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_cdclp533_calibration()  local
904 					msm_host->offset;  in sdhci_msm_cdclp533_calibration()
917 	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);  in sdhci_msm_cdclp533_calibration()
1006 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_cm_dll_sdc4_calibration()  local
1019 	if (msm_host->updated_ddr_cfg)  in sdhci_msm_cm_dll_sdc4_calibration()
1023 	writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);  in sdhci_msm_cm_dll_sdc4_calibration()
1057 	if (!msm_host->use_14lpp_dll_reset) {  in sdhci_msm_cm_dll_sdc4_calibration()
1079 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_hs400_dll_calibration()  local
1084 					msm_host->offset;  in sdhci_msm_hs400_dll_calibration()
1099 					      msm_host->saved_tuning_phase);  in sdhci_msm_hs400_dll_calibration()
1109 	if (msm_host->use_cdclp533)  in sdhci_msm_hs400_dll_calibration()
1140 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_restore_sdr_dll_config()  local
1156 	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);  in sdhci_msm_restore_sdr_dll_config()
1190 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_execute_tuning()  local
1193 		msm_host->use_cdr = false;  in sdhci_msm_execute_tuning()
1199 	msm_host->use_cdr = true;  in sdhci_msm_execute_tuning()
1205 	msm_host->tuning_done = 0;  in sdhci_msm_execute_tuning()
1271 		msm_host->saved_tuning_phase = phase;  in sdhci_msm_execute_tuning()
1284 		msm_host->tuning_done = true;  in sdhci_msm_execute_tuning()
1297 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_hs400()  local
1301 	    (msm_host->tuning_done || ios->enhanced_strobe) &&  in sdhci_msm_hs400()
1302 	    !msm_host->calibration_done) {  in sdhci_msm_hs400()
1305 			msm_host->calibration_done = true;  in sdhci_msm_hs400()
1317 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_set_uhs_signaling()  local
1321 					msm_host->offset;  in sdhci_msm_set_uhs_signaling()
1378 		msm_host->calibration_done = false;  in sdhci_msm_set_uhs_signaling()
1389 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)  in sdhci_msm_set_pincfg()  argument
1391 	struct platform_device *pdev = msm_host->pdev;  in sdhci_msm_set_pincfg()
1410 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,  in msm_toggle_vqmmc()  argument
1416 	if (msm_host->vqmmc_enabled == level)  in msm_toggle_vqmmc()
1421 		if (msm_host->caps_0 & CORE_3_0V_SUPPORT)  in msm_toggle_vqmmc()
1423 		else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)  in msm_toggle_vqmmc()
1426 		if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {  in msm_toggle_vqmmc()
1443 		msm_host->vqmmc_enabled = level;  in msm_toggle_vqmmc()
1448 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,  in msm_config_vqmmc_mode()  argument
1461 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,  in sdhci_msm_set_vqmmc()  argument
1484 		ret = msm_config_vqmmc_mode(msm_host, mmc, level);  in sdhci_msm_set_vqmmc()
1486 		ret = msm_toggle_vqmmc(msm_host, mmc, level);  in sdhci_msm_set_vqmmc()
1491 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)  in sdhci_msm_init_pwr_irq_wait()  argument
1493 	init_waitqueue_head(&msm_host->pwr_irq_wait);  in sdhci_msm_init_pwr_irq_wait()
1497 		struct sdhci_msm_host *msm_host)  in sdhci_msm_complete_pwr_irq_wait()  argument
1499 	wake_up(&msm_host->pwr_irq_wait);  in sdhci_msm_complete_pwr_irq_wait()
1514 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_check_power_status()  local
1518 					msm_host->offset;  in sdhci_msm_check_power_status()
1522 			msm_host->curr_pwr_state, msm_host->curr_io_level);  in sdhci_msm_check_power_status()
1530 	if (!msm_host->mci_removed)  in sdhci_msm_check_power_status()
1531 		val = msm_host_readl(msm_host, host,  in sdhci_msm_check_power_status()
1555 	if ((req_type & msm_host->curr_pwr_state) ||  in sdhci_msm_check_power_status()
1556 			(req_type & msm_host->curr_io_level))  in sdhci_msm_check_power_status()
1565 		if (!wait_event_timeout(msm_host->pwr_irq_wait,  in sdhci_msm_check_power_status()
1566 				msm_host->pwr_irq_flag,  in sdhci_msm_check_power_status()
1568 			dev_warn(&msm_host->pdev->dev,  in sdhci_msm_check_power_status()
1579 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_dump_pwr_ctrl_regs()  local
1581 					msm_host->offset;  in sdhci_msm_dump_pwr_ctrl_regs()
1585 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),  in sdhci_msm_dump_pwr_ctrl_regs()
1586 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),  in sdhci_msm_dump_pwr_ctrl_regs()
1587 		msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));  in sdhci_msm_dump_pwr_ctrl_regs()
1593 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_handle_pwr_irq()  local
1599 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;  in sdhci_msm_handle_pwr_irq()
1601 	irq_status = msm_host_readl(msm_host, host,  in sdhci_msm_handle_pwr_irq()
1605 	msm_host_writel(msm_host, irq_status, host,  in sdhci_msm_handle_pwr_irq()
1615 	while (irq_status & msm_host_readl(msm_host, host,  in sdhci_msm_handle_pwr_irq()
1624 		msm_host_writel(msm_host, irq_status, host,  in sdhci_msm_handle_pwr_irq()
1643 			ret = sdhci_msm_set_vqmmc(msm_host, mmc,  in sdhci_msm_handle_pwr_irq()
1646 			ret = sdhci_msm_set_pincfg(msm_host,  in sdhci_msm_handle_pwr_irq()
1680 	msm_host_writel(msm_host, irq_ack, host,  in sdhci_msm_handle_pwr_irq()
1687 	if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {  in sdhci_msm_handle_pwr_irq()
1705 				(msm_host->caps_0 & CORE_3_0V_SUPPORT))  in sdhci_msm_handle_pwr_irq()
1708 				(msm_host->caps_0 & CORE_1_8V_SUPPORT))  in sdhci_msm_handle_pwr_irq()
1717 		msm_host->curr_pwr_state = pwr_state;  in sdhci_msm_handle_pwr_irq()
1719 		msm_host->curr_io_level = io_level;  in sdhci_msm_handle_pwr_irq()
1722 		mmc_hostname(msm_host->mmc), __func__, irq, irq_status,  in sdhci_msm_handle_pwr_irq()
1730 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_pwr_irq()  local
1733 	msm_host->pwr_irq_flag = 1;  in sdhci_msm_pwr_irq()
1734 	sdhci_msm_complete_pwr_irq_wait(msm_host);  in sdhci_msm_pwr_irq()
1743 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_get_max_clock()  local
1744 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in sdhci_msm_get_max_clock()
1784 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_set_clock()  local
1787 		host->mmc->actual_clock = msm_host->clk_rate = 0;  in sdhci_msm_set_clock()
1827 static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_supported()  argument
1829 	struct device *dev = mmc_dev(msm_host->mmc);  in sdhci_msm_ice_supported()
1830 	u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION);  in sdhci_msm_ice_supported()
1846 	regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING);  in sdhci_msm_ice_supported()
1861 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,  in sdhci_msm_ice_init()  argument
1864 	struct mmc_host *mmc = msm_host->mmc;  in sdhci_msm_ice_init()
1871 	res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM,  in sdhci_msm_ice_init()
1883 	msm_host->ice_mem = devm_ioremap_resource(dev, res);  in sdhci_msm_ice_init()
1884 	if (IS_ERR(msm_host->ice_mem))  in sdhci_msm_ice_init()
1885 		return PTR_ERR(msm_host->ice_mem);  in sdhci_msm_ice_init()
1887 	if (!sdhci_msm_ice_supported(msm_host))  in sdhci_msm_ice_init()
1898 static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_low_power_mode_enable()  argument
1902 	regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);  in sdhci_msm_ice_low_power_mode_enable()
1908 	sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);  in sdhci_msm_ice_low_power_mode_enable()
1911 static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_optimization_enable()  argument
1916 	regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);  in sdhci_msm_ice_optimization_enable()
1920 	sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);  in sdhci_msm_ice_optimization_enable()
1936 static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_wait_bist_status()  argument
1941 	err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS,  in sdhci_msm_ice_wait_bist_status()
1945 		dev_err(mmc_dev(msm_host->mmc),  in sdhci_msm_ice_wait_bist_status()
1950 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_enable()  argument
1952 	if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))  in sdhci_msm_ice_enable()
1954 	sdhci_msm_ice_low_power_mode_enable(msm_host);  in sdhci_msm_ice_enable()
1955 	sdhci_msm_ice_optimization_enable(msm_host);  in sdhci_msm_ice_enable()
1956 	sdhci_msm_ice_wait_bist_status(msm_host);  in sdhci_msm_ice_enable()
1959 static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_resume()  argument
1961 	if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))  in sdhci_msm_ice_resume()
1963 	return sdhci_msm_ice_wait_bist_status(msm_host);  in sdhci_msm_ice_resume()
2017 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,  in sdhci_msm_ice_init()  argument
2023 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_enable()  argument
2028 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)  in sdhci_msm_ice_resume()  argument
2056 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_cqe_enable()  local
2059 	sdhci_msm_ice_enable(msm_host);  in sdhci_msm_cqe_enable()
2122 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_cqe_add_host()  local
2146 	msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;  in sdhci_msm_cqe_add_host()
2151 	ret = sdhci_msm_ice_init(msm_host, cq_host);  in sdhci_msm_cqe_add_host()
2199 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in __sdhci_msm_check_write()  local
2215 		msm_host->transfer_mode = val;  in __sdhci_msm_check_write()
2218 		if (!msm_host->use_cdr)  in __sdhci_msm_check_write()
2220 		if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&  in __sdhci_msm_check_write()
2230 		msm_host->pwr_irq_flag = 0;  in __sdhci_msm_check_write()
2265 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)  in sdhci_msm_set_regulator_caps()  argument
2267 	struct mmc_host *mmc = msm_host->mmc;  in sdhci_msm_set_regulator_caps()
2271 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;  in sdhci_msm_set_regulator_caps()
2289 		u32 io_level = msm_host->curr_io_level;  in sdhci_msm_set_regulator_caps()
2303 	msm_host->caps_0 |= caps;  in sdhci_msm_set_regulator_caps()
2314 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)  in sdhci_msm_register_vreg()  argument
2318 	ret = mmc_regulator_get_supply(msm_host->mmc);  in sdhci_msm_register_vreg()
2322 	sdhci_msm_set_regulator_caps(msm_host);  in sdhci_msm_register_vreg()
2386 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_dump_vendor_regs()  local
2387 	const struct sdhci_msm_offset *msm_offset = msm_host->offset;  in sdhci_msm_dump_vendor_regs()
2482 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_get_of_property()  local
2485 				&msm_host->ddr_config))  in sdhci_msm_get_of_property()
2486 		msm_host->ddr_config = DDR_CONFIG_POR_VAL;  in sdhci_msm_get_of_property()
2488 	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);  in sdhci_msm_get_of_property()
2533 	struct sdhci_msm_host *msm_host;  in sdhci_msm_probe()  local
2543 	host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));  in sdhci_msm_probe()
2549 	msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_probe()
2550 	msm_host->mmc = host->mmc;  in sdhci_msm_probe()
2551 	msm_host->pdev = pdev;  in sdhci_msm_probe()
2563 	msm_host->mci_removed = var_info->mci_removed;  in sdhci_msm_probe()
2564 	msm_host->restore_dll_config = var_info->restore_dll_config;  in sdhci_msm_probe()
2565 	msm_host->var_ops = var_info->var_ops;  in sdhci_msm_probe()
2566 	msm_host->offset = var_info->offset;  in sdhci_msm_probe()
2568 	msm_offset = msm_host->offset;  in sdhci_msm_probe()
2573 	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;  in sdhci_msm_probe()
2580 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");  in sdhci_msm_probe()
2581 	if (!IS_ERR(msm_host->bus_clk)) {  in sdhci_msm_probe()
2583 		ret = clk_set_rate(msm_host->bus_clk, INT_MAX);  in sdhci_msm_probe()
2586 		ret = clk_prepare_enable(msm_host->bus_clk);  in sdhci_msm_probe()
2598 	msm_host->bulk_clks[1].clk = clk;  in sdhci_msm_probe()
2607 	msm_host->bulk_clks[0].clk = clk;  in sdhci_msm_probe()
2633 	msm_host->bulk_clks[2].clk = clk;  in sdhci_msm_probe()
2638 	msm_host->bulk_clks[3].clk = clk;  in sdhci_msm_probe()
2643 	msm_host->bulk_clks[4].clk = clk;  in sdhci_msm_probe()
2645 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),  in sdhci_msm_probe()
2646 				      msm_host->bulk_clks);  in sdhci_msm_probe()
2654 	msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");  in sdhci_msm_probe()
2655 	if (IS_ERR(msm_host->xo_clk)) {  in sdhci_msm_probe()
2656 		ret = PTR_ERR(msm_host->xo_clk);  in sdhci_msm_probe()
2660 	if (!msm_host->mci_removed) {  in sdhci_msm_probe()
2661 		msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);  in sdhci_msm_probe()
2662 		if (IS_ERR(msm_host->core_mem)) {  in sdhci_msm_probe()
2663 			ret = PTR_ERR(msm_host->core_mem);  in sdhci_msm_probe()
2672 	if (!msm_host->mci_removed) {  in sdhci_msm_probe()
2674 		msm_host_writel(msm_host, HC_MODE_EN, host,  in sdhci_msm_probe()
2676 		config = msm_host_readl(msm_host, host,  in sdhci_msm_probe()
2679 		msm_host_writel(msm_host, config, host,  in sdhci_msm_probe()
2688 	core_version = msm_host_readl(msm_host, host,  in sdhci_msm_probe()
2697 		msm_host->use_14lpp_dll_reset = true;  in sdhci_msm_probe()
2704 		msm_host->use_cdclp533 = true;  in sdhci_msm_probe()
2718 		msm_host->updated_ddr_cfg = true;  in sdhci_msm_probe()
2721 		msm_host->uses_tassadar_dll = true;  in sdhci_msm_probe()
2723 	ret = sdhci_msm_register_vreg(msm_host);  in sdhci_msm_probe()
2743 	msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");  in sdhci_msm_probe()
2744 	if (msm_host->pwr_irq < 0) {  in sdhci_msm_probe()
2745 		ret = msm_host->pwr_irq;  in sdhci_msm_probe()
2749 	sdhci_msm_init_pwr_irq_wait(msm_host);  in sdhci_msm_probe()
2751 	msm_host_writel(msm_host, INT_MASK, host,  in sdhci_msm_probe()
2754 	ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,  in sdhci_msm_probe()
2762 	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;  in sdhci_msm_probe()
2794 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),  in sdhci_msm_probe()
2795 				   msm_host->bulk_clks);  in sdhci_msm_probe()
2797 	if (!IS_ERR(msm_host->bus_clk))  in sdhci_msm_probe()
2798 		clk_disable_unprepare(msm_host->bus_clk);  in sdhci_msm_probe()
2808 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_remove()  local
2818 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),  in sdhci_msm_remove()
2819 				   msm_host->bulk_clks);  in sdhci_msm_remove()
2820 	if (!IS_ERR(msm_host->bus_clk))  in sdhci_msm_remove()
2821 		clk_disable_unprepare(msm_host->bus_clk);  in sdhci_msm_remove()
2830 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_runtime_suspend()  local
2834 	clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),  in sdhci_msm_runtime_suspend()
2835 				   msm_host->bulk_clks);  in sdhci_msm_runtime_suspend()
2844 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);  in sdhci_msm_runtime_resume()  local
2847 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),  in sdhci_msm_runtime_resume()
2848 				       msm_host->bulk_clks);  in sdhci_msm_runtime_resume()
2855 	if (msm_host->restore_dll_config && msm_host->clk_rate) {  in sdhci_msm_runtime_resume()
2861 	dev_pm_opp_set_rate(dev, msm_host->clk_rate);  in sdhci_msm_runtime_resume()
2863 	return sdhci_msm_ice_resume(msm_host);  in sdhci_msm_runtime_resume()