25 #define CORE_MCI_VERSION		0x50
27 #define CORE_VERSION_MAJOR_MASK		(0xf << CORE_VERSION_MAJOR_SHIFT)
28 #define CORE_VERSION_MINOR_MASK		0xff
30 #define CORE_MCI_GENERICS		0x70
33 #define HC_MODE_EN		0x1
34 #define CORE_POWER		0x0
38 #define CORE_PWRCTL_BUS_OFF	BIT(0)
42 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
46 #define REQ_BUS_OFF		BIT(0)
50 #define INT_MASK		0xf
60 #define CORE_CMD_DAT_TRACK_SEL	BIT(0)
62 #define CORE_DDR_CAL_EN		BIT(0)
66 #define DLL_USR_CTL_POR_VAL	0x10800
71 #define DLL_CONFIG_3_LOW_FREQ_VAL	0x08
72 #define DLL_CONFIG_3_HIGH_FREQ_VAL	0x10
74 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
89 #define CORE_CSR_CDC_CTLR_CFG0		0x130
93 #define CORE_CSR_CDC_CTLR_CFG1		0x134
94 #define CORE_CSR_CDC_CAL_TIMER_CFG0	0x138
97 #define CORE_CSR_CDC_CAL_TIMER_CFG1	0x13C
98 #define CORE_CSR_CDC_REFCOUNT_CFG	0x140
99 #define CORE_CSR_CDC_COARSE_CAL_CFG	0x144
100 #define CORE_CDC_OFFSET_CFG		0x14C
101 #define CORE_CSR_CDC_DELAY_CFG		0x150
102 #define CORE_CDC_SLAVE_DDA_CFG		0x160
103 #define CORE_CSR_CDC_STATUS0		0x164
104 #define CORE_CALIBRATION_DONE		BIT(0)
106 #define CORE_CDC_ERROR_CODE_MASK	0x7000000
108 #define CORE_CSR_CDC_GEN_CFG		0x178
109 #define CORE_CDC_SWITCH_BYPASS_OFF	BIT(0)
112 #define CORE_CDC_T4_DLY_SEL		BIT(0)
118 #define DDR_CONFIG_POR_VAL	0x80040873
126 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)
145 #define CQHCI_VENDOR_CFG1	0xA00
146 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
175 	u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
181 	.core_mci_data_cnt = 0x35c,
182 	.core_mci_status = 0x324,
183 	.core_mci_fifo_cnt = 0x308,
184 	.core_mci_version = 0x318,
185 	.core_generics = 0x320,
186 	.core_testbus_config = 0x32c,
190 	.core_pwrctl_status = 0x240,
191 	.core_pwrctl_mask = 0x244,
192 	.core_pwrctl_clear = 0x248,
193 	.core_pwrctl_ctl = 0x24c,
194 	.core_sdcc_debug_reg = 0x358,
195 	.core_dll_config = 0x200,
196 	.core_dll_status = 0x208,
197 	.core_vendor_spec = 0x20c,
198 	.core_vendor_spec_adma_err_addr0 = 0x214,
199 	.core_vendor_spec_adma_err_addr1 = 0x218,
200 	.core_vendor_spec_func2 = 0x210,
201 	.core_vendor_spec_capabilities0 = 0x21c,
202 	.core_ddr_200_cfg = 0x224,
203 	.core_vendor_spec3 = 0x250,
204 	.core_dll_config_2 = 0x254,
205 	.core_dll_config_3 = 0x258,
206 	.core_ddr_config = 0x25c,
207 	.core_dll_usr_ctl = 0x388,
211 	.core_hc_mode = 0x78,
212 	.core_mci_data_cnt = 0x30,
213 	.core_mci_status = 0x34,
214 	.core_mci_fifo_cnt = 0x44,
215 	.core_mci_version = 0x050,
216 	.core_generics = 0x70,
217 	.core_testbus_config = 0x0cc,
221 	.core_pwrctl_status = 0xdc,
222 	.core_pwrctl_mask = 0xe0,
223 	.core_pwrctl_clear = 0xe4,
224 	.core_pwrctl_ctl = 0xe8,
225 	.core_sdcc_debug_reg = 0x124,
226 	.core_dll_config = 0x100,
227 	.core_dll_status = 0x108,
228 	.core_vendor_spec = 0x10c,
229 	.core_vendor_spec_adma_err_addr0 = 0x114,
230 	.core_vendor_spec_adma_err_addr1 = 0x118,
231 	.core_vendor_spec_func2 = 0x110,
232 	.core_vendor_spec_capabilities0 = 0x11c,
233 	.core_ddr_200_cfg = 0x184,
234 	.core_vendor_spec3 = 0x1b0,
235 	.core_dll_config_2 = 0x1b4,
236 	.core_ddr_config_old = 0x1b8,
237 	.core_ddr_config = 0x1bc,
356 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in msm_set_clock_rate_for_bus_mode()
403 		if (--wait_cnt == 0) {  in msm_dll_poll_ck_out_en()
414 	return 0;  in msm_dll_poll_ck_out_en()
421 		0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,  in msm_config_cm_dll_phase()
422 		0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8  in msm_config_cm_dll_phase()
430 	if (phase > 0xf)  in msm_config_cm_dll_phase()
440 	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */  in msm_config_cm_dll_phase()
441 	rc = msm_dll_poll_ck_out_en(host, 0);  in msm_config_cm_dll_phase()
446 	 * Write the selected DLL clock output phase (0 ... 15)  in msm_config_cm_dll_phase()
480  * setting for SD3.0 UHS-I card read operation (in SDR104
491 	u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };  in msm_find_most_appropriate_phase()
492 	u8 phases_per_row[MAX_PHASES] = { 0 };  in msm_find_most_appropriate_phase()
493 	int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;  in msm_find_most_appropriate_phase()
494 	int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;  in msm_find_most_appropriate_phase()
504 	for (cnt = 0; cnt < total_phases; cnt++) {  in msm_find_most_appropriate_phase()
514 			col_index = 0;  in msm_find_most_appropriate_phase()
521 	/* Check if phase-0 is present in first valid window? */  in msm_find_most_appropriate_phase()
522 	if (!ranges[0][0]) {  in msm_find_most_appropriate_phase()
524 		phase_0_raw_index = 0;  in msm_find_most_appropriate_phase()
528 				for (i = 0; i < phases_per_row[cnt]; i++) {  in msm_find_most_appropriate_phase()
541 		/* number of phases in raw where phase 0 is present */  in msm_find_most_appropriate_phase()
556 		for (cnt = 0; cnt < phases_0; cnt++) {  in msm_find_most_appropriate_phase()
563 		phases_per_row[phase_0_raw_index] = 0;  in msm_find_most_appropriate_phase()
567 	for (cnt = 0; cnt <= row_index; cnt++) {  in msm_find_most_appropriate_phase()
591 	u32 mclk_freq = 0, config;  in msm_cm_dll_set_freq()
597 		mclk_freq = 0;  in msm_cm_dll_set_freq()
626 	unsigned long flags, xo_clk = 0;  in msm_init_cm_dll()
680 		u32 mclk_freq = 0;  in msm_init_cm_dll()
694 		config &= ~(0xFF << 10);  in msm_init_cm_dll()
737 		config &= ~0xFF;  in msm_init_cm_dll()
762 		if (--wait_cnt == 0) {  in msm_init_cm_dll()
772 	return 0;  in msm_init_cm_dll()
800 	 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field  in msm_hc_select_default()
858 			pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",  in msm_hc_select_hs400()
943 	writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);  in sdhci_msm_cdclp533_calibration()
944 	writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);  in sdhci_msm_cdclp533_calibration()
945 	writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);  in sdhci_msm_cdclp533_calibration()
946 	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);  in sdhci_msm_cdclp533_calibration()
947 	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);  in sdhci_msm_cdclp533_calibration()
948 	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);  in sdhci_msm_cdclp533_calibration()
949 	writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);  in sdhci_msm_cdclp533_calibration()
950 	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);  in sdhci_msm_cdclp533_calibration()
951 	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);  in sdhci_msm_cdclp533_calibration()
1148 		return 0;  in sdhci_msm_restore_sdr_dll_config()
1186 	u8 phase, tuned_phases[16], tuned_phase_cnt = 0;  in sdhci_msm_execute_tuning()
1195 		return 0;  in sdhci_msm_execute_tuning()
1205 	msm_host->tuning_done = 0;  in sdhci_msm_execute_tuning()
1224 	phase = 0;  in sdhci_msm_execute_tuning()
1252 				tuned_phase_cnt = 0;  in sdhci_msm_execute_tuning()
1259 		if (rc < 0)  in sdhci_msm_execute_tuning()
1351 	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.  in sdhci_msm_set_uhs_signaling()
1381 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",  in sdhci_msm_set_uhs_signaling()
1405 		return 0;  in sdhci_msm_set_vmmc()
1417 		return 0;  in msm_toggle_vqmmc()
1428 			if (ret < 0) {  in msm_toggle_vqmmc()
1453 	load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;  in msm_config_vqmmc_mode()
1469 		return 0;  in sdhci_msm_set_vqmmc()
1474 	 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off  in sdhci_msm_set_vqmmc()
1541 	 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0  in sdhci_msm_check_power_status()
1583 	pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",  in sdhci_msm_dump_pwr_ctrl_regs()
1595 	u32 irq_status, irq_ack = 0;  in sdhci_msm_handle_pwr_irq()
1597 	u32 pwr_state = 0, io_level = 0;  in sdhci_msm_handle_pwr_irq()
1617 		if (retry == 0) {  in sdhci_msm_handle_pwr_irq()
1618 			pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",  in sdhci_msm_handle_pwr_irq()
1666 		if (ret < 0) {  in sdhci_msm_handle_pwr_irq()
1667 …(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",  in sdhci_msm_handle_pwr_irq()
1721 	dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",  in sdhci_msm_handle_pwr_irq()
1744 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in sdhci_msm_get_max_clock()
1766 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in __sdhci_msm_set_clock()
1768 	if (clock == 0)  in __sdhci_msm_set_clock()
1787 		host->mmc->actual_clock = msm_host->clk_rate = 0;  in sdhci_msm_set_clock()
1810 #define QCOM_ICE_REG_VERSION			0x0008
1812 #define QCOM_ICE_REG_FUSE_SETTING		0x0010
1813 #define QCOM_ICE_FUSE_SETTING_MASK		0x1
1814 #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK	0x2
1815 #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK	0x4
1817 #define QCOM_ICE_REG_BIST_STATUS		0x0070
1818 #define QCOM_ICE_BIST_STATUS_MASK		0xF0000000
1820 #define QCOM_ICE_REG_ADVANCED_CONTROL		0x1000
1832 	int minor = (regval >> 16) & 0xFF;  in sdhci_msm_ice_supported()
1833 	int step = regval & 0xFFFF;  in sdhci_msm_ice_supported()
1869 		return 0;  in sdhci_msm_ice_init()
1891 	return 0;  in sdhci_msm_ice_init()
1895 	return 0;  in sdhci_msm_ice_init()
1905 	 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0  in sdhci_msm_ice_low_power_mode_enable()
1907 	regval |= 0x7000;  in sdhci_msm_ice_low_power_mode_enable()
1917 	regval |= 0xD807100;  in sdhci_msm_ice_optimization_enable()
1962 		return 0;  in sdhci_msm_ice_resume()
2002 	for (i = 0; i < ARRAY_SIZE(key.words); i++)  in sdhci_msm_program_key()
2020 	return 0;  in sdhci_msm_ice_init()
2030 	return 0;  in sdhci_msm_ice_resume()
2042 	int cmd_error = 0;  in sdhci_msm_cqe_irq()
2043 	int data_error = 0;  in sdhci_msm_cqe_irq()
2049 	return 0;  in sdhci_msm_cqe_irq()
2200 	u32 req_type = 0;  in __sdhci_msm_check_write()
2230 		msm_host->pwr_irq_flag = 0;  in __sdhci_msm_check_write()
2243 	u32 req_type = 0;  in sdhci_msm_writew()
2255 	u32 req_type = 0;  in sdhci_msm_writeb()
2269 	u32 caps = 0, config;  in sdhci_msm_set_regulator_caps()
2304 	pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);  in sdhci_msm_set_regulator_caps()
2324 	return 0;  in sdhci_msm_register_vreg()
2338 		return 0;  in sdhci_msm_start_signal_voltage_switch()
2347 		/* Set 1.8V Signal Enable in the Host Control2 register to 0 */  in sdhci_msm_start_signal_voltage_switch()
2371 		return 0;  in sdhci_msm_start_signal_voltage_switch()
2392 			"DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2397 			"DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2402 			"Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2494 	int ret = 0;  in sdhci_msm_gcc_reset()
2547 	host->sdma_boundary = 0;  in sdhci_msm_probe()
2607 	msm_host->bulk_clks[0].clk = clk;  in sdhci_msm_probe()
2684 	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",  in sdhci_msm_probe()
2693 	dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",  in sdhci_msm_probe()
2696 	if (core_major == 1 && core_minor >= 0x42)  in sdhci_msm_probe()
2700 	 * SDCC 5 controller with major version 1, minor version 0x34 and later  in sdhci_msm_probe()
2703 	if (core_major == 1 && core_minor < 0x34)  in sdhci_msm_probe()
2710 	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {  in sdhci_msm_probe()
2717 	if (core_major == 1 && core_minor >= 0x49)  in sdhci_msm_probe()
2720 	if (core_major == 1 && core_minor >= 0x71)  in sdhci_msm_probe()
2734 	sdhci_msm_handle_pwr_irq(host, 0);  in sdhci_msm_probe()
2744 	if (msm_host->pwr_irq < 0) {  in sdhci_msm_probe()
2765 	host->max_timeout_count = 0xF;  in sdhci_msm_probe()
2787 	return 0;  in sdhci_msm_probe()
2810 		    0xffffffff);  in sdhci_msm_remove()
2823 	return 0;  in sdhci_msm_remove()
2833 	dev_pm_opp_set_rate(dev, 0);  in sdhci_msm_runtime_suspend()
2837 	return 0;  in sdhci_msm_runtime_suspend()