Lines Matching +full:rx +full:- +full:sample +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
36 #include <linux/mmc/slot-gpio.h>
43 /*--------------------------------------------------------------------------*/
45 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
54 /*--------------------------------------------------------------------------*/
91 /*--------------------------------------------------------------------------*/
93 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
100 /*--------------------------------------------------------------------------*/
330 #define PAD_DELAY_MAX 32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
333 /*--------------------------------------------------------------------------*/
438 u32 timeout_ns; /* data timeout ns */
463 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
464 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
466 /* cmd response sample selection for HS400 */
469 bool internal_cd; /* Use internal card-detect logic */
606 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
607 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
608 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
609 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
610 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
611 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
612 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
613 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
614 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
615 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
642 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
650 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
657 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
658 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
660 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
661 readl_poll_timeout(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
664 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
665 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
685 return 0xff - (u8) sum; in msdc_dma_calcs()
698 sg = data->sg; in msdc_dma_setup()
700 gpd = dma->gpd; in msdc_dma_setup()
701 bd = dma->bd; in msdc_dma_setup()
704 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
705 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
707 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
708 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
711 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
719 if (host->dev_comp->support_64g) { in msdc_dma_setup()
725 if (host->dev_comp->support_64g) { in msdc_dma_setup()
733 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
743 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
744 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
747 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
748 if (host->dev_comp->support_64g) in msdc_dma_setup()
749 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
750 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
751 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
756 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
757 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
758 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
765 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
768 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
769 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
771 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
775 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) in msdc_timeout_cal() argument
781 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
785 do_div(clk_ns, mmc->actual_clock); in msdc_timeout_cal()
786 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
791 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
792 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
795 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
799 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
805 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_timeout() argument
809 host->timeout_ns = ns; in msdc_set_timeout()
810 host->timeout_clks = clks; in msdc_set_timeout()
812 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_timeout()
813 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
817 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_busy_timeout() argument
821 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_busy_timeout()
822 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
828 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
829 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
830 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
831 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
832 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
840 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
841 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
842 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
843 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
844 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
846 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
850 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
861 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
865 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
866 host->mclk = 0; in msdc_set_mclk()
867 mmc->actual_clock = 0; in msdc_set_mclk()
868 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
872 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
873 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
874 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
875 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
877 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
887 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
889 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
891 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
892 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
897 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
898 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
899 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
902 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
904 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
907 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
910 sclk = host->src_clk_freq; in msdc_set_mclk()
913 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
915 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
917 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
918 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
921 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
923 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
924 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
925 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
929 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
933 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
934 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
935 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
936 mmc->actual_clock = sclk; in msdc_set_mclk()
937 host->mclk = hz; in msdc_set_mclk()
938 host->timing = timing; in msdc_set_mclk()
940 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
941 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
947 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
948 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
949 if (host->top_base) { in msdc_set_mclk()
950 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
951 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
952 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
953 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
955 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
956 host->base + tune_reg); in msdc_set_mclk()
959 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
960 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
961 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
962 if (host->top_base) { in msdc_set_mclk()
963 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
964 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
965 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
966 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
968 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
969 host->base + tune_reg); in msdc_set_mclk()
974 host->dev_comp->hs400_tune) in msdc_set_mclk()
975 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
977 host->hs400_cmd_int_delay); in msdc_set_mclk()
978 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1018 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1022 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1024 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1036 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1037 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1040 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1041 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1045 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1046 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1048 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1053 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1055 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1056 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1057 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1058 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1060 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1070 WARN_ON(host->data); in msdc_start_data()
1071 host->data = data; in msdc_start_data()
1072 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1074 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1075 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1076 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1077 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1078 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1079 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1080 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1086 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1088 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1091 cmd->error = 0; in msdc_auto_cmd_done()
1095 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1096 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1098 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1099 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1101 dev_err(host->dev, in msdc_auto_cmd_done()
1103 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1105 return cmd->error; in msdc_auto_cmd_done()
1109 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1120 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1121 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1123 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1124 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1136 if (host->error) in msdc_track_cmd_data()
1137 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1138 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1149 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1151 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1152 host->mrq = NULL; in msdc_request_done()
1153 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1155 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1156 if (mrq->data) in msdc_request_done()
1157 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1158 if (host->error) in msdc_request_done()
1161 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1174 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1177 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1179 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1186 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1187 done = !host->cmd; in msdc_cmd_done()
1188 host->cmd = NULL; in msdc_cmd_done()
1189 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1193 rsp = cmd->resp; in msdc_cmd_done()
1195 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1197 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1198 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1199 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1200 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1201 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1202 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1204 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1210 (cmd->opcode != MMC_SEND_TUNING_BLOCK && in msdc_cmd_done()
1211 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && in msdc_cmd_done()
1212 !host->hs400_tuning)) in msdc_cmd_done()
1220 cmd->error = -EILSEQ; in msdc_cmd_done()
1221 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1223 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1224 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1227 if (cmd->error) in msdc_cmd_done()
1228 dev_dbg(host->dev, in msdc_cmd_done()
1230 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1231 cmd->error); in msdc_cmd_done()
1248 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1251 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1252 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1257 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1259 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1262 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1263 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1277 WARN_ON(host->cmd); in msdc_start_command()
1278 host->cmd = cmd; in msdc_start_command()
1280 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1284 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1285 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1286 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1290 cmd->error = 0; in msdc_start_command()
1293 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1294 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1295 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1297 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1298 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1304 if ((cmd->error && in msdc_cmd_next()
1305 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1306 (cmd->opcode == MMC_SEND_TUNING_BLOCK || in msdc_cmd_next()
1307 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || in msdc_cmd_next()
1308 host->hs400_tuning))) || in msdc_cmd_next()
1309 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1311 else if (cmd == mrq->sbc) in msdc_cmd_next()
1312 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1313 else if (!cmd->data) in msdc_cmd_next()
1316 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1323 host->error = 0; in msdc_ops_request()
1324 WARN_ON(host->mrq); in msdc_ops_request()
1325 host->mrq = mrq; in msdc_ops_request()
1327 if (mrq->data) in msdc_ops_request()
1328 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1334 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1335 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1336 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1338 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1344 struct mmc_data *data = mrq->data; in msdc_pre_req()
1350 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1357 struct mmc_data *data = mrq->data; in msdc_post_req()
1362 if (data->host_cookie) { in msdc_post_req()
1363 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1370 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1371 !mrq->sbc) in msdc_data_xfer_next()
1372 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1390 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1391 done = !host->data; in msdc_data_xfer_done()
1393 host->data = NULL; in msdc_data_xfer_done()
1394 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1398 stop = data->stop; in msdc_data_xfer_done()
1400 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1401 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1402 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1403 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1406 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1409 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1411 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1414 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1416 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1417 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1419 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1420 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1422 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1424 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1425 data->bytes_xfered = 0; in msdc_data_xfer_done()
1428 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1430 data->error = -EILSEQ; in msdc_data_xfer_done()
1432 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1433 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1434 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1435 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1444 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1461 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1462 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1470 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1471 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1472 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1473 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1474 return -EINVAL; in msdc_ops_switch_volt()
1479 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1480 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1485 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1486 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1488 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1496 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1508 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1509 if (host->mrq) { in msdc_request_timeout()
1510 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1511 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1512 if (host->cmd) { in msdc_request_timeout()
1513 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1514 __func__, host->cmd->opcode); in msdc_request_timeout()
1515 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1516 host->cmd); in msdc_request_timeout()
1517 } else if (host->data) { in msdc_request_timeout()
1518 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1519 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1520 host->data->blocks); in msdc_request_timeout()
1521 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1522 host->data); in msdc_request_timeout()
1530 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1531 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1532 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1535 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1536 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1546 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1548 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1550 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1558 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1559 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1562 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1563 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1564 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1566 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1569 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1571 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1575 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1576 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1577 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1579 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1590 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1591 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1593 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1594 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1598 dat_err = -EILSEQ; in msdc_cmdq_irq()
1599 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1601 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1602 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1606 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", in msdc_cmdq_irq()
1624 spin_lock(&host->lock); in msdc_irq()
1625 events = readl(host->base + MSDC_INT); in msdc_irq()
1626 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1630 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1632 mrq = host->mrq; in msdc_irq()
1633 cmd = host->cmd; in msdc_irq()
1634 data = host->data; in msdc_irq()
1635 spin_unlock(&host->lock); in msdc_irq()
1641 if (host->internal_cd) in msdc_irq()
1649 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1653 writel(events, host->base + MSDC_INT); in msdc_irq()
1658 dev_err(host->dev, in msdc_irq()
1665 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1679 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1682 if (host->reset) { in msdc_init_hw()
1683 reset_control_assert(host->reset); in msdc_init_hw()
1685 reset_control_deassert(host->reset); in msdc_init_hw()
1689 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1695 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1696 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1697 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1700 if (host->internal_cd) { in msdc_init_hw()
1701 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1703 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1704 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1705 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1707 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1708 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1709 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1712 if (host->top_base) { in msdc_init_hw()
1713 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1714 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1716 writel(0, host->base + tune_reg); in msdc_init_hw()
1718 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1719 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1720 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1721 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1722 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1723 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1725 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1726 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1728 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1730 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1734 if (host->dev_comp->busy_check) in msdc_init_hw()
1735 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1737 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1738 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1740 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1741 if (host->top_base) in msdc_init_hw()
1742 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1745 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1748 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1750 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1753 /* use async fifo, then no need tune internal delay */ in msdc_init_hw()
1754 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1756 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1760 if (host->dev_comp->support_64g) in msdc_init_hw()
1761 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1763 if (host->dev_comp->data_tune) { in msdc_init_hw()
1764 if (host->top_base) { in msdc_init_hw()
1765 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1767 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1769 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1772 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1778 if (host->top_base) in msdc_init_hw()
1779 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1782 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1786 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1787 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1788 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1789 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1792 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1795 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1796 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1800 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1802 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1803 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1804 if (host->top_base) { in msdc_init_hw()
1805 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1806 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1807 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1808 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1809 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1810 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1811 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1812 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1814 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1815 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1817 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1824 if (host->internal_cd) { in msdc_deinit_hw()
1825 /* Disabled card-detect */ in msdc_deinit_hw()
1826 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1827 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1831 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1833 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1834 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1840 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
1841 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
1847 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
1848 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
1849 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
1852 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
1853 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1854 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
1856 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
1857 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
1858 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1859 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
1862 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
1863 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
1865 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1875 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1878 switch (ios->power_mode) { in msdc_ops_set_ios()
1880 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
1882 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
1883 ios->vdd); in msdc_ops_set_ios()
1885 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1891 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1892 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1894 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1896 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1900 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
1901 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
1903 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1904 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1905 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1912 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1913 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1916 static u32 test_delay_bit(u32 delay, u32 bit) in test_delay_bit() argument
1919 return delay & BIT(bit); in test_delay_bit()
1922 static int get_delay_len(u32 delay, u32 start_bit) in get_delay_len() argument
1926 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { in get_delay_len()
1927 if (test_delay_bit(delay, start_bit + i) == 0) in get_delay_len()
1930 return PAD_DELAY_MAX - start_bit; in get_delay_len()
1933 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) in get_best_delay() argument
1940 if (delay == 0) { in get_best_delay()
1941 dev_err(host->dev, "phase error: [map:%x]\n", delay); in get_best_delay()
1947 len = get_delay_len(delay, start); in get_best_delay()
1957 /* The rule is that to find the smallest delay cell */ in get_best_delay()
1962 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", in get_best_delay()
1963 delay, len_final, final_phase); in get_best_delay()
1973 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
1975 if (host->top_base) in msdc_set_cmd_delay()
1976 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
1979 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
1985 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
1987 if (host->top_base) in msdc_set_data_delay()
1988 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
1991 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2003 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2007 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2008 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2009 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2011 host->hs200_cmd_int_delay); in msdc_tune_response()
2013 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2037 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2062 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2065 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2070 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2074 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2080 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2082 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2085 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2086 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2099 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2100 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2102 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2103 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2104 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2106 host->hs200_cmd_int_delay); in hs400_tune_response()
2108 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2109 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2111 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2113 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2131 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2135 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2136 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2147 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2148 host->latch_ck); in msdc_tune_data()
2149 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2150 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2163 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2164 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2176 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2177 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2180 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2181 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2186 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2187 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2202 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2203 host->latch_ck); in msdc_tune_together()
2205 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2206 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2221 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2222 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2236 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2237 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2241 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2242 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2250 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2251 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2258 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2260 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2262 if (host->hs400_mode) { in msdc_execute_tuning()
2263 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2269 if (host->hs400_mode && in msdc_execute_tuning()
2270 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2274 if (ret == -EIO) { in msdc_execute_tuning()
2275 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2278 if (host->hs400_mode == false) { in msdc_execute_tuning()
2280 if (ret == -EIO) in msdc_execute_tuning()
2281 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2285 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2286 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2287 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2288 if (host->top_base) { in msdc_execute_tuning()
2289 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2291 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2300 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2302 if (host->top_base) in msdc_prepare_hs400_tuning()
2303 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2304 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2306 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2308 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2310 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2323 if (host->top_base) { in msdc_execute_hs400_tuning()
2324 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2326 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2327 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2328 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2330 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2331 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2332 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2333 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2336 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2338 if (host->top_base) in msdc_execute_hs400_tuning()
2339 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2342 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2350 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2354 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2357 if (host->top_base) in msdc_execute_hs400_tuning()
2358 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2361 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2364 if (host->top_base) in msdc_execute_hs400_tuning()
2365 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2367 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2369 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2374 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2375 return -EIO; in msdc_execute_hs400_tuning()
2382 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2384 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2392 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2394 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2402 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2405 if (!host->internal_cd) in msdc_get_cd()
2408 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2409 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2420 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2422 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2423 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2424 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2426 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2427 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2428 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2430 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2431 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2432 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2434 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2435 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2436 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2445 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2447 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2460 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2462 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2464 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2465 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2468 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2470 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2473 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2482 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2492 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2528 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2529 &host->latch_ck); in msdc_of_property_parse()
2531 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2532 &host->hs400_ds_delay); in msdc_of_property_parse()
2534 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2535 &host->hs400_ds_dly3); in msdc_of_property_parse()
2537 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2538 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2540 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2541 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2543 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2544 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2545 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2547 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2549 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2550 "supports-cqe")) in msdc_of_property_parse()
2551 host->cqhci = true; in msdc_of_property_parse()
2553 host->cqhci = false; in msdc_of_property_parse()
2561 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2562 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2563 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2565 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2566 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2567 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2569 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2570 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2571 host->bus_clk = NULL; in msdc_of_clock_parse()
2574 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2575 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2576 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2579 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2585 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2586 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2587 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2588 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2592 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2593 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2594 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2596 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2597 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2598 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2599 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2600 host->bulk_clks); in msdc_of_clock_parse()
2602 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2616 if (!pdev->dev.of_node) { in msdc_drv_probe()
2617 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2618 return -EINVAL; in msdc_drv_probe()
2622 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); in msdc_drv_probe()
2624 return -ENOMEM; in msdc_drv_probe()
2631 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2632 if (IS_ERR(host->base)) { in msdc_drv_probe()
2633 ret = PTR_ERR(host->base); in msdc_drv_probe()
2639 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2640 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2641 host->top_base = NULL; in msdc_drv_probe()
2652 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2654 if (IS_ERR(host->reset)) { in msdc_drv_probe()
2655 ret = PTR_ERR(host->reset); in msdc_drv_probe()
2659 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2660 if (host->irq < 0) { in msdc_drv_probe()
2661 ret = -EINVAL; in msdc_drv_probe()
2665 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2666 if (IS_ERR(host->pinctrl)) { in msdc_drv_probe()
2667 ret = PTR_ERR(host->pinctrl); in msdc_drv_probe()
2668 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); in msdc_drv_probe()
2672 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2673 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2674 ret = PTR_ERR(host->pins_default); in msdc_drv_probe()
2675 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2679 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2680 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2681 ret = PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2682 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2687 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2688 host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup"); in msdc_drv_probe()
2689 if (host->eint_irq > 0) { in msdc_drv_probe()
2690 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2691 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2692 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2693 host->pins_eint = NULL; in msdc_drv_probe()
2695 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2702 host->dev = &pdev->dev; in msdc_drv_probe()
2703 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2704 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2706 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2707 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2708 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2710 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2712 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2714 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2719 host->internal_cd = true; in msdc_drv_probe()
2722 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2723 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2725 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2726 if (host->cqhci) in msdc_drv_probe()
2727 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2729 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2730 if (host->dev_comp->support_64g) in msdc_drv_probe()
2731 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2733 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2734 mmc->max_blk_size = 2048; in msdc_drv_probe()
2735 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2736 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2737 if (host->dev_comp->support_64g) in msdc_drv_probe()
2738 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2740 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2741 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2743 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2744 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2746 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2747 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2749 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2750 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2751 ret = -ENOMEM; in msdc_drv_probe()
2754 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2755 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2756 spin_lock_init(&host->lock); in msdc_drv_probe()
2761 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
2766 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
2767 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2768 sizeof(*host->cq_host), in msdc_drv_probe()
2770 if (!host->cq_host) { in msdc_drv_probe()
2771 ret = -ENOMEM; in msdc_drv_probe()
2774 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2775 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2776 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2777 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2780 mmc->max_segs = 128; in msdc_drv_probe()
2782 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
2783 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
2786 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2787 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2791 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2792 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2793 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2794 pm_runtime_enable(host->dev); in msdc_drv_probe()
2802 pm_runtime_disable(host->dev); in msdc_drv_probe()
2808 if (host->dma.gpd) in msdc_drv_probe()
2809 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2811 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2812 if (host->dma.bd) in msdc_drv_probe()
2813 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2815 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2830 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2837 pm_runtime_disable(host->dev); in msdc_drv_remove()
2838 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2839 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
2841 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2842 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
2843 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2852 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2854 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2855 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2856 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2857 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2858 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2859 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2860 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2861 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2862 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2863 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2864 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2865 if (host->top_base) { in msdc_save_reg()
2866 host->save_para.emmc_top_control = in msdc_save_reg()
2867 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2868 host->save_para.emmc_top_cmd = in msdc_save_reg()
2869 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2870 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2871 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
2873 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
2880 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
2882 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
2883 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
2884 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
2885 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
2886 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
2887 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
2888 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
2889 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
2890 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
2891 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
2892 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
2893 if (host->top_base) { in msdc_restore_reg()
2894 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
2895 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
2896 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
2897 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
2898 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
2899 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
2901 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
2916 if (host->pins_eint) { in msdc_runtime_suspend()
2917 disable_irq(host->irq); in msdc_runtime_suspend()
2918 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
2939 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
2940 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
2941 enable_irq(host->irq); in msdc_runtime_resume()
2953 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
2957 val = readl(host->base + MSDC_INT); in msdc_suspend()
2958 writel(val, host->base + MSDC_INT); in msdc_suspend()
2962 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
2965 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
2976 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
2991 .name = "mtk-msdc",