Lines Matching full:dev
55 * @dev: the device structure
59 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
67 * @dev: the device structure
70 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
78 * @dev: the device structure
82 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
87 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
95 * @dev: the device structure
99 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
104 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
112 * @dev: the device structure
115 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
117 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
118 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
125 * @dev: the device structure
128 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
131 mei_hcsr_write(dev, reg); in mei_hcsr_set()
137 * @dev: the device structure
139 static inline void mei_hcsr_set_hig(struct mei_device *dev) in mei_hcsr_set_hig() argument
143 hcsr = mei_hcsr_read(dev) | H_IG; in mei_hcsr_set_hig()
144 mei_hcsr_set(dev, hcsr); in mei_hcsr_set_hig()
150 * @dev: the device structure
154 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
159 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
167 * @dev: the device structure
170 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
172 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
179 * @dev: mei device
184 static int mei_me_trc_status(struct mei_device *dev, u32 *trc) in mei_me_trc_status() argument
186 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_trc_status()
192 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc); in mei_me_trc_status()
200 * @dev: mei device
205 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
208 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
218 ret = hw->read_fws(dev, fw_src->status[i], in mei_me_fw_status()
220 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X", in mei_me_fw_status()
233 * @dev: mei device
240 static int mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
242 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
249 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
253 hw->read_fws(dev, PCI_CFG_HFS_1, ®); in mei_me_hw_config()
254 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_hw_config()
260 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
272 * @dev: mei device
276 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
278 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
292 * @dev: the device structure
295 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) in me_intr_disable() argument
298 mei_hcsr_set(dev, hcsr); in me_intr_disable()
304 * @dev: the device structure
307 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) in me_intr_clear() argument
310 mei_hcsr_write(dev, hcsr); in me_intr_clear()
316 * @dev: the device structure
318 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
320 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
322 me_intr_clear(dev, hcsr); in mei_me_intr_clear()
327 * @dev: the device structure
329 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
333 if (mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_intr_enable()
336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK; in mei_me_intr_enable()
337 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
343 * @dev: the device structure
345 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
347 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
349 me_intr_disable(dev, hcsr); in mei_me_intr_disable()
355 * @dev: the device structure
357 static void mei_me_synchronize_irq(struct mei_device *dev) in mei_me_synchronize_irq() argument
359 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_synchronize_irq()
370 * @dev: the device structure
372 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
374 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
378 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
384 * @dev: mei device
386 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
388 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
390 if (!mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_host_set_ready()
394 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
400 * @dev: mei device
403 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
405 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
413 * @dev: mei device
416 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
418 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
426 * @dev: mei device
429 static bool mei_me_hw_is_resetting(struct mei_device *dev) in mei_me_hw_is_resetting() argument
431 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_resetting()
439 * @dev: the device structure
441 static void mei_gsc_pxp_check(struct mei_device *dev) in mei_gsc_pxp_check() argument
443 struct mei_me_hw *hw = to_me_hw(dev); in mei_gsc_pxp_check()
446 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT) in mei_gsc_pxp_check()
449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5); in mei_gsc_pxp_check()
450 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5); in mei_gsc_pxp_check()
452 dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5); in mei_gsc_pxp_check()
453 dev->pxp_mode = MEI_DEV_PXP_READY; in mei_gsc_pxp_check()
455 dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5); in mei_gsc_pxp_check()
463 * @dev: mei device
466 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
468 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
469 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
470 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
471 dev->timeouts.hw_ready); in mei_me_hw_ready_wait()
472 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
473 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
474 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
478 mei_gsc_pxp_check(dev); in mei_me_hw_ready_wait()
480 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
481 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
488 * @dev: mei device
491 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
493 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
497 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
499 mei_me_host_set_ready(dev); in mei_me_hw_start()
507 * @dev: the device structure
511 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
516 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
527 * @dev: the device structure
531 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
533 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
539 * @dev: the device structure
543 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
545 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_empty_slots()
548 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
561 * @dev: the device structure
565 static u32 mei_me_hbuf_depth(const struct mei_device *dev) in mei_me_hbuf_depth() argument
567 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_depth()
575 * @dev: the device structure
583 static int mei_me_hbuf_write(struct mei_device *dev, in mei_me_hbuf_write() argument
596 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_me_hbuf_write()
598 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_hbuf_write()
599 dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots); in mei_me_hbuf_write()
610 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
614 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
621 mei_me_hcbww_write(dev, reg); in mei_me_hbuf_write()
624 mei_hcsr_set_hig(dev); in mei_me_hbuf_write()
625 if (!mei_me_hw_is_ready(dev)) in mei_me_hbuf_write()
634 * @dev: the device structure
638 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
644 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
654 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
661 * @dev: the device structure
667 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
673 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
676 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
681 mei_hcsr_set_hig(dev); in mei_me_read_slots()
688 * @dev: the device structure
690 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
692 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
696 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
700 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
707 * @dev: the device structure
709 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
711 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
715 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
721 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
728 * @dev: the device structure
732 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
734 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
737 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
739 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
743 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
744 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
745 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_pg_legacy_enter_sync()
746 dev->timeouts.pgi); in mei_me_pg_legacy_enter_sync()
747 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
749 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
750 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
756 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
765 * @dev: the device structure
769 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
771 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
774 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
777 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
779 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
781 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
782 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
783 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_pg_legacy_exit_sync()
784 dev->timeouts.pgi); in mei_me_pg_legacy_exit_sync()
785 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
788 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
793 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
794 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
798 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
799 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
800 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_pg_legacy_exit_sync()
801 dev->timeouts.pgi); in mei_me_pg_legacy_exit_sync()
802 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
804 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
810 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
819 * @dev: the device structure
823 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
825 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
826 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
832 * @dev: the device structure
836 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
838 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
839 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
847 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
853 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
856 dev->version.major_version, in mei_me_pg_is_enabled()
857 dev->version.minor_version, in mei_me_pg_is_enabled()
867 * @dev: the device structure
872 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
874 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
881 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
883 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
890 * @dev: the device structure
894 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
896 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
900 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
902 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
909 * @dev: the device structure
913 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
915 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
919 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
922 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
928 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
930 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
935 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
936 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
937 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_d0i3_enter_sync()
938 dev->timeouts.pgi); in mei_me_d0i3_enter_sync()
939 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
941 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
947 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
949 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
951 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
956 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
957 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
958 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_d0i3_enter_sync()
959 dev->timeouts.d0i3); in mei_me_d0i3_enter_sync()
960 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
962 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
963 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
974 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
975 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
985 * @dev: the device structure
989 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
991 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
994 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
997 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
1001 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
1004 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
1005 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
1012 * @dev: the device structure
1016 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
1018 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
1022 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
1024 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1027 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
1032 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
1034 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
1039 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1040 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
1041 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_d0i3_exit_sync()
1042 dev->timeouts.d0i3); in mei_me_d0i3_exit_sync()
1043 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1045 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
1046 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1057 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
1059 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
1067 * @dev: the device structure
1069 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
1071 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
1073 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
1076 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
1078 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
1079 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
1085 * @dev: the device structure
1088 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) in mei_me_d0i3_intr() argument
1090 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
1092 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
1094 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
1097 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
1102 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
1103 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
1109 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
1118 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
1119 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
1126 * @dev: the device structure
1129 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) in mei_me_pg_intr() argument
1131 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1134 mei_me_d0i3_intr(dev, intr_source); in mei_me_pg_intr()
1136 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1142 * @dev: the device structure
1146 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1148 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1151 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1153 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1159 * @dev: the device structure
1163 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1165 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1168 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1170 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1176 * @dev: the device structure
1181 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1183 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1188 mei_me_intr_enable(dev); in mei_me_hw_reset()
1190 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1198 pm_runtime_set_active(dev->dev); in mei_me_hw_reset()
1200 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1207 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1209 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1210 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1215 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_hw_reset()
1218 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1219 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1225 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1228 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1231 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1234 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1236 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1254 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1257 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1261 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); in mei_me_irq_quick_handler()
1264 me_intr_disable(dev, hcsr); in mei_me_irq_quick_handler()
1281 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1287 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1289 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1291 hcsr = mei_hcsr_read(dev); in mei_me_irq_thread_handler()
1292 me_intr_clear(dev, hcsr); in mei_me_irq_thread_handler()
1297 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1298 dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n", in mei_me_irq_thread_handler()
1299 dev->dev_state, dev->pxp_mode); in mei_me_irq_thread_handler()
1300 if (dev->dev_state == MEI_DEV_POWERING_DOWN || in mei_me_irq_thread_handler()
1301 dev->dev_state == MEI_DEV_POWER_DOWN) in mei_me_irq_thread_handler()
1302 mei_cl_all_disconnect(dev); in mei_me_irq_thread_handler()
1303 else if (dev->dev_state != MEI_DEV_DISABLED) in mei_me_irq_thread_handler()
1304 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1308 if (mei_me_hw_is_resetting(dev)) in mei_me_irq_thread_handler()
1309 mei_hcsr_set_hig(dev); in mei_me_irq_thread_handler()
1311 mei_me_pg_intr(dev, me_intr_src(hcsr)); in mei_me_irq_thread_handler()
1313 /* check if we need to start the dev */ in mei_me_irq_thread_handler()
1314 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1315 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1316 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1317 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1318 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1320 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1325 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1327 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1328 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); in mei_me_irq_thread_handler()
1337 dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n", in mei_me_irq_thread_handler()
1338 rets, dev->dev_state); in mei_me_irq_thread_handler()
1339 if (dev->dev_state != MEI_DEV_RESETTING && in mei_me_irq_thread_handler()
1340 dev->dev_state != MEI_DEV_DISABLED && in mei_me_irq_thread_handler()
1341 dev->dev_state != MEI_DEV_POWERING_DOWN && in mei_me_irq_thread_handler()
1342 dev->dev_state != MEI_DEV_POWER_DOWN) in mei_me_irq_thread_handler()
1343 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1348 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1355 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1356 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1357 rets = mei_irq_write_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1358 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1361 mei_irq_compl_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1364 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1365 mei_me_intr_enable(dev); in mei_me_irq_thread_handler()
1366 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1392 struct mei_device *dev = _dev; in mei_me_polling_thread() local
1396 dev_dbg(dev->dev, "kernel thread is running\n"); in mei_me_polling_thread()
1398 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_polling_thread()
1408 hcsr = mei_hcsr_read(dev); in mei_me_polling_thread()
1411 irq_ret = mei_me_irq_thread_handler(1, dev); in mei_me_polling_thread()
1413 dev_err(dev->dev, "irq_ret %d\n", irq_ret); in mei_me_polling_thread()
1481 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); in mei_me_fw_type_nm()
1507 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_fw_type_sps_4()
1532 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg); in mei_me_fw_type_sps_ign()
1535 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type); in mei_me_fw_type_sps_ign()
1743 struct mei_device *dev; in mei_me_dev_init() local
1747 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); in mei_me_dev_init()
1748 if (!dev) in mei_me_dev_init()
1751 hw = to_me_hw(dev); in mei_me_dev_init()
1754 dev->dr_dscr[i].size = cfg->dma_size[i]; in mei_me_dev_init()
1756 mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops); in mei_me_dev_init()
1759 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported; in mei_me_dev_init()
1761 dev->kind = cfg->kind; in mei_me_dev_init()
1763 return dev; in mei_me_dev_init()