Lines Matching +full:2 +full:mb
12 #define MSIX_BAR_ID 2
16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
70 #define MAX_ASID 2
75 * except MME and Scheduler ARCs which contain 2 DCCM blocks
81 #define NUM_OF_PSOC_ARC 2
87 #define NUM_OF_EDMA_PER_DCORE 2
89 #define NUM_OF_PDMA 2
95 #define NUM_OF_DEC_PER_DCORE 2
96 #define NUM_OF_ROT 2
100 #define NUM_OF_MME_WB_PER_DCORE 2
102 #define NUM_OF_VDEC_PER_DCORE 2
104 #define NUM_OF_PCIE_VDEC 2
115 #define NIC_NUMBER_OF_QM_PER_MACRO 2
117 #define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)
119 #define NIC_MAX_NUMBER_OF_PORTS (NIC_NUMBER_OF_ENGINES * 2)