Lines Matching +full:cmdq +full:- +full:sync
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
46 * - MSG_LONG/SHORT are allowed.
57 * - PQ entry is in kernel address space and the driver doesn't map it.
58 * - CP writes to MSIX register and to kernel address space (completion
73 #define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb"
74 #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb"
362 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_set_fixed_properties()
365 prop->max_queues = GOYA_QUEUE_ID_SIZE; in goya_set_fixed_properties()
366 prop->hw_queues_props = kcalloc(prop->max_queues, in goya_set_fixed_properties()
370 if (!prop->hw_queues_props) in goya_set_fixed_properties()
371 return -ENOMEM; in goya_set_fixed_properties()
374 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; in goya_set_fixed_properties()
375 prop->hw_queues_props[i].driver_only = 0; in goya_set_fixed_properties()
376 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; in goya_set_fixed_properties()
380 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; in goya_set_fixed_properties()
381 prop->hw_queues_props[i].driver_only = 1; in goya_set_fixed_properties()
382 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL; in goya_set_fixed_properties()
387 prop->hw_queues_props[i].type = QUEUE_TYPE_INT; in goya_set_fixed_properties()
388 prop->hw_queues_props[i].driver_only = 0; in goya_set_fixed_properties()
389 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER; in goya_set_fixed_properties()
392 prop->cfg_base_address = CFG_BASE; in goya_set_fixed_properties()
393 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE; in goya_set_fixed_properties()
394 prop->host_base_address = HOST_PHYS_BASE; in goya_set_fixed_properties()
395 prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE; in goya_set_fixed_properties()
396 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; in goya_set_fixed_properties()
397 prop->completion_mode = HL_COMPLETION_MODE_JOB; in goya_set_fixed_properties()
398 prop->dram_base_address = DRAM_PHYS_BASE; in goya_set_fixed_properties()
399 prop->dram_size = DRAM_PHYS_DEFAULT_SIZE; in goya_set_fixed_properties()
400 prop->dram_end_address = prop->dram_base_address + prop->dram_size; in goya_set_fixed_properties()
401 prop->dram_user_base_address = DRAM_BASE_ADDR_USER; in goya_set_fixed_properties()
403 prop->sram_base_address = SRAM_BASE_ADDR; in goya_set_fixed_properties()
404 prop->sram_size = SRAM_SIZE; in goya_set_fixed_properties()
405 prop->sram_end_address = prop->sram_base_address + prop->sram_size; in goya_set_fixed_properties()
406 prop->sram_user_base_address = prop->sram_base_address + in goya_set_fixed_properties()
409 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; in goya_set_fixed_properties()
410 prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR; in goya_set_fixed_properties()
411 if (hdev->pldm) in goya_set_fixed_properties()
412 prop->mmu_pgt_size = 0x800000; /* 8MB */ in goya_set_fixed_properties()
414 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; in goya_set_fixed_properties()
415 prop->mmu_pte_size = HL_PTE_SIZE; in goya_set_fixed_properties()
416 prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE; in goya_set_fixed_properties()
417 prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE; in goya_set_fixed_properties()
418 prop->dram_page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
419 prop->device_mem_alloc_default_page_size = prop->dram_page_size; in goya_set_fixed_properties()
420 prop->dram_supports_virtual_memory = true; in goya_set_fixed_properties()
422 prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT; in goya_set_fixed_properties()
423 prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT; in goya_set_fixed_properties()
424 prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT; in goya_set_fixed_properties()
425 prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT; in goya_set_fixed_properties()
426 prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT; in goya_set_fixed_properties()
427 prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK; in goya_set_fixed_properties()
428 prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK; in goya_set_fixed_properties()
429 prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK; in goya_set_fixed_properties()
430 prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK; in goya_set_fixed_properties()
431 prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK; in goya_set_fixed_properties()
432 prop->dmmu.start_addr = VA_DDR_SPACE_START; in goya_set_fixed_properties()
433 prop->dmmu.end_addr = VA_DDR_SPACE_END; in goya_set_fixed_properties()
434 prop->dmmu.page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
435 prop->dmmu.num_hops = MMU_ARCH_5_HOPS; in goya_set_fixed_properties()
436 prop->dmmu.last_mask = LAST_MASK; in goya_set_fixed_properties()
437 /* TODO: will be duplicated until implementing per-MMU props */ in goya_set_fixed_properties()
438 prop->dmmu.hop_table_size = prop->mmu_hop_table_size; in goya_set_fixed_properties()
439 prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; in goya_set_fixed_properties()
442 memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu)); in goya_set_fixed_properties()
443 prop->pmmu.start_addr = VA_HOST_SPACE_START; in goya_set_fixed_properties()
444 prop->pmmu.end_addr = VA_HOST_SPACE_END; in goya_set_fixed_properties()
445 prop->pmmu.page_size = PAGE_SIZE_4KB; in goya_set_fixed_properties()
446 prop->pmmu.num_hops = MMU_ARCH_5_HOPS; in goya_set_fixed_properties()
447 prop->pmmu.last_mask = LAST_MASK; in goya_set_fixed_properties()
448 /* TODO: will be duplicated until implementing per-MMU props */ in goya_set_fixed_properties()
449 prop->pmmu.hop_table_size = prop->mmu_hop_table_size; in goya_set_fixed_properties()
450 prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; in goya_set_fixed_properties()
453 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); in goya_set_fixed_properties()
454 prop->pmmu_huge.page_size = PAGE_SIZE_2MB; in goya_set_fixed_properties()
456 prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END; in goya_set_fixed_properties()
457 prop->cfg_size = CFG_SIZE; in goya_set_fixed_properties()
458 prop->max_asid = MAX_ASID; in goya_set_fixed_properties()
459 prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE; in goya_set_fixed_properties()
460 prop->high_pll = PLL_HIGH_DEFAULT; in goya_set_fixed_properties()
461 prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT; in goya_set_fixed_properties()
462 prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE; in goya_set_fixed_properties()
463 prop->max_power_default = MAX_POWER_DEFAULT; in goya_set_fixed_properties()
464 prop->dc_power_default = DC_POWER_DEFAULT; in goya_set_fixed_properties()
465 prop->tpc_enabled_mask = TPC_ENABLED_MASK; in goya_set_fixed_properties()
466 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; in goya_set_fixed_properties()
467 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; in goya_set_fixed_properties()
469 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, in goya_set_fixed_properties()
472 prop->max_pending_cs = GOYA_MAX_PENDING_CS; in goya_set_fixed_properties()
474 prop->first_available_user_interrupt = USHRT_MAX; in goya_set_fixed_properties()
477 prop->first_available_cq[i] = USHRT_MAX; in goya_set_fixed_properties()
479 prop->fw_cpu_boot_dev_sts0_valid = false; in goya_set_fixed_properties()
480 prop->fw_cpu_boot_dev_sts1_valid = false; in goya_set_fixed_properties()
481 prop->hard_reset_done_by_fw = false; in goya_set_fixed_properties()
482 prop->gic_interrupts_enable = true; in goya_set_fixed_properties()
484 prop->server_type = HL_SERVER_TYPE_UNKNOWN; in goya_set_fixed_properties()
486 prop->clk_pll_index = HL_GOYA_MME_PLL; in goya_set_fixed_properties()
488 prop->use_get_power_for_reset_history = true; in goya_set_fixed_properties()
490 prop->configurable_stop_on_err = true; in goya_set_fixed_properties()
492 prop->set_max_power_on_device_init = true; in goya_set_fixed_properties()
494 prop->dma_mask = 48; in goya_set_fixed_properties()
500 * goya_pci_bars_map - Map PCI BARS of Goya device
518 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + in goya_pci_bars_map()
519 (CFG_BASE - SRAM_BASE_ADDR); in goya_pci_bars_map()
526 struct goya_device *goya = hdev->asic_specific; in goya_set_ddr_bar_base()
531 if ((goya) && (goya->ddr_bar_cur_addr == addr)) in goya_set_ddr_bar_base()
534 /* Inbound Region 1 - Bar 4 - Point to DDR */ in goya_set_ddr_bar_base()
543 old_addr = goya->ddr_bar_cur_addr; in goya_set_ddr_bar_base()
544 goya->ddr_bar_cur_addr = addr; in goya_set_ddr_bar_base()
551 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
564 if (hdev->asic_prop.iatu_done_by_fw) in goya_init_iatu()
567 /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */ in goya_init_iatu()
575 /* Inbound Region 1 - Bar 4 - Point to DDR */ in goya_init_iatu()
583 /* Outbound Region 0 - Point to Host */ in goya_init_iatu()
598 * goya_early_init - GOYA early initialization code
610 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_early_init()
611 struct pci_dev *pdev = hdev->pdev; in goya_early_init()
618 dev_err(hdev->dev, "Failed to get fixed properties\n"); in goya_early_init()
626 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", in goya_early_init()
628 rc = -ENODEV; in goya_early_init()
635 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n", in goya_early_init()
637 rc = -ENODEV; in goya_early_init()
641 prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); in goya_early_init()
642 hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID); in goya_early_init()
645 if (hdev->asic_prop.fw_security_enabled) { in goya_early_init()
646 hdev->asic_prop.iatu_done_by_fw = true; in goya_early_init()
658 hdev->asic_prop.iatu_done_by_fw = true; in goya_early_init()
666 * version to determine whether we run with a security-enabled firmware in goya_early_init()
670 if (hdev->reset_on_preboot_fail) in goya_early_init()
671 hdev->asic_funcs->hw_fini(hdev, true, false); in goya_early_init()
676 dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); in goya_early_init()
677 hdev->asic_funcs->hw_fini(hdev, true, false); in goya_early_init()
680 if (!hdev->pldm) { in goya_early_init()
683 dev_warn(hdev->dev, in goya_early_init()
692 kfree(hdev->asic_prop.hw_queues_props); in goya_early_init()
697 * goya_early_fini - GOYA early finalization code
706 kfree(hdev->asic_prop.hw_queues_props); in goya_early_fini()
721 struct goya_device *goya = hdev->asic_specific; in goya_qman0_set_security()
723 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_qman0_set_security()
735 * goya_fetch_psoc_frequency - Fetch PSOC frequency values
742 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_fetch_psoc_frequency()
747 if (hdev->asic_prop.fw_security_enabled) { in goya_fetch_psoc_frequency()
748 struct goya_device *goya = hdev->asic_specific; in goya_fetch_psoc_frequency()
750 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_fetch_psoc_frequency()
782 dev_warn(hdev->dev, in goya_fetch_psoc_frequency()
789 prop->psoc_timestamp_frequency = freq; in goya_fetch_psoc_frequency()
790 prop->psoc_pci_pll_nr = nr; in goya_fetch_psoc_frequency()
791 prop->psoc_pci_pll_nf = nf; in goya_fetch_psoc_frequency()
792 prop->psoc_pci_pll_od = od; in goya_fetch_psoc_frequency()
793 prop->psoc_pci_pll_div_factor = div_fctr; in goya_fetch_psoc_frequency()
797 * goya_set_frequency - set the frequency of the device
811 struct goya_device *goya = hdev->asic_specific; in goya_set_frequency()
813 if ((goya->pm_mng_profile == PM_MANUAL) || in goya_set_frequency()
814 (goya->curr_pll_profile == freq)) in goya_set_frequency()
817 dev_dbg(hdev->dev, "Changing device frequency to %s\n", in goya_set_frequency()
822 goya->curr_pll_profile = freq; in goya_set_frequency()
832 struct hl_device *hdev = goya_work->hdev; in goya_set_freq_to_low_job()
834 mutex_lock(&hdev->fpriv_list_lock); in goya_set_freq_to_low_job()
836 if (!hdev->is_compute_ctx_active) in goya_set_freq_to_low_job()
839 mutex_unlock(&hdev->fpriv_list_lock); in goya_set_freq_to_low_job()
841 schedule_delayed_work(&goya_work->work_freq, in goya_set_freq_to_low_job()
847 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_late_init()
848 struct goya_device *goya = hdev->asic_specific; in goya_late_init()
855 dev_err(hdev->dev, in goya_late_init()
862 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc); in goya_late_init()
880 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc); in goya_late_init()
888 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
892 dev_err(hdev->dev, in goya_late_init()
898 goya->curr_pll_profile = PLL_LOW; in goya_late_init()
900 goya->pm_mng_profile = PM_AUTO; in goya_late_init()
904 schedule_delayed_work(&goya->goya_work->work_freq, in goya_late_init()
911 * goya_late_fini - GOYA late tear-down code
919 struct goya_device *goya = hdev->asic_specific; in goya_late_fini()
921 cancel_delayed_work_sync(&goya->goya_work->work_freq); in goya_late_fini()
928 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_set_pci_memory_regions()
932 region = &hdev->pci_mem_region[PCI_REGION_CFG]; in goya_set_pci_memory_regions()
933 region->region_base = CFG_BASE; in goya_set_pci_memory_regions()
934 region->region_size = CFG_SIZE; in goya_set_pci_memory_regions()
935 region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR; in goya_set_pci_memory_regions()
936 region->bar_size = CFG_BAR_SIZE; in goya_set_pci_memory_regions()
937 region->bar_id = SRAM_CFG_BAR_ID; in goya_set_pci_memory_regions()
938 region->used = 1; in goya_set_pci_memory_regions()
941 region = &hdev->pci_mem_region[PCI_REGION_SRAM]; in goya_set_pci_memory_regions()
942 region->region_base = SRAM_BASE_ADDR; in goya_set_pci_memory_regions()
943 region->region_size = SRAM_SIZE; in goya_set_pci_memory_regions()
944 region->offset_in_bar = 0; in goya_set_pci_memory_regions()
945 region->bar_size = CFG_BAR_SIZE; in goya_set_pci_memory_regions()
946 region->bar_id = SRAM_CFG_BAR_ID; in goya_set_pci_memory_regions()
947 region->used = 1; in goya_set_pci_memory_regions()
950 region = &hdev->pci_mem_region[PCI_REGION_DRAM]; in goya_set_pci_memory_regions()
951 region->region_base = DRAM_PHYS_BASE; in goya_set_pci_memory_regions()
952 region->region_size = hdev->asic_prop.dram_size; in goya_set_pci_memory_regions()
953 region->offset_in_bar = 0; in goya_set_pci_memory_regions()
954 region->bar_size = prop->dram_pci_bar_size; in goya_set_pci_memory_regions()
955 region->bar_id = DDR_BAR_ID; in goya_set_pci_memory_regions()
956 region->used = 1; in goya_set_pci_memory_regions()
960 * goya_sw_init - Goya software initialization code
973 return -ENOMEM; in goya_sw_init()
976 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE; in goya_sw_init()
978 goya->mme_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
979 goya->tpc_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
980 goya->ic_clk = GOYA_PLL_FREQ_LOW; in goya_sw_init()
982 hdev->asic_specific = goya; in goya_sw_init()
985 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), in goya_sw_init()
986 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0); in goya_sw_init()
987 if (!hdev->dma_pool) { in goya_sw_init()
988 dev_err(hdev->dev, "failed to create DMA pool\n"); in goya_sw_init()
989 rc = -ENOMEM; in goya_sw_init()
993 hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, in goya_sw_init()
994 &hdev->cpu_accessible_dma_address, in goya_sw_init()
997 if (!hdev->cpu_accessible_dma_mem) { in goya_sw_init()
998 rc = -ENOMEM; in goya_sw_init()
1002 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n", in goya_sw_init()
1003 &hdev->cpu_accessible_dma_address); in goya_sw_init()
1005 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); in goya_sw_init()
1006 if (!hdev->cpu_accessible_dma_pool) { in goya_sw_init()
1007 dev_err(hdev->dev, in goya_sw_init()
1009 rc = -ENOMEM; in goya_sw_init()
1013 rc = gen_pool_add(hdev->cpu_accessible_dma_pool, in goya_sw_init()
1014 (uintptr_t) hdev->cpu_accessible_dma_mem, in goya_sw_init()
1015 HL_CPU_ACCESSIBLE_MEM_SIZE, -1); in goya_sw_init()
1017 dev_err(hdev->dev, in goya_sw_init()
1019 rc = -EFAULT; in goya_sw_init()
1023 spin_lock_init(&goya->hw_queues_lock); in goya_sw_init()
1024 hdev->supports_coresight = true; in goya_sw_init()
1025 hdev->asic_prop.supports_compute_reset = true; in goya_sw_init()
1026 hdev->asic_prop.allow_inference_soft_reset = true; in goya_sw_init()
1027 hdev->supports_wait_for_multi_cs = false; in goya_sw_init()
1028 hdev->supports_ctx_switch = true; in goya_sw_init()
1030 hdev->asic_funcs->set_pci_memory_regions(hdev); in goya_sw_init()
1032 goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL); in goya_sw_init()
1033 if (!goya->goya_work) { in goya_sw_init()
1034 rc = -ENOMEM; in goya_sw_init()
1038 goya->goya_work->hdev = hdev; in goya_sw_init()
1039 INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job); in goya_sw_init()
1044 gen_pool_destroy(hdev->cpu_accessible_dma_pool); in goya_sw_init()
1046 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, in goya_sw_init()
1047 hdev->cpu_accessible_dma_address); in goya_sw_init()
1049 dma_pool_destroy(hdev->dma_pool); in goya_sw_init()
1057 * goya_sw_fini - Goya software tear-down code
1064 struct goya_device *goya = hdev->asic_specific; in goya_sw_fini()
1066 gen_pool_destroy(hdev->cpu_accessible_dma_pool); in goya_sw_fini()
1068 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem, in goya_sw_fini()
1069 hdev->cpu_accessible_dma_address); in goya_sw_fini()
1071 dma_pool_destroy(hdev->dma_pool); in goya_sw_fini()
1073 kfree(goya->goya_work); in goya_sw_fini()
1082 struct goya_device *goya = hdev->asic_specific; in goya_init_dma_qman()
1086 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman()
1119 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_init_dma_qman()
1124 if (hdev->stop_on_err) in goya_init_dma_qman()
1135 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); in goya_init_dma_ch()
1149 (dma_id - 1) * 4; in goya_init_dma_ch()
1158 * goya_init_dma_qmans - Initialize QMAN DMA registers
1167 struct goya_device *goya = hdev->asic_specific; in goya_init_dma_qmans()
1171 if (goya->hw_cap_initialized & HW_CAP_DMA) in goya_init_dma_qmans()
1174 q = &hdev->kernel_queues[0]; in goya_init_dma_qmans()
1177 q->cq_id = q->msi_vec = i; in goya_init_dma_qmans()
1178 goya_init_dma_qman(hdev, i, q->bus_address); in goya_init_dma_qmans()
1182 goya->hw_cap_initialized |= HW_CAP_DMA; in goya_init_dma_qmans()
1186 * goya_disable_external_queues - Disable external queues
1193 struct goya_device *goya = hdev->asic_specific; in goya_disable_external_queues()
1195 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_disable_external_queues()
1239 dev_err(hdev->dev, in goya_stop_queue()
1241 return -EINVAL; in goya_stop_queue()
1248 * goya_stop_external_queues - Stop external queues
1259 struct goya_device *goya = hdev->asic_specific; in goya_stop_external_queues()
1261 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_stop_external_queues()
1270 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n"); in goya_stop_external_queues()
1271 retval = -EIO; in goya_stop_external_queues()
1280 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n"); in goya_stop_external_queues()
1281 retval = -EIO; in goya_stop_external_queues()
1290 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n"); in goya_stop_external_queues()
1291 retval = -EIO; in goya_stop_external_queues()
1300 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n"); in goya_stop_external_queues()
1301 retval = -EIO; in goya_stop_external_queues()
1310 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n"); in goya_stop_external_queues()
1311 retval = -EIO; in goya_stop_external_queues()
1318 * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1327 struct goya_device *goya = hdev->asic_specific; in goya_init_cpu_queues()
1328 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_init_cpu_queues()
1331 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; in goya_init_cpu_queues()
1334 if (!hdev->cpu_queues_enable) in goya_init_cpu_queues()
1337 if (goya->hw_cap_initialized & HW_CAP_CPU_Q) in goya_init_cpu_queues()
1340 eq = &hdev->event_queue; in goya_init_cpu_queues()
1342 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); in goya_init_cpu_queues()
1343 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); in goya_init_cpu_queues()
1345 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); in goya_init_cpu_queues()
1346 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); in goya_init_cpu_queues()
1376 dev_err(hdev->dev, in goya_init_cpu_queues()
1378 return -EIO; in goya_init_cpu_queues()
1382 if (prop->fw_cpu_boot_dev_sts0_valid) in goya_init_cpu_queues()
1383 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0); in goya_init_cpu_queues()
1385 if (prop->fw_cpu_boot_dev_sts1_valid) in goya_init_cpu_queues()
1386 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1); in goya_init_cpu_queues()
1388 goya->hw_cap_initialized |= HW_CAP_CPU_Q; in goya_init_cpu_queues()
1444 tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE); in _goya_tpc_mbist_workaround()
1454 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n", in _goya_tpc_mbist_workaround()
1482 dev_err(hdev->dev, in _goya_tpc_mbist_workaround()
1503 struct goya_device *goya = hdev->asic_specific; in goya_tpc_mbist_workaround()
1506 if (hdev->pldm) in goya_tpc_mbist_workaround()
1509 if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST) in goya_tpc_mbist_workaround()
1517 goya->hw_cap_initialized |= HW_CAP_TPC_MBIST; in goya_tpc_mbist_workaround()
1521 * goya_init_golden_registers - Initialize golden registers
1530 struct goya_device *goya = hdev->asic_specific; in goya_init_golden_registers()
1534 if (goya->hw_cap_initialized & HW_CAP_GOLDEN) in goya_init_golden_registers()
1810 * Workaround for H2 #HW-23 bug in goya_init_golden_registers()
1820 goya->hw_cap_initialized |= HW_CAP_GOLDEN; in goya_init_golden_registers()
1840 qman_base_addr = hdev->asic_prop.sram_base_address + in goya_init_mme_qman()
1894 /* CMDQ CQ has 20 cache lines */ in goya_init_mme_cmdq()
1911 struct goya_device *goya = hdev->asic_specific; in goya_init_mme_qmans()
1914 if (goya->hw_cap_initialized & HW_CAP_MME) in goya_init_mme_qmans()
1926 goya->hw_cap_initialized |= HW_CAP_MME; in goya_init_mme_qmans()
1935 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); in goya_init_tpc_qman()
1947 qman_base_addr = hdev->asic_prop.sram_base_address + base_off; in goya_init_tpc_qman()
1984 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); in goya_init_tpc_cmdq()
2018 struct goya_device *goya = hdev->asic_specific; in goya_init_tpc_qmans()
2020 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW - in goya_init_tpc_qmans()
2024 if (goya->hw_cap_initialized & HW_CAP_TPC) in goya_init_tpc_qmans()
2049 goya->hw_cap_initialized |= HW_CAP_TPC; in goya_init_tpc_qmans()
2053 * goya_disable_internal_queues - Disable internal queues
2060 struct goya_device *goya = hdev->asic_specific; in goya_disable_internal_queues()
2062 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_disable_internal_queues()
2069 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_disable_internal_queues()
2098 * goya_stop_internal_queues - Stop internal queues
2107 struct goya_device *goya = hdev->asic_specific; in goya_stop_internal_queues()
2110 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_stop_internal_queues()
2125 dev_err(hdev->dev, "failed to stop MME QMAN\n"); in goya_stop_internal_queues()
2126 retval = -EIO; in goya_stop_internal_queues()
2135 dev_err(hdev->dev, "failed to stop MME CMDQ\n"); in goya_stop_internal_queues()
2136 retval = -EIO; in goya_stop_internal_queues()
2140 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_stop_internal_queues()
2149 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n"); in goya_stop_internal_queues()
2150 retval = -EIO; in goya_stop_internal_queues()
2159 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n"); in goya_stop_internal_queues()
2160 retval = -EIO; in goya_stop_internal_queues()
2169 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n"); in goya_stop_internal_queues()
2170 retval = -EIO; in goya_stop_internal_queues()
2179 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n"); in goya_stop_internal_queues()
2180 retval = -EIO; in goya_stop_internal_queues()
2189 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n"); in goya_stop_internal_queues()
2190 retval = -EIO; in goya_stop_internal_queues()
2199 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n"); in goya_stop_internal_queues()
2200 retval = -EIO; in goya_stop_internal_queues()
2209 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n"); in goya_stop_internal_queues()
2210 retval = -EIO; in goya_stop_internal_queues()
2219 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n"); in goya_stop_internal_queues()
2220 retval = -EIO; in goya_stop_internal_queues()
2229 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n"); in goya_stop_internal_queues()
2230 retval = -EIO; in goya_stop_internal_queues()
2239 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n"); in goya_stop_internal_queues()
2240 retval = -EIO; in goya_stop_internal_queues()
2249 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n"); in goya_stop_internal_queues()
2250 retval = -EIO; in goya_stop_internal_queues()
2259 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n"); in goya_stop_internal_queues()
2260 retval = -EIO; in goya_stop_internal_queues()
2269 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n"); in goya_stop_internal_queues()
2270 retval = -EIO; in goya_stop_internal_queues()
2279 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n"); in goya_stop_internal_queues()
2280 retval = -EIO; in goya_stop_internal_queues()
2289 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n"); in goya_stop_internal_queues()
2290 retval = -EIO; in goya_stop_internal_queues()
2299 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n"); in goya_stop_internal_queues()
2300 retval = -EIO; in goya_stop_internal_queues()
2308 struct goya_device *goya = hdev->asic_specific; in goya_dma_stall()
2310 if (!(goya->hw_cap_initialized & HW_CAP_DMA)) in goya_dma_stall()
2322 struct goya_device *goya = hdev->asic_specific; in goya_tpc_stall()
2324 if (!(goya->hw_cap_initialized & HW_CAP_TPC)) in goya_tpc_stall()
2339 struct goya_device *goya = hdev->asic_specific; in goya_mme_stall()
2341 if (!(goya->hw_cap_initialized & HW_CAP_MME)) in goya_mme_stall()
2349 struct goya_device *goya = hdev->asic_specific; in goya_enable_msix()
2350 int cq_cnt = hdev->asic_prop.completion_queues_count; in goya_enable_msix()
2353 if (goya->hw_cap_initialized & HW_CAP_MSIX) in goya_enable_msix()
2356 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES, in goya_enable_msix()
2359 dev_err(hdev->dev, in goya_enable_msix()
2360 "MSI-X: Failed to enable support -- %d/%d\n", in goya_enable_msix()
2366 irq = pci_irq_vector(hdev->pdev, i); in goya_enable_msix()
2368 &hdev->completion_queue[i]); in goya_enable_msix()
2370 dev_err(hdev->dev, "Failed to request IRQ %d", irq); in goya_enable_msix()
2375 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); in goya_enable_msix()
2379 &hdev->event_queue); in goya_enable_msix()
2381 dev_err(hdev->dev, "Failed to request IRQ %d", irq); in goya_enable_msix()
2385 goya->hw_cap_initialized |= HW_CAP_MSIX; in goya_enable_msix()
2390 free_irq(pci_irq_vector(hdev->pdev, i), in goya_enable_msix()
2391 &hdev->completion_queue[i]); in goya_enable_msix()
2393 pci_free_irq_vectors(hdev->pdev); in goya_enable_msix()
2399 struct goya_device *goya = hdev->asic_specific; in goya_sync_irqs()
2402 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) in goya_sync_irqs()
2406 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) in goya_sync_irqs()
2407 synchronize_irq(pci_irq_vector(hdev->pdev, i)); in goya_sync_irqs()
2409 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX)); in goya_sync_irqs()
2414 struct goya_device *goya = hdev->asic_specific; in goya_disable_msix()
2417 if (!(goya->hw_cap_initialized & HW_CAP_MSIX)) in goya_disable_msix()
2422 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX); in goya_disable_msix()
2423 free_irq(irq, &hdev->event_queue); in goya_disable_msix()
2425 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { in goya_disable_msix()
2426 irq = pci_irq_vector(hdev->pdev, i); in goya_disable_msix()
2427 free_irq(irq, &hdev->completion_queue[i]); in goya_disable_msix()
2430 pci_free_irq_vectors(hdev->pdev); in goya_disable_msix()
2432 goya->hw_cap_initialized &= ~HW_CAP_MSIX; in goya_disable_msix()
2438 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in goya_enable_timestamp()
2440 /* Zero the lower/upper parts of the 64-bit counter */ in goya_enable_timestamp()
2441 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); in goya_enable_timestamp()
2442 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); in goya_enable_timestamp()
2445 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); in goya_enable_timestamp()
2451 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); in goya_disable_timestamp()
2458 if (hdev->pldm) in goya_halt_engines()
2488 * goya_load_firmware_to_device() - Load LINUX FW code to device.
2493 * Return: 0 on success, non-zero for failure.
2499 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; in goya_load_firmware_to_device()
2505 * goya_load_boot_fit_to_device() - Load boot fit to device.
2510 * Return: 0 on success, non-zero for failure.
2516 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET; in goya_load_boot_fit_to_device()
2526 dynamic_loader = &hdev->fw_loader.dynamic_loader; in goya_init_dynamic_firmware_loader()
2531 * hard-coded) in later stages of the protocol those values will be in goya_init_dynamic_firmware_loader()
2533 * will always be up-to-date in goya_init_dynamic_firmware_loader()
2535 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs; in goya_init_dynamic_firmware_loader()
2536 dyn_regs->kmd_msg_to_cpu = in goya_init_dynamic_firmware_loader()
2538 dyn_regs->cpu_cmd_status_to_host = in goya_init_dynamic_firmware_loader()
2541 dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC; in goya_init_dynamic_firmware_loader()
2548 static_loader = &hdev->fw_loader.static_loader; in goya_init_static_firmware_loader()
2550 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; in goya_init_static_firmware_loader()
2551 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN; in goya_init_static_firmware_loader()
2552 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU; in goya_init_static_firmware_loader()
2553 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST; in goya_init_static_firmware_loader()
2554 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; in goya_init_static_firmware_loader()
2555 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0; in goya_init_static_firmware_loader()
2556 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1; in goya_init_static_firmware_loader()
2557 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0; in goya_init_static_firmware_loader()
2558 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1; in goya_init_static_firmware_loader()
2559 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET; in goya_init_static_firmware_loader()
2560 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET; in goya_init_static_firmware_loader()
2561 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR)); in goya_init_static_firmware_loader()
2566 struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load; in goya_init_firmware_preload_params()
2568 pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS; in goya_init_firmware_preload_params()
2569 pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0; in goya_init_firmware_preload_params()
2570 pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1; in goya_init_firmware_preload_params()
2571 pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0; in goya_init_firmware_preload_params()
2572 pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1; in goya_init_firmware_preload_params()
2573 pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; in goya_init_firmware_preload_params()
2578 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_init_firmware_loader()
2579 struct fw_load_mgr *fw_loader = &hdev->fw_loader; in goya_init_firmware_loader()
2582 fw_loader->fw_comp_loaded = FW_TYPE_NONE; in goya_init_firmware_loader()
2583 fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE; in goya_init_firmware_loader()
2584 fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE; in goya_init_firmware_loader()
2585 fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC; in goya_init_firmware_loader()
2586 fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC; in goya_init_firmware_loader()
2587 fw_loader->skip_bmc = false; in goya_init_firmware_loader()
2588 fw_loader->sram_bar_id = SRAM_CFG_BAR_ID; in goya_init_firmware_loader()
2589 fw_loader->dram_bar_id = DDR_BAR_ID; in goya_init_firmware_loader()
2591 if (prop->dynamic_fw_load) in goya_init_firmware_loader()
2599 struct goya_device *goya = hdev->asic_specific; in goya_init_cpu()
2602 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU)) in goya_init_cpu()
2605 if (goya->hw_cap_initialized & HW_CAP_CPU) in goya_init_cpu()
2609 * Before pushing u-boot/linux to device, need to set the ddr bar to in goya_init_cpu()
2613 dev_err(hdev->dev, in goya_init_cpu()
2615 return -EIO; in goya_init_cpu()
2623 goya->hw_cap_initialized |= HW_CAP_CPU; in goya_init_cpu()
2634 if (hdev->pldm) in goya_mmu_update_asid_hop0_addr()
2652 dev_err(hdev->dev, in goya_mmu_update_asid_hop0_addr()
2662 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_init()
2663 struct goya_device *goya = hdev->asic_specific; in goya_mmu_init()
2667 if (!hdev->mmu_enable) in goya_mmu_init()
2670 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_mmu_init()
2673 hdev->dram_default_page_mapping = true; in goya_mmu_init()
2675 for (i = 0 ; i < prop->max_asid ; i++) { in goya_mmu_init()
2676 hop0_addr = prop->mmu_pgt_addr + in goya_mmu_init()
2677 (i * prop->mmu_hop_table_size); in goya_mmu_init()
2681 dev_err(hdev->dev, in goya_mmu_init()
2687 goya->hw_cap_initialized |= HW_CAP_MMU; in goya_mmu_init()
2710 * goya_hw_init - Goya hardware initialization code
2719 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_hw_init()
2735 dev_err(hdev->dev, "failed to initialize CPU\n"); in goya_hw_init()
2748 ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) { in goya_hw_init()
2749 dev_err(hdev->dev, in goya_hw_init()
2751 return -EIO; in goya_hw_init()
2768 /* MSI-X must be enabled before CPU queues are initialized */ in goya_hw_init()
2773 /* Perform read from the device to flush all MSI-X configuration */ in goya_hw_init()
2787 struct goya_device *goya = hdev->asic_specific; in goya_hw_fini()
2790 if (hdev->pldm) { in goya_hw_fini()
2813 dev_dbg(hdev->dev, in goya_hw_fini()
2818 dev_dbg(hdev->dev, in goya_hw_fini()
2832 dev_err(hdev->dev, in goya_hw_fini()
2837 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME | in goya_hw_fini()
2844 /* Chicken bit to re-initiate boot sequencer flow */ in goya_hw_fini()
2852 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | in goya_hw_fini()
2858 memset(goya->events_stat, 0, sizeof(goya->events_stat)); in goya_hw_fini()
2868 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); in goya_suspend()
2883 vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | in goya_mmap()
2886 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, in goya_mmap()
2887 (dma_addr - HOST_PHYS_BASE), size); in goya_mmap()
2889 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc); in goya_mmap()
2961 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n", in goya_ring_doorbell()
2988 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size, in goya_dma_alloc_coherent()
3002 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE; in goya_dma_free_coherent()
3004 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); in goya_dma_free_coherent()
3018 *dma_handle = hdev->asic_prop.sram_base_address; in goya_get_int_queue_base()
3020 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID]; in goya_get_int_queue_base()
3060 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); in goya_get_int_queue_base()
3079 if (hdev->pldm) in goya_send_job_on_qman0()
3084 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) { in goya_send_job_on_qman0()
3085 dev_err_ratelimited(hdev->dev, in goya_send_job_on_qman0()
3087 return -EBUSY; in goya_send_job_on_qman0()
3092 dev_err(hdev->dev, in goya_send_job_on_qman0()
3094 return -ENOMEM; in goya_send_job_on_qman0()
3099 cb = job->patched_cb; in goya_send_job_on_qman0()
3101 fence_pkt = cb->kernel_address + in goya_send_job_on_qman0()
3102 job->job_cb_size - sizeof(struct packet_msg_prot); in goya_send_job_on_qman0()
3107 fence_pkt->ctl = cpu_to_le32(tmp); in goya_send_job_on_qman0()
3108 fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL); in goya_send_job_on_qman0()
3109 fence_pkt->addr = cpu_to_le64(fence_dma_addr); in goya_send_job_on_qman0()
3112 job->job_cb_size, cb->bus_address); in goya_send_job_on_qman0()
3114 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); in goya_send_job_on_qman0()
3124 if (rc == -ETIMEDOUT) { in goya_send_job_on_qman0()
3125 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp); in goya_send_job_on_qman0()
3140 struct goya_device *goya = hdev->asic_specific; in goya_send_cpu_message()
3142 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) { in goya_send_cpu_message()
3168 dev_err(hdev->dev, in goya_test_queue()
3171 return -ENOMEM; in goya_test_queue()
3179 dev_err(hdev->dev, in goya_test_queue()
3182 rc = -ENOMEM; in goya_test_queue()
3189 fence_pkt->ctl = cpu_to_le32(tmp); in goya_test_queue()
3190 fence_pkt->value = cpu_to_le32(fence_val); in goya_test_queue()
3191 fence_pkt->addr = cpu_to_le64(fence_dma_addr); in goya_test_queue()
3197 dev_err(hdev->dev, in goya_test_queue()
3208 if (rc == -ETIMEDOUT) { in goya_test_queue()
3209 dev_err(hdev->dev, in goya_test_queue()
3212 rc = -EIO; in goya_test_queue()
3224 struct goya_device *goya = hdev->asic_specific; in goya_test_cpu_queue()
3230 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_test_cpu_queue()
3243 ret_val = -EINVAL; in goya_test_queues()
3257 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); in goya_dma_pool_zalloc()
3270 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE; in goya_dma_pool_free()
3272 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr); in goya_dma_pool_free()
3281 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address + in goya_cpu_accessible_dma_pool_alloc()
3309 while ((count + 1) < sgt->nents) { in goya_get_dma_desc_list_size()
3341 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), in goya_pin_memory_before_cs()
3342 parser->job_userptr_list, &userptr)) in goya_pin_memory_before_cs()
3347 return -ENOMEM; in goya_pin_memory_before_cs()
3349 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), in goya_pin_memory_before_cs()
3354 list_add_tail(&userptr->job_node, parser->job_userptr_list); in goya_pin_memory_before_cs()
3356 rc = hdev->asic_funcs->asic_dma_map_sgtable(hdev, userptr->sgt, dir); in goya_pin_memory_before_cs()
3358 dev_err(hdev->dev, "failed to map sgt with DMA region\n"); in goya_pin_memory_before_cs()
3362 userptr->dma_mapped = true; in goya_pin_memory_before_cs()
3363 userptr->dir = dir; in goya_pin_memory_before_cs()
3366 parser->patched_cb_size += in goya_pin_memory_before_cs()
3367 goya_get_dma_desc_list_size(hdev, userptr->sgt); in goya_pin_memory_before_cs()
3372 list_del(&userptr->job_node); in goya_pin_memory_before_cs()
3392 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_host()
3402 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n"); in goya_validate_dma_pkt_host()
3405 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3406 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3412 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n"); in goya_validate_dma_pkt_host()
3415 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3416 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3420 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n"); in goya_validate_dma_pkt_host()
3422 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3423 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3429 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n"); in goya_validate_dma_pkt_host()
3431 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_host()
3432 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_host()
3435 dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir); in goya_validate_dma_pkt_host()
3436 return -EFAULT; in goya_validate_dma_pkt_host()
3441 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_host()
3442 hdev->asic_prop.sram_user_base_address, in goya_validate_dma_pkt_host()
3443 hdev->asic_prop.sram_end_address)) { in goya_validate_dma_pkt_host()
3445 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3448 user_dma_pkt->tsize); in goya_validate_dma_pkt_host()
3449 return -EFAULT; in goya_validate_dma_pkt_host()
3453 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_host()
3454 hdev->asic_prop.dram_user_base_address, in goya_validate_dma_pkt_host()
3455 hdev->asic_prop.dram_end_address)) { in goya_validate_dma_pkt_host()
3457 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3460 user_dma_pkt->tsize); in goya_validate_dma_pkt_host()
3461 return -EFAULT; in goya_validate_dma_pkt_host()
3466 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_host()
3469 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) { in goya_validate_dma_pkt_host()
3470 dev_err(hdev->dev, in goya_validate_dma_pkt_host()
3472 return -EFAULT; in goya_validate_dma_pkt_host()
3490 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_no_host()
3495 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n"); in goya_validate_dma_pkt_no_host()
3496 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_no_host()
3497 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_no_host()
3499 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n"); in goya_validate_dma_pkt_no_host()
3500 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_validate_dma_pkt_no_host()
3501 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_validate_dma_pkt_no_host()
3505 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_no_host()
3506 hdev->asic_prop.sram_user_base_address, in goya_validate_dma_pkt_no_host()
3507 hdev->asic_prop.sram_end_address)) { in goya_validate_dma_pkt_no_host()
3508 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n", in goya_validate_dma_pkt_no_host()
3509 sram_memory_addr, user_dma_pkt->tsize); in goya_validate_dma_pkt_no_host()
3510 return -EFAULT; in goya_validate_dma_pkt_no_host()
3514 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_no_host()
3515 hdev->asic_prop.dram_user_base_address, in goya_validate_dma_pkt_no_host()
3516 hdev->asic_prop.dram_end_address)) { in goya_validate_dma_pkt_no_host()
3517 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n", in goya_validate_dma_pkt_no_host()
3518 dram_memory_addr, user_dma_pkt->tsize); in goya_validate_dma_pkt_no_host()
3519 return -EFAULT; in goya_validate_dma_pkt_no_host()
3522 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_no_host()
3535 dev_dbg(hdev->dev, "DMA packet details:\n"); in goya_validate_dma_pkt_no_mmu()
3536 dev_dbg(hdev->dev, "source == 0x%llx\n", in goya_validate_dma_pkt_no_mmu()
3537 le64_to_cpu(user_dma_pkt->src_addr)); in goya_validate_dma_pkt_no_mmu()
3538 dev_dbg(hdev->dev, "destination == 0x%llx\n", in goya_validate_dma_pkt_no_mmu()
3539 le64_to_cpu(user_dma_pkt->dst_addr)); in goya_validate_dma_pkt_no_mmu()
3540 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); in goya_validate_dma_pkt_no_mmu()
3542 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_validate_dma_pkt_no_mmu()
3550 if (user_dma_pkt->tsize == 0) { in goya_validate_dma_pkt_no_mmu()
3551 dev_err(hdev->dev, in goya_validate_dma_pkt_no_mmu()
3553 return -EINVAL; in goya_validate_dma_pkt_no_mmu()
3568 dev_dbg(hdev->dev, "DMA packet details:\n"); in goya_validate_dma_pkt_mmu()
3569 dev_dbg(hdev->dev, "source == 0x%llx\n", in goya_validate_dma_pkt_mmu()
3570 le64_to_cpu(user_dma_pkt->src_addr)); in goya_validate_dma_pkt_mmu()
3571 dev_dbg(hdev->dev, "destination == 0x%llx\n", in goya_validate_dma_pkt_mmu()
3572 le64_to_cpu(user_dma_pkt->dst_addr)); in goya_validate_dma_pkt_mmu()
3573 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); in goya_validate_dma_pkt_mmu()
3576 * WA for HW-23. in goya_validate_dma_pkt_mmu()
3580 if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 && in goya_validate_dma_pkt_mmu()
3581 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr), in goya_validate_dma_pkt_mmu()
3582 le32_to_cpu(user_dma_pkt->tsize), in goya_validate_dma_pkt_mmu()
3583 hdev->asic_prop.pmmu.start_addr, in goya_validate_dma_pkt_mmu()
3584 hdev->asic_prop.pmmu.end_addr)) { in goya_validate_dma_pkt_mmu()
3585 dev_err(hdev->dev, in goya_validate_dma_pkt_mmu()
3587 return -EFAULT; in goya_validate_dma_pkt_mmu()
3590 if (user_dma_pkt->tsize == 0) { in goya_validate_dma_pkt_mmu()
3591 dev_err(hdev->dev, in goya_validate_dma_pkt_mmu()
3593 return -EINVAL; in goya_validate_dma_pkt_mmu()
3596 parser->patched_cb_size += sizeof(*user_dma_pkt); in goya_validate_dma_pkt_mmu()
3605 struct goya_device *goya = hdev->asic_specific; in goya_validate_wreg32()
3609 reg_offset = le32_to_cpu(wreg_pkt->ctl) & in goya_validate_wreg32()
3612 dev_dbg(hdev->dev, "WREG32 packet details:\n"); in goya_validate_wreg32()
3613 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset); in goya_validate_wreg32()
3614 dev_dbg(hdev->dev, "value == 0x%x\n", in goya_validate_wreg32()
3615 le32_to_cpu(wreg_pkt->value)); in goya_validate_wreg32()
3618 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n", in goya_validate_wreg32()
3620 return -EPERM; in goya_validate_wreg32()
3626 * non-secured property in goya_validate_wreg32()
3628 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_validate_wreg32()
3634 if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) || in goya_validate_wreg32()
3635 (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) { in goya_validate_wreg32()
3637 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n", in goya_validate_wreg32()
3638 wreg_pkt->value); in goya_validate_wreg32()
3639 return -EPERM; in goya_validate_wreg32()
3651 parser->patched_cb_size = 0; in goya_validate_cb()
3654 while (cb_parsed_length < parser->user_cb_size) { in goya_validate_cb()
3659 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; in goya_validate_cb()
3662 (le64_to_cpu(user_pkt->header) & in goya_validate_cb()
3667 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); in goya_validate_cb()
3668 rc = -EINVAL; in goya_validate_cb()
3674 if (cb_parsed_length > parser->user_cb_size) { in goya_validate_cb()
3675 dev_err(hdev->dev, in goya_validate_cb()
3677 rc = -EINVAL; in goya_validate_cb()
3690 parser->patched_cb_size += pkt_size; in goya_validate_cb()
3694 dev_err(hdev->dev, in goya_validate_cb()
3696 rc = -EPERM; in goya_validate_cb()
3700 dev_err(hdev->dev, in goya_validate_cb()
3702 rc = -EPERM; in goya_validate_cb()
3706 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); in goya_validate_cb()
3707 rc = -EPERM; in goya_validate_cb()
3711 dev_err(hdev->dev, "User not allowed to use STOP\n"); in goya_validate_cb()
3712 rc = -EPERM; in goya_validate_cb()
3728 parser->patched_cb_size += pkt_size; in goya_validate_cb()
3732 dev_err(hdev->dev, "Invalid packet header 0x%x\n", in goya_validate_cb()
3734 rc = -EINVAL; in goya_validate_cb()
3745 * 2. A packet that will generate MSI-X interrupt in goya_validate_cb()
3747 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; in goya_validate_cb()
3771 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_patch_dma_packet()
3780 (user_dma_pkt->tsize == 0)) { in goya_patch_dma_packet()
3787 addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_patch_dma_packet()
3788 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_patch_dma_packet()
3793 addr = le64_to_cpu(user_dma_pkt->dst_addr); in goya_patch_dma_packet()
3794 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); in goya_patch_dma_packet()
3800 le32_to_cpu(user_dma_pkt->tsize), in goya_patch_dma_packet()
3801 parser->job_userptr_list, &userptr) == false)) { in goya_patch_dma_packet()
3802 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", in goya_patch_dma_packet()
3803 addr, user_dma_pkt->tsize); in goya_patch_dma_packet()
3804 return -EFAULT; in goya_patch_dma_packet()
3817 sgt = userptr->sgt; in goya_patch_dma_packet()
3827 while ((count + 1) < sgt->nents) { in goya_patch_dma_packet()
3845 ctl = le32_to_cpu(user_dma_pkt->ctl); in goya_patch_dma_packet()
3850 new_dma_pkt->ctl = cpu_to_le32(ctl); in goya_patch_dma_packet()
3851 new_dma_pkt->tsize = cpu_to_le32((u32) len); in goya_patch_dma_packet()
3854 new_dma_pkt->src_addr = cpu_to_le64(dma_addr); in goya_patch_dma_packet()
3855 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); in goya_patch_dma_packet()
3857 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); in goya_patch_dma_packet()
3858 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); in goya_patch_dma_packet()
3868 dev_err(hdev->dev, in goya_patch_dma_packet()
3870 return -EFAULT; in goya_patch_dma_packet()
3873 /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */ in goya_patch_dma_packet()
3874 new_dma_pkt--; in goya_patch_dma_packet()
3875 new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask); in goya_patch_dma_packet()
3890 while (cb_parsed_length < parser->user_cb_size) { in goya_patch_cb()
3896 user_pkt = parser->user_cb->kernel_address + cb_parsed_length; in goya_patch_cb()
3897 kernel_pkt = parser->patched_cb->kernel_address + in goya_patch_cb()
3901 (le64_to_cpu(user_pkt->header) & in goya_patch_cb()
3906 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id); in goya_patch_cb()
3907 rc = -EINVAL; in goya_patch_cb()
3913 if (cb_parsed_length > parser->user_cb_size) { in goya_patch_cb()
3914 dev_err(hdev->dev, in goya_patch_cb()
3916 rc = -EINVAL; in goya_patch_cb()
3937 dev_err(hdev->dev, in goya_patch_cb()
3939 rc = -EPERM; in goya_patch_cb()
3943 dev_err(hdev->dev, in goya_patch_cb()
3945 rc = -EPERM; in goya_patch_cb()
3949 dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); in goya_patch_cb()
3950 rc = -EPERM; in goya_patch_cb()
3954 dev_err(hdev->dev, "User not allowed to use STOP\n"); in goya_patch_cb()
3955 rc = -EPERM; in goya_patch_cb()
3967 dev_err(hdev->dev, "Invalid packet header 0x%x\n", in goya_patch_cb()
3969 rc = -EINVAL; in goya_patch_cb()
3991 * 2. A packet that will generate MSI-X interrupt in goya_parse_cb_mmu()
3993 parser->patched_cb_size = parser->user_cb_size + in goya_parse_cb_mmu()
3996 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, in goya_parse_cb_mmu()
3997 parser->patched_cb_size, false, false, in goya_parse_cb_mmu()
4001 dev_err(hdev->dev, in goya_parse_cb_mmu()
4007 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_mmu()
4009 if (!parser->patched_cb) { in goya_parse_cb_mmu()
4010 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); in goya_parse_cb_mmu()
4011 rc = -EFAULT; in goya_parse_cb_mmu()
4016 * The check that parser->user_cb_size <= parser->user_cb->size was done in goya_parse_cb_mmu()
4019 memcpy(parser->patched_cb->kernel_address, in goya_parse_cb_mmu()
4020 parser->user_cb->kernel_address, in goya_parse_cb_mmu()
4021 parser->user_cb_size); in goya_parse_cb_mmu()
4023 patched_cb_size = parser->patched_cb_size; in goya_parse_cb_mmu()
4026 user_cb = parser->user_cb; in goya_parse_cb_mmu()
4027 parser->user_cb = parser->patched_cb; in goya_parse_cb_mmu()
4029 parser->user_cb = user_cb; in goya_parse_cb_mmu()
4032 hl_cb_put(parser->patched_cb); in goya_parse_cb_mmu()
4036 if (patched_cb_size != parser->patched_cb_size) { in goya_parse_cb_mmu()
4037 dev_err(hdev->dev, "user CB size mismatch\n"); in goya_parse_cb_mmu()
4038 hl_cb_put(parser->patched_cb); in goya_parse_cb_mmu()
4039 rc = -EINVAL; in goya_parse_cb_mmu()
4050 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_mmu()
4066 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, in goya_parse_cb_no_mmu()
4067 parser->patched_cb_size, false, false, in goya_parse_cb_no_mmu()
4070 dev_err(hdev->dev, in goya_parse_cb_no_mmu()
4075 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_no_mmu()
4077 if (!parser->patched_cb) { in goya_parse_cb_no_mmu()
4078 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle); in goya_parse_cb_no_mmu()
4079 rc = -EFAULT; in goya_parse_cb_no_mmu()
4086 hl_cb_put(parser->patched_cb); in goya_parse_cb_no_mmu()
4095 hl_cb_destroy(&hdev->kernel_mem_mgr, handle); in goya_parse_cb_no_mmu()
4099 hl_userptr_delete_list(hdev, parser->job_userptr_list); in goya_parse_cb_no_mmu()
4106 struct asic_fixed_properties *asic_prop = &hdev->asic_prop; in goya_parse_cb_no_ext_queue()
4107 struct goya_device *goya = hdev->asic_specific; in goya_parse_cb_no_ext_queue()
4109 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_parse_cb_no_ext_queue()
4114 (u64) (uintptr_t) parser->user_cb, in goya_parse_cb_no_ext_queue()
4115 parser->user_cb_size, in goya_parse_cb_no_ext_queue()
4116 asic_prop->sram_user_base_address, in goya_parse_cb_no_ext_queue()
4117 asic_prop->sram_end_address)) in goya_parse_cb_no_ext_queue()
4121 (u64) (uintptr_t) parser->user_cb, in goya_parse_cb_no_ext_queue()
4122 parser->user_cb_size, in goya_parse_cb_no_ext_queue()
4123 asic_prop->dram_user_base_address, in goya_parse_cb_no_ext_queue()
4124 asic_prop->dram_end_address)) in goya_parse_cb_no_ext_queue()
4127 dev_err(hdev->dev, in goya_parse_cb_no_ext_queue()
4129 parser->user_cb, parser->user_cb_size); in goya_parse_cb_no_ext_queue()
4131 return -EFAULT; in goya_parse_cb_no_ext_queue()
4136 struct goya_device *goya = hdev->asic_specific; in goya_cs_parser()
4138 if (parser->queue_type == QUEUE_TYPE_INT) in goya_cs_parser()
4141 if (goya->hw_cap_initialized & HW_CAP_MMU) in goya_cs_parser()
4154 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2); in goya_add_end_of_cb_packets()
4159 cq_pkt->ctl = cpu_to_le32(tmp); in goya_add_end_of_cb_packets()
4160 cq_pkt->value = cpu_to_le32(cq_val); in goya_add_end_of_cb_packets()
4161 cq_pkt->addr = cpu_to_le64(cq_addr); in goya_add_end_of_cb_packets()
4167 cq_pkt->ctl = cpu_to_le32(tmp); in goya_add_end_of_cb_packets()
4168 cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF); in goya_add_end_of_cb_packets()
4169 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF); in goya_add_end_of_cb_packets()
4187 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4); in goya_clear_sm_regs()
4190 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4); in goya_clear_sm_regs()
4204 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n"); in goya_debugfs_read_dma()
4205 return -EPERM; in goya_debugfs_read_dma()
4210 struct goya_device *goya = hdev->asic_specific; in goya_read_pte()
4212 if (hdev->reset_info.hard_reset_pending) in goya_read_pte()
4215 return readq(hdev->pcie_bar[DDR_BAR_ID] + in goya_read_pte()
4216 (addr - goya->ddr_bar_cur_addr)); in goya_read_pte()
4221 struct goya_device *goya = hdev->asic_specific; in goya_write_pte()
4223 if (hdev->reset_info.hard_reset_pending) in goya_write_pte()
4226 writeq(val, hdev->pcie_bar[DDR_BAR_ID] + in goya_write_pte()
4227 (addr - goya->ddr_bar_cur_addr)); in goya_write_pte()
4355 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3; in goya_get_event_desc()
4359 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0; in goya_get_event_desc()
4363 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0; in goya_get_event_desc()
4374 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3; in goya_get_event_desc()
4385 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10; in goya_get_event_desc()
4389 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ; in goya_get_event_desc()
4393 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM; in goya_get_event_desc()
4397 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM; in goya_get_event_desc()
4401 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH; in goya_get_event_desc()
4412 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10; in goya_get_event_desc()
4416 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0; in goya_get_event_desc()
4431 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n"); in goya_print_razwi_info()
4436 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n"); in goya_print_razwi_info()
4441 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n"); in goya_print_razwi_info()
4446 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n"); in goya_print_razwi_info()
4453 struct goya_device *goya = hdev->asic_specific; in goya_print_mmu_error_info()
4457 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_print_mmu_error_info()
4466 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", in goya_print_mmu_error_info()
4476 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ]; in goya_print_out_of_sync_info()
4478 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n", in goya_print_out_of_sync_info()
4479 sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci)); in goya_print_out_of_sync_info()
4488 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", in goya_print_irq_info()
4510 /* data should be aligned to 8 bytes in order to CPU-CP to copy it */ in goya_unmask_irq_arr()
4515 dev_err(hdev->dev, "too many elements in IRQ array\n"); in goya_unmask_irq_arr()
4516 return -EINVAL; in goya_unmask_irq_arr()
4521 return -ENOMEM; in goya_unmask_irq_arr()
4524 pkt->length = cpu_to_le32(irq_num_entries); in goya_unmask_irq_arr()
4529 for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs; in goya_unmask_irq_arr()
4534 pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << in goya_unmask_irq_arr()
4537 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, in goya_unmask_irq_arr()
4541 dev_err(hdev->dev, "failed to unmask IRQ array\n"); in goya_unmask_irq_arr()
4570 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), in goya_unmask_irq()
4574 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); in goya_unmask_irq()
4583 mutex_lock(&hdev->clk_throttling.lock); in goya_print_clk_change_info()
4587 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4588 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4589 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get(); in goya_print_clk_change_info()
4590 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time; in goya_print_clk_change_info()
4591 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4596 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER; in goya_print_clk_change_info()
4597 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get(); in goya_print_clk_change_info()
4598 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4603 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4604 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4605 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get(); in goya_print_clk_change_info()
4606 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time; in goya_print_clk_change_info()
4607 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4612 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL; in goya_print_clk_change_info()
4613 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get(); in goya_print_clk_change_info()
4614 dev_info_ratelimited(hdev->dev, in goya_print_clk_change_info()
4619 dev_err(hdev->dev, "Received invalid clock change event %d\n", in goya_print_clk_change_info()
4624 mutex_unlock(&hdev->clk_throttling.lock); in goya_print_clk_change_info()
4629 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); in goya_handle_eqe()
4632 struct goya_device *goya = hdev->asic_specific; in goya_handle_eqe()
4635 dev_err(hdev->dev, "Event type %u exceeds maximum of %u", in goya_handle_eqe()
4636 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1); in goya_handle_eqe()
4640 goya->events_stat[event_type]++; in goya_handle_eqe()
4641 goya->events_stat_aggregate[event_type]++; in goya_handle_eqe()
4667 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4674 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4733 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err); in goya_handle_eqe()
4734 if (hdev->hard_reset_on_fw_events) in goya_handle_eqe()
4741 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", in goya_handle_eqe()
4749 struct goya_device *goya = hdev->asic_specific; in goya_get_events_stat()
4752 *size = (u32) sizeof(goya->events_stat_aggregate); in goya_get_events_stat()
4753 return goya->events_stat_aggregate; in goya_get_events_stat()
4756 *size = (u32) sizeof(goya->events_stat); in goya_get_events_stat()
4757 return goya->events_stat; in goya_get_events_stat()
4774 return -ENOMEM; in goya_memset_device_memory()
4776 lin_dma_pkt = cb->kernel_address; in goya_memset_device_memory()
4788 lin_dma_pkt->ctl = cpu_to_le32(ctl); in goya_memset_device_memory()
4790 lin_dma_pkt->src_addr = cpu_to_le64(val); in goya_memset_device_memory()
4791 lin_dma_pkt->dst_addr = cpu_to_le64(addr); in goya_memset_device_memory()
4793 lin_dma_pkt->tsize = cpu_to_le32(SZ_2G); in goya_memset_device_memory()
4795 lin_dma_pkt->tsize = cpu_to_le32(size); in goya_memset_device_memory()
4797 size -= SZ_2G; in goya_memset_device_memory()
4800 } while (--lin_dma_pkts_cnt); in goya_memset_device_memory()
4804 dev_err(hdev->dev, "Failed to allocate a new job\n"); in goya_memset_device_memory()
4805 rc = -ENOMEM; in goya_memset_device_memory()
4809 job->id = 0; in goya_memset_device_memory()
4810 job->user_cb = cb; in goya_memset_device_memory()
4811 atomic_inc(&job->user_cb->cs_cnt); in goya_memset_device_memory()
4812 job->user_cb_size = cb_size; in goya_memset_device_memory()
4813 job->hw_queue_id = GOYA_QUEUE_ID_DMA_0; in goya_memset_device_memory()
4814 job->patched_cb = job->user_cb; in goya_memset_device_memory()
4815 job->job_cb_size = job->user_cb_size; in goya_memset_device_memory()
4823 atomic_dec(&cb->cs_cnt); in goya_memset_device_memory()
4827 hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle); in goya_memset_device_memory()
4834 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_context_switch()
4835 u64 addr = prop->sram_base_address, sob_addr; in goya_context_switch()
4836 u32 size = hdev->pldm ? 0x10000 : prop->sram_size; in goya_context_switch()
4839 u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO - in goya_context_switch()
4844 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); in goya_context_switch()
4854 (dma_id - 1) * 4; in goya_context_switch()
4868 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_clear_pgt_range()
4869 struct goya_device *goya = hdev->asic_specific; in goya_mmu_clear_pgt_range()
4870 u64 addr = prop->mmu_pgt_addr; in goya_mmu_clear_pgt_range()
4871 u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE + in goya_mmu_clear_pgt_range()
4874 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_clear_pgt_range()
4882 struct goya_device *goya = hdev->asic_specific; in goya_mmu_set_dram_default_page()
4883 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr; in goya_mmu_set_dram_default_page()
4887 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_set_dram_default_page()
4895 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_add_mappings_for_device_cpu()
4896 struct goya_device *goya = hdev->asic_specific; in goya_mmu_add_mappings_for_device_cpu()
4900 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_add_mappings_for_device_cpu()
4904 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4905 prop->dram_base_address + off, in goya_mmu_add_mappings_for_device_cpu()
4906 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_add_mappings_for_device_cpu()
4909 dev_err(hdev->dev, "Map failed for address 0x%llx\n", in goya_mmu_add_mappings_for_device_cpu()
4910 prop->dram_base_address + off); in goya_mmu_add_mappings_for_device_cpu()
4915 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { in goya_mmu_add_mappings_for_device_cpu()
4916 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4918 hdev->cpu_accessible_dma_address, in goya_mmu_add_mappings_for_device_cpu()
4922 dev_err(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4924 off -= PAGE_SIZE_2MB; in goya_mmu_add_mappings_for_device_cpu()
4929 rc = hl_mmu_map_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4931 hdev->cpu_accessible_dma_address + cpu_off, in goya_mmu_add_mappings_for_device_cpu()
4934 dev_err(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4936 cpu_off -= PAGE_SIZE_4KB; in goya_mmu_add_mappings_for_device_cpu()
4950 goya->device_cpu_mmu_mappings_done = true; in goya_mmu_add_mappings_for_device_cpu()
4955 for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB) in goya_mmu_add_mappings_for_device_cpu()
4956 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4959 dev_warn_ratelimited(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4963 for (; off >= 0 ; off -= PAGE_SIZE_2MB) in goya_mmu_add_mappings_for_device_cpu()
4964 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_add_mappings_for_device_cpu()
4965 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_add_mappings_for_device_cpu()
4967 dev_warn_ratelimited(hdev->dev, in goya_mmu_add_mappings_for_device_cpu()
4969 prop->dram_base_address + off); in goya_mmu_add_mappings_for_device_cpu()
4976 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_mmu_remove_device_cpu_mappings()
4977 struct goya_device *goya = hdev->asic_specific; in goya_mmu_remove_device_cpu_mappings()
4980 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_remove_device_cpu_mappings()
4983 if (!goya->device_cpu_mmu_mappings_done) in goya_mmu_remove_device_cpu_mappings()
4989 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) { in goya_mmu_remove_device_cpu_mappings()
4990 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
4993 dev_warn(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
4997 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
5001 dev_warn_ratelimited(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
5007 if (hl_mmu_unmap_page(hdev->kernel_ctx, in goya_mmu_remove_device_cpu_mappings()
5008 prop->dram_base_address + off, PAGE_SIZE_2MB, in goya_mmu_remove_device_cpu_mappings()
5010 dev_warn_ratelimited(hdev->dev, in goya_mmu_remove_device_cpu_mappings()
5012 prop->dram_base_address + off); in goya_mmu_remove_device_cpu_mappings()
5014 goya->device_cpu_mmu_mappings_done = false; in goya_mmu_remove_device_cpu_mappings()
5019 struct goya_device *goya = hdev->asic_specific; in goya_mmu_prepare()
5022 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) in goya_mmu_prepare()
5026 dev_crit(hdev->dev, "asid %u is too big\n", asid); in goya_mmu_prepare()
5038 struct goya_device *goya = hdev->asic_specific; in goya_mmu_invalidate_cache()
5042 if (!(goya->hw_cap_initialized & HW_CAP_MMU) || in goya_mmu_invalidate_cache()
5043 hdev->reset_info.hard_reset_pending) in goya_mmu_invalidate_cache()
5050 if (hdev->pldm) in goya_mmu_invalidate_cache()
5081 struct goya_device *goya = hdev->asic_specific; in goya_send_heartbeat()
5083 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_send_heartbeat()
5091 struct goya_device *goya = hdev->asic_specific; in goya_cpucp_info_get()
5092 struct asic_fixed_properties *prop = &hdev->asic_prop; in goya_cpucp_info_get()
5096 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_cpucp_info_get()
5105 dram_size = le64_to_cpu(prop->cpucp_info.dram_size); in goya_cpucp_info_get()
5109 dev_err(hdev->dev, in goya_cpucp_info_get()
5115 prop->dram_size = dram_size; in goya_cpucp_info_get()
5116 prop->dram_end_address = prop->dram_base_address + dram_size; in goya_cpucp_info_get()
5119 if (!strlen(prop->cpucp_info.card_name)) in goya_cpucp_info_get()
5120 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME, in goya_cpucp_info_get()
5129 const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n"; in goya_is_device_idle()
5130 const char *dma_fmt = "%-5d%-9s%#-14x%#x\n"; in goya_is_device_idle()
5140 "--- ------- ------------ -------------\n"); in goya_is_device_idle()
5142 offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0; in goya_is_device_idle()
5161 "--- ------- ------------ -------------- ----------\n"); in goya_is_device_idle()
5163 offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0; in goya_is_device_idle()
5184 "--- ------- ------------ -------------- -----------\n"); in goya_is_device_idle()
5206 __acquires(&goya->hw_queues_lock) in goya_hw_queues_lock()
5208 struct goya_device *goya = hdev->asic_specific; in goya_hw_queues_lock()
5210 spin_lock(&goya->hw_queues_lock); in goya_hw_queues_lock()
5214 __releases(&goya->hw_queues_lock) in goya_hw_queues_unlock()
5216 struct goya_device *goya = hdev->asic_specific; in goya_hw_queues_unlock()
5218 spin_unlock(&goya->hw_queues_lock); in goya_hw_queues_unlock()
5223 return hdev->pdev->device; in goya_get_pci_id()
5229 struct goya_device *goya = hdev->asic_specific; in goya_get_eeprom_data()
5231 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) in goya_get_eeprom_data()
5244 if (ctx->asid != HL_KERNEL_ASID_ID) in goya_ctx_init()
5245 goya_mmu_prepare(ctx->hdev, ctx->asid); in goya_ctx_init()
5308 return -EINVAL; in goya_collective_wait_create_jobs()
5319 return -EPERM; in goya_get_hw_block_id()
5325 return -EPERM; in goya_block_mmap()
5336 return -EINVAL; in goya_ack_mmu_page_fault_or_access_error()
5349 default: return -EINVAL; in goya_map_pll_idx_to_fw_idx()
5395 hdev->state_dump_specs.props = goya_state_dump_specs_props; in goya_state_dump_init()
5396 hdev->state_dump_specs.funcs = goya_state_dump_funcs; in goya_state_dump_init()
5411 return -EOPNOTSUPP; in goya_get_monitor_dump()
5420 return -EOPNOTSUPP; in goya_scrub_device_dram()
5524 * goya_set_asic_funcs - set Goya function pointers
5531 hdev->asic_funcs = &goya_funcs; in goya_set_asic_funcs()